NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_crc_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP.I_MAC_CRC_CALC_15	100.0 % (15/15)	100.0 % (14/14)	100.0 % (108/108)	100.0 % (21/21)	N.A.	N.A.	100.0 % (158/158)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP.I_MAC_CRC_CALC_15

100.0 % (15/15)

100.0 % (14/14)

100.0 % (108/108)

100.0 % (21/21)

N.A.

100.0 % (158/158)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

150: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
Count: 5725038
Threshold: 1

If statement on lines 154 to 162:

154:        if (load_init_vect = '1') then 
155:            crc_d <= (others => '0'); 
...
161:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0'); 
162:        end if;

Count: 11786374
Threshold: 1

Signal assignment statement on line 155:

155: crc_d <= (others => '0');
Count: 195675
Threshold: 1

Signal assignment statement on line 156:

156: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
Count: 195675
Threshold: 1

Signal assignment statement on lines 158 to 159:

158:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor 
159:                      G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);

Count: 5894612
Threshold: 1

Signal assignment statement on line 161:

161: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
Count: 5696087
Threshold: 1

If statement on lines 165 to 167:

165:    crc_ce <= '1' when (load_init_vect = '1') else 
166:              '1' when (enable = '1' and trig = '1') else 
167:              '0';

Count: 21581759
Threshold: 1

Signal assignment statement on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else
Count: 113844
Threshold: 1

Signal assignment statement on line 166:

166: '1' when (enable = '1' and trig = '1') else
Count: 6234900
Threshold: 1

Signal assignment statement on line 167:

167: '0';
Count: 15233015
Threshold: 1

If statement on lines 174 to 180:

174:        if (rst_n = '0') then 
175:            crc_q             <= (others => '0'); 
...
179:            end if; 
180:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 175:

175: crc_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 177 to 179:

177:            if (crc_ce = '1') then 
178:                crc_q <= crc_d; 
179:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 178:

178: crc_q <= crc_d;
Count: 6080245
Threshold: 1

Signal assignment statement on line 184:

184: crc <= crc_q;
Count: 5835347
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	True	195675	1
Bin	False	11590699	1

"if" / "when" / "else" condition on line 157:

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	True	5894612	1
Bin	False	5696087	1

"if" / "when" / "else" condition on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	True	113844	1
Bin	False	21467915	1

"if" / "when" / "else" condition on line 166:

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	True	6234900	1
Bin	False	15233015	1

"if" / "when" / "else" condition on line 174:

174: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 176:

176: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 177:

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	6080245	1
Bin	False	541094089	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INIT_VECT_MSB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CRC

	Element	From	To	Count	Threshold
Bin	(14)	0	1	1464603	1
Bin	(14)	1	0	1466201	1
Bin	(13)	0	1	1414055	1
Bin	(13)	1	0	1415654	1
Bin	(12)	0	1	1426975	1
Bin	(12)	1	0	1428575	1
Bin	(11)	0	1	1440706	1
Bin	(11)	1	0	1442303	1
Bin	(10)	0	1	1457147	1
Bin	(10)	1	0	1458746	1
Bin	(9)	0	1	1452500	1
Bin	(9)	1	0	1454099	1
Bin	(8)	0	1	1468253	1
Bin	(8)	1	0	1469850	1
Bin	(7)	0	1	1492277	1
Bin	(7)	1	0	1493877	1
Bin	(6)	0	1	1438993	1
Bin	(6)	1	0	1440591	1
Bin	(5)	0	1	1451287	1
Bin	(5)	1	0	1452883	1
Bin	(4)	0	1	1465089	1
Bin	(4)	1	0	1466687	1
Bin	(3)	0	1	1462665	1
Bin	(3)	1	0	1464264	1
Bin	(2)	0	1	1454912	1
Bin	(2)	1	0	1456508	1
Bin	(1)	0	1	1468642	1
Bin	(1)	1	0	1470239	1
Bin	(0)	0	1	1481303	1
Bin	(0)	1	0	1482900	1

Signal:

CRC_Q

	Element	From	To	Count	Threshold
Bin	(14)	0	1	2890635	1
Bin	(14)	1	0	2943111	1
Bin	(13)	0	1	1414055	1
Bin	(13)	1	0	1415676	1
Bin	(12)	0	1	1426975	1
Bin	(12)	1	0	1428575	1
Bin	(11)	0	1	1440706	1
Bin	(11)	1	0	1442303	1
Bin	(10)	0	1	1457147	1
Bin	(10)	1	0	1458746	1
Bin	(9)	0	1	1452500	1
Bin	(9)	1	0	1454099	1
Bin	(8)	0	1	1468253	1
Bin	(8)	1	0	1469850	1
Bin	(7)	0	1	1492277	1
Bin	(7)	1	0	1493877	1
Bin	(6)	0	1	1438993	1
Bin	(6)	1	0	1440591	1
Bin	(5)	0	1	1451287	1
Bin	(5)	1	0	1452883	1
Bin	(4)	0	1	1465089	1
Bin	(4)	1	0	1466687	1
Bin	(3)	0	1	1462665	1
Bin	(3)	1	0	1464264	1
Bin	(2)	0	1	1454912	1
Bin	(2)	1	0	1456508	1
Bin	(1)	0	1	1468642	1
Bin	(1)	1	0	1470239	1
Bin	(0)	0	1	1481303	1
Bin	(0)	1	0	1482900	1

Signal:

CRC_NXT

	From	To	Count	Threshold
Bin	0	1	2861717	1
Bin	1	0	2860119	1

Signal:

CRC_D

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5867386	1
Bin	(14)	1	0	5833835	1
Bin	(13)	0	1	1426979	1
Bin	(13)	1	0	1428626	1
Bin	(12)	0	1	1440708	1
Bin	(12)	1	0	1442305	1
Bin	(11)	0	1	1457149	1
Bin	(11)	1	0	1458748	1
Bin	(10)	0	1	4387342	1
Bin	(10)	1	0	4387373	1
Bin	(9)	0	1	1468256	1
Bin	(9)	1	0	1469853	1
Bin	(8)	0	1	4426645	1
Bin	(8)	1	0	4426643	1
Bin	(7)	0	1	4371863	1
Bin	(7)	1	0	4371895	1
Bin	(6)	0	1	1451288	1
Bin	(6)	1	0	1452884	1
Bin	(5)	0	1	1465090	1
Bin	(5)	1	0	1466688	1
Bin	(4)	0	1	4396505	1
Bin	(4)	1	0	4396502	1
Bin	(3)	0	1	4390381	1
Bin	(3)	1	0	4390413	1
Bin	(2)	0	1	1468644	1
Bin	(2)	1	0	1470241	1
Bin	(1)	0	1	1481306	1
Bin	(1)	1	0	1482903	1
Bin	(0)	0	1	2947521	1
Bin	(0)	1	0	2947518	1

Signal:

CRC_CE

	From	To	Count	Threshold
Bin	0	1	6348744	1
Bin	1	0	6350345	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

 data_in xor crc_q(G_CRC_WIDTH - 1) 
 <-LHS->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1456168	1
Bin	'0'	'1'	1387008	1
Bin	'1'	'0'	1474709	1
Bin	'1'	'1'	1403951	1

"=" expression on line 154:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	11590699	1
Bin	True	195675	1

"=" expression on line 157:

crc_nxt = '1'

	Evaluated to	Count	Threshold
Bin	False	5696087	1
Bin	True	5894612	1

"=" expression on line 165:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	21467915	1
Bin	True	113844	1

"and" expression on line 166:

 enable = '1' and trig = '1' 
 <---LHS---->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	4442281	1
Bin	True	False	6217050	1
Bin	True	True	6234900	1

"=" expression on line 166:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	9015965	1
Bin	True	12451950	1

"=" expression on line 166:

trig = '1'

	Evaluated to	Count	Threshold
Bin	False	10790734	1
Bin	True	10677181	1

"=" expression on line 174:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 177:

crc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	541094089	1
Bin	True	6080245	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP.I_MAC_CRC_CALC_15

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_crc_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

If statement on lines 154 to 162:

Signal assignment statement on line 155:

Signal assignment statement on line 156:

Signal assignment statement on lines 158 to 159:

Signal assignment statement on line 161:

If statement on lines 165 to 167:

Signal assignment statement on line 165:

Signal assignment statement on line 166:

Signal assignment statement on line 167:

If statement on lines 174 to 180:

Signal assignment statement on line 175:

If statement on lines 177 to 179:

Signal assignment statement on line 178:

Signal assignment statement on line 184:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

"if" / "when" / "else" condition on line 157:

"if" / "when" / "else" condition on line 165:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 176:

"if" / "when" / "else" condition on line 177:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

"=" expression on line 154:

"=" expression on line 157:

"=" expression on line 165:

"and" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 174:

"=" expression on line 177:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: