NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_DFF_ENA_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
I_DFF_FIXED_STUFF_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)
I_DFF_DATA_OUT_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)
I_DFF_HALT_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_DFF_ENA_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

I_DFF_FIXED_STUFF_REG

100.0 % (4/4)

100.0 % (6/6)

100.0 % (10/10)

100.0 % (4/4)

N.A.

100.0 % (24/24)

I_DFF_DATA_OUT_REG

100.0 % (4/4)

100.0 % (6/6)

100.0 % (10/10)

100.0 % (4/4)

N.A.

100.0 % (24/24)

I_DFF_HALT_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_BIT_STUFFING	100.0 % (63/63)	100.0 % (56/56)	100.0 % (92/92)	100.0 % (115/115)	N.A.	N.A.	100.0 % (326/326)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_BIT_STUFFING

100.0 % (63/63)

100.0 % (56/56)

100.0 % (92/92)

100.0 % (115/115)

N.A.

100.0 % (326/326)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 227 to 229:

227:    non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0') 
228:                               else 
229:                           '0';

Count: 46247
Threshold: 1

Signal assignment statement on line 227:

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')
Count: 13027
Threshold: 1

Signal assignment statement on line 229:

229: '0';
Count: 33220
Threshold: 1

If statement on lines 236 to 238:

236:    fixed_reg_d <= '0'         when (enable_prev = '0') else 
237:                   fixed_stuff when (bst_trigger = '1') else 
238:                   fixed_reg_q;

Count: 22962071
Threshold: 1

Signal assignment statement on line 236:

236: fixed_reg_d <= '0' when (enable_prev = '0') else
Count: 17231680
Threshold: 1

Signal assignment statement on line 237:

237: fixed_stuff when (bst_trigger = '1') else
Count: 2852882
Threshold: 1

Signal assignment statement on line 238:

238: fixed_reg_q;
Count: 2877509
Threshold: 1

Signal assignment statement on line 261:

261: bst_ctr_add <= (bst_ctr_q + 1) mod 8;
Count: 298951
Threshold: 1

If statement on lines 269 to 272:

269:    bst_ctr_d <=        "000" when (enable_prev = '0') else 
270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
271:                                    fixed_stuff = '0') else 
272:                    bst_ctr_q;

Count: 23873888
Threshold: 1

Signal assignment statement on line 269:

269: bst_ctr_d <= "000" when (enable_prev = '0') else
Count: 17241920
Threshold: 1

Signal assignment statement on line 270:

270: bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and
Count: 821677
Threshold: 1

Signal assignment statement on line 272:

272: bst_ctr_q;
Count: 5810291
Threshold: 1

If statement on lines 279 to 285:

279:        if (rst_n = '0') then 
280:            bst_ctr_q <= (others => '0'); 
...
284:            end if; 
285:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 280:

280: bst_ctr_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 282 to 284:

282:            if (stuff_enable = '1') then 
283:                bst_ctr_q <= bst_ctr_d; 
284:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 283:

283: bst_ctr_q <= bst_ctr_d;
Count: 157839379
Threshold: 1

If statement on lines 294 to 298:

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or 
296:                                   (data_in /= data_out_i and fixed_stuff = '0') 
297:                              else 
298:                          '0';

Count: 3245872
Threshold: 1

Signal assignment statement on line 294:

294: same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or
Count: 1857572
Threshold: 1

Signal assignment statement on line 298:

298: '0';
Count: 1388300
Threshold: 1

If statement on lines 305 to 308:

305:    same_bits_rst <= '1' when (enable_prev = '0') or 
306:                              (bst_trigger = '1' and same_bits_rst_trig = '1') 
307:                         else 
308:                     '0';

Count: 24707888
Threshold: 1

Signal assignment statement on line 305:

305: same_bits_rst <= '1' when (enable_prev = '0') or
Count: 18851657
Threshold: 1

Signal assignment statement on line 308:

308: '0';
Count: 5856231
Threshold: 1

Signal assignment statement on line 313:

313: same_bits_add <= (same_bits_q + 1) mod 8;
Count: 2306679
Threshold: 1

If statement on lines 321 to 322:

321:    tx_no_sof_val <= "10" when (data_in = DOMINANT) else 
322:                     "01";

Count: 1296894
Threshold: 1

Signal assignment statement on line 321:

321: tx_no_sof_val <= "10" when (data_in = DOMINANT) else
Count: 646847
Threshold: 1

Signal assignment statement on line 322:

322: "01";
Count: 650047
Threshold: 1

If statement on lines 331 to 334:

331:    same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else 
332:                                   "001" when (same_bits_rst = '1') else 
333:                           same_bits_add when (bst_trigger = '1') else 
334:                             same_bits_q;

Count: 30720272
Threshold: 1

Signal assignment statement on line 331:

331: same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else
Count: 1656
Threshold: 1

Signal assignment statement on line 332:

332: "001" when (same_bits_rst = '1') else
Count: 20312197
Threshold: 1

Signal assignment statement on line 333:

333: same_bits_add when (bst_trigger = '1') else
Count: 7325958
Threshold: 1

Signal assignment statement on line 334:

334: same_bits_q;
Count: 3080461
Threshold: 1

If statement on lines 346 to 348:

346:    stuff_lvl_reached <= '1' when (same_bits_q = "101") 
347:                             else 
348:                         '0';

Count: 2306679
Threshold: 1

Signal assignment statement on line 346:

346: stuff_lvl_reached <= '1' when (same_bits_q = "101")
Count: 311694
Threshold: 1

Signal assignment statement on line 348:

348: '0';
Count: 1994985
Threshold: 1

If statement on lines 355 to 363:

355:        if (rst_n = '0') then 
356:            same_bits_q <= "001"; 
...
362:            end if; 
363:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 356:

356: same_bits_q <= "001";
Count: 2422674
Threshold: 1

If statement on lines 358 to 362:

358:            if (stuff_enable = '1') then 
359:                same_bits_q <= same_bits_d; 
360:            else 
361:                same_bits_q <= "001"; 
362:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 359:

359: same_bits_q <= same_bits_d;
Count: 157839379
Threshold: 1

Signal assignment statement on line 361:

361: same_bits_q <= "001";
Count: 389334955
Threshold: 1

If statement on lines 371 to 373:

371:    insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') 
372:                            else 
373:                        '0';

Count: 651882
Threshold: 1

Signal assignment statement on line 371:

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')
Count: 324721
Threshold: 1

Signal assignment statement on line 373:

373: '0';
Count: 327161
Threshold: 1

If statement on lines 382 to 384:

382:    data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else 
383:                              data_in  when (bst_trigger = '1') else 
384:                           data_out_i;

Count: 26087472
Threshold: 1

Signal assignment statement on line 382:

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else
Count: 1330833
Threshold: 1

Signal assignment statement on line 383:

383: data_in when (bst_trigger = '1') else
Count: 12982621
Threshold: 1

Signal assignment statement on line 384:

384: data_out_i;
Count: 11774018
Threshold: 1

If statement on lines 386 to 388:

386:    data_out_d <= data_out_d_ena when (stuff_enable = '1') else 
387:                         data_in when (bst_trigger = '1') else 
388:                      data_out_i;

Count: 28816014
Threshold: 1

Signal assignment statement on line 386:

386: data_out_d <= data_out_d_ena when (stuff_enable = '1') else
Count: 11061222
Threshold: 1

Signal assignment statement on line 387:

387: data_in when (bst_trigger = '1') else
Count: 8875669
Threshold: 1

Signal assignment statement on line 388:

388: data_out_i;
Count: 8879123
Threshold: 1

If statement on lines 390 to 391:

390:    data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else 
391:                     '0';

Count: 22919878
Threshold: 1

Signal assignment statement on line 390:

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else
Count: 14290970
Threshold: 1

Signal assignment statement on line 391:

391: '0';
Count: 8628908
Threshold: 1

If statement on lines 421 to 424:

421:    data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else 
422:                   '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else 
423:                   '0' when (bst_trigger = '1') else 
424:                   data_halt_q;

Count: 24250720
Threshold: 1

Signal assignment statement on line 421:

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else
Count: 17288268
Threshold: 1

Signal assignment statement on line 422:

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else
Count: 947582
Threshold: 1

Signal assignment statement on line 423:

423: '0' when (bst_trigger = '1') else
Count: 3145818
Threshold: 1

Signal assignment statement on line 424:

424: data_halt_q;
Count: 2869052
Threshold: 1

If statement on lines 432 to 433:

432:    data_halt <= data_halt_q when (data_halt_q = data_halt_d) else 
433:                 data_halt_d;

Count: 2535855
Threshold: 1

Signal assignment statement on line 432:

432: data_halt <= data_halt_q when (data_halt_q = data_halt_d) else
Count: 1268728
Threshold: 1

Signal assignment statement on line 433:

433: data_halt_d;
Count: 1267127
Threshold: 1

Signal assignment statement on line 454:

454: bst_ctr <= std_logic_vector(bst_ctr_q);
Count: 298951
Threshold: 1

Signal assignment statement on line 455:

455: data_out <= data_out_i;
Count: 1276992
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 227:

227: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_reg_q = '0')

	Evaluated to	Count	Threshold
Bin	True	13027	1
Bin	False	33220	1

"if" / "when" / "else" condition on line 236:

236: fixed_reg_d <= '0' when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	17231680	1
Bin	False	5730391	1

"if" / "when" / "else" condition on line 237:

237: fixed_stuff when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	2852882	1
Bin	False	2877509	1

"if" / "when" / "else" condition on line 269:

269: bst_ctr_d <= "000" when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	17241920	1
Bin	False	6631968	1

"if" / "when" / "else" condition on lines 270 to 271:

270:                  bst_ctr_add when (bst_trigger = '1' and stuff_lvl_reached = '1' and 
271:                                    fixed_stuff = '0') else

	Evaluated to	Count	Threshold
Bin	True	821677	1
Bin	False	5810291	1

"if" / "when" / "else" condition on line 279:

279: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 281:

281: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 282:

282: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	157839379	1
Bin	False	389334955	1

"if" / "when" / "else" condition on lines 294 to 296:

294:    same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or 
295:                                   (stuff_lvl_reached = '1') or 
296:                                   (data_in /= data_out_i and fixed_stuff = '0')

	Evaluated to	Count	Threshold
Bin	True	1857572	1
Bin	False	1388300	1

"if" / "when" / "else" condition on lines 305 to 306:

305:    same_bits_rst <= '1' when (enable_prev = '0') or 
306:                              (bst_trigger = '1' and same_bits_rst_trig = '1')

	Evaluated to	Count	Threshold
Bin	True	18851657	1
Bin	False	5856231	1

"if" / "when" / "else" condition on line 321:

321: tx_no_sof_val <= "10" when (data_in = DOMINANT) else

	Evaluated to	Count	Threshold
Bin	True	646847	1
Bin	False	650047	1

"if" / "when" / "else" condition on line 331:

331: same_bits_d <= ('0' & tx_no_sof_val) when (tx_frame_no_sof = '1') else

	Evaluated to	Count	Threshold
Bin	True	1656	1
Bin	False	30718616	1

"if" / "when" / "else" condition on line 332:

332: "001" when (same_bits_rst = '1') else

	Evaluated to	Count	Threshold
Bin	True	20312197	1
Bin	False	10406419	1

"if" / "when" / "else" condition on line 333:

333: same_bits_add when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	7325958	1
Bin	False	3080461	1

"if" / "when" / "else" condition on line 346:

346: stuff_lvl_reached <= '1' when (same_bits_q = "101")

	Evaluated to	Count	Threshold
Bin	True	311694	1
Bin	False	1994985	1

"if" / "when" / "else" condition on line 355:

355: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 357:

357: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 358:

358: if (stuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	157839379	1
Bin	False	389334955	1

"if" / "when" / "else" condition on line 371:

371: insert_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')

	Evaluated to	Count	Threshold
Bin	True	324721	1
Bin	False	327161	1

"if" / "when" / "else" condition on line 382:

382: data_out_d_ena <= (not data_out_i) when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	1330833	1
Bin	False	24756639	1

"if" / "when" / "else" condition on line 383:

383: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	12982621	1
Bin	False	11774018	1

"if" / "when" / "else" condition on line 386:

386: data_out_d <= data_out_d_ena when (stuff_enable = '1') else

	Evaluated to	Count	Threshold
Bin	True	11061222	1
Bin	False	17754792	1

"if" / "when" / "else" condition on line 387:

387: data_in when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	8875669	1
Bin	False	8879123	1

"if" / "when" / "else" condition on line 390:

390: data_out_ce <= '1' when (stuff_enable = '1' or bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	14290970	1
Bin	False	8628908	1

"if" / "when" / "else" condition on line 421:

421: data_halt_d <= '0' when (enable_prev = '0' or stuff_enable = '0') else

	Evaluated to	Count	Threshold
Bin	True	17288268	1
Bin	False	6962452	1

"if" / "when" / "else" condition on line 422:

422: '1' when (bst_trigger = '1' and insert_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	947582	1
Bin	False	6014870	1

"if" / "when" / "else" condition on line 423:

423: '0' when (bst_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	3145818	1
Bin	False	2869052	1

"if" / "when" / "else" condition on line 432:

432: data_halt <= data_halt_q when (data_halt_q = data_halt_d) else

	Evaluated to	Count	Threshold
Bin	True	1268728	1
Bin	False	1267127	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BST_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STUFF_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

FIXED_STUFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_FRAME_NO_SOF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

DATA_OUT

	From	To	Count	Threshold
Bin	0	1	638495	1
Bin	1	0	636896	1

Port:

BST_CTR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33793	1
Bin	(2)	1	0	35393	1
Bin	(1)	0	1	71746	1
Bin	(1)	1	0	73346	1
Bin	(0)	0	1	142471	1
Bin	(0)	1	0	144071	1

Port:

DATA_HALT

	From	To	Count	Threshold
Bin	0	1	947582	1
Bin	1	0	949183	1

Signal:

DATA_OUT_I

	From	To	Count	Threshold
Bin	0	1	638495	1
Bin	1	0	636896	1

Signal:

SAME_BITS_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	356433	1
Bin	(2)	1	0	358034	1
Bin	(1)	0	1	599433	1
Bin	(1)	1	0	601034	1
Bin	(0)	0	1	957467	1
Bin	(0)	1	0	955866	1

Signal:

SAME_BITS_ADD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	436484	1
Bin	(2)	1	0	438085	1
Bin	(1)	0	1	438085	1
Bin	(1)	1	0	436484	1
Bin	(0)	0	1	955866	1
Bin	(0)	1	0	957467	1

Signal:

SAME_BITS_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	1179396	1
Bin	(2)	1	0	1180997	1
Bin	(1)	0	1	3281390	1
Bin	(1)	1	0	3282991	1
Bin	(0)	0	1	4670015	1
Bin	(0)	1	0	4668414	1

Signal:

TX_NO_SOF_VAL

	Element	From	To	Count	Threshold
Bin	(1)	0	1	646847	1
Bin	(1)	1	0	648446	1
Bin	(0)	0	1	648446	1
Bin	(0)	1	0	646847	1

Signal:

DATA_HALT_Q

	From	To	Count	Threshold
Bin	0	1	317944	1
Bin	1	0	319545	1

Signal:

DATA_HALT_D

	From	To	Count	Threshold
Bin	0	1	947582	1
Bin	1	0	949183	1

Signal:

FIXED_REG_Q

	From	To	Count	Threshold
Bin	0	1	7695	1
Bin	1	0	9296	1

Signal:

FIXED_REG_D

	From	To	Count	Threshold
Bin	0	1	7695	1
Bin	1	0	9296	1

Signal:

BST_CTR_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33793	1
Bin	(2)	1	0	35393	1
Bin	(1)	0	1	71746	1
Bin	(1)	1	0	73346	1
Bin	(0)	0	1	142471	1
Bin	(0)	1	0	144071	1

Signal:

BST_CTR_ADD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	37917	1
Bin	(2)	1	0	39517	1
Bin	(1)	0	1	78035	1
Bin	(1)	1	0	79634	1
Bin	(0)	0	1	144071	1
Bin	(0)	1	0	142471	1

Signal:

BST_CTR_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	93167	1
Bin	(2)	1	0	94768	1
Bin	(1)	0	1	203296	1
Bin	(1)	1	0	204897	1
Bin	(0)	0	1	417288	1
Bin	(0)	1	0	418889	1

Signal:

ENABLE_PREV

	From	To	Count	Threshold
Bin	0	1	25501	1
Bin	1	0	27102	1

Signal:

NON_FIX_TO_FIX_CHNG

	From	To	Count	Threshold
Bin	0	1	13027	1
Bin	1	0	14628	1

Signal:

STUFF_LVL_REACHED

	From	To	Count	Threshold
Bin	0	1	311694	1
Bin	1	0	313295	1

Signal:

SAME_BITS_RST_TRIG

	From	To	Count	Threshold
Bin	0	1	1233315	1
Bin	1	0	1234916	1

Signal:

SAME_BITS_RST

	From	To	Count	Threshold
Bin	0	1	1467931	1
Bin	1	0	1467931	1

Signal:

INSERT_STUFF_BIT

	From	To	Count	Threshold
Bin	0	1	323959	1
Bin	1	0	325560	1

Signal:

DATA_OUT_D_ENA

	From	To	Count	Threshold
Bin	0	1	2153193	1
Bin	1	0	2151594	1

Signal:

DATA_OUT_D

	From	To	Count	Threshold
Bin	0	1	2007968	1
Bin	1	0	2006369	1

Signal:

DATA_OUT_CE

	From	To	Count	Threshold
Bin	0	1	8624108	1
Bin	1	0	8625706	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 227:

 fixed_stuff = '1' and fixed_reg_q = '0' 
 <------LHS------>     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	14628	1
Bin	True	False	7695	1
Bin	True	True	13027	1

"=" expression on line 227:

fixed_stuff = '1'

	Evaluated to	Count	Threshold
Bin	False	25525	1
Bin	True	20722	1

"=" expression on line 227:

fixed_reg_q = '0'

	Evaluated to	Count	Threshold
Bin	False	18592	1
Bin	True	27655	1

"=" expression on line 236:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	5730391	1
Bin	True	17231680	1

"=" expression on line 237:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2877509	1
Bin	True	2852882	1

"=" expression on line 269:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	6631968	1
Bin	True	17241920	1

"and" expression on lines 270 to 271:

 bst_trigger = '1' and stuff_lvl_reached = '1' and fixed_stuff = '0' 
 <--------------------LHS-------------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	5323909	1
Bin	True	False	74679	1
Bin	True	True	821677	1

"and" expression on line 270:

 bst_trigger = '1' and stuff_lvl_reached = '1' 
 <------LHS------>     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	312609	1
Bin	True	False	2838140	1
Bin	True	True	896356	1

"=" expression on line 270:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2897472	1
Bin	True	3734496	1

"=" expression on line 270:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	5423003	1
Bin	True	1208965	1

"=" expression on line 271:

fixed_stuff = '0'

	Evaluated to	Count	Threshold
Bin	False	486382	1
Bin	True	6145586	1

"=" expression on line 279:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 282:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	389334955	1
Bin	True	157839379	1

"or" expression on lines 294 to 296:

 (non_fix_to_fix_chng = '1') or (stuff_lvl_reached = '1') or (data_in /= data_out_i and fixed_stuff = '0') 
 <-------------------------LHS-------------------------->     <-------------------RHS------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	1388300	1
Bin	False	True	959530	1
Bin	True	False	622567	1

"or" expression on lines 294 to 295:

 (non_fix_to_fix_chng = '1') or (stuff_lvl_reached = '1') 
  <----------LHS---------->      <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	2347830	1
Bin	False	True	871988	1
Bin	True	False	24530	1

"=" expression on line 294:

non_fix_to_fix_chng = '1'

	Evaluated to	Count	Threshold
Bin	False	3219818	1
Bin	True	26054	1

"=" expression on line 295:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	2372360	1
Bin	True	873512	1

"and" expression on line 296:

 data_in /= data_out_i and fixed_stuff = '0' 
 <--------LHS-------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	1694890	1
Bin	True	False	131831	1
Bin	True	True	1235005	1

"/=" expression on line 296:

data_in /= data_out_i

	Evaluated to	Count	Threshold
Bin	False	1879036	1
Bin	True	1366836	1

"=" expression on line 296:

fixed_stuff = '0'

	Evaluated to	Count	Threshold
Bin	False	315977	1
Bin	True	2929895	1

"or" expression on lines 305 to 306:

 (enable_prev = '0') or (bst_trigger = '1' and same_bits_rst_trig = '1') 
  <------LHS------>      <--------------------RHS--------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	5856231	1
Bin	False	True	1443215	1
Bin	True	False	17197560	1

"=" expression on line 305:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	7299446	1
Bin	True	17408442	1

"and" expression on line 306:

 bst_trigger = '1' and same_bits_rst_trig = '1' 
 <------LHS------>     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	1458456	1
Bin	True	False	11239731	1
Bin	True	True	1654097	1

"=" expression on line 306:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11814060	1
Bin	True	12893828	1

"=" expression on line 306:

same_bits_rst_trig = '1'

	Evaluated to	Count	Threshold
Bin	False	21595335	1
Bin	True	3112553	1

"=" expression on line 321:

data_in = DOMINANT

	Evaluated to	Count	Threshold
Bin	False	650047	1
Bin	True	646847	1

"=" expression on line 331:

tx_frame_no_sof = '1'

	Evaluated to	Count	Threshold
Bin	False	30718616	1
Bin	True	1656	1

"=" expression on line 332:

same_bits_rst = '1'

	Evaluated to	Count	Threshold
Bin	False	10406419	1
Bin	True	20312197	1

"=" expression on line 333:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	3080461	1
Bin	True	7325958	1

"=" expression on line 355:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 358:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	389334955	1
Bin	True	157839379	1

"or" expression on line 371:

 non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1' 
 <----------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	327161	1
Bin	False	True	311694	1
Bin	True	False	12265	1

"=" expression on line 371:

non_fix_to_fix_chng = '1'

	Evaluated to	Count	Threshold
Bin	False	638855	1
Bin	True	13027	1

"=" expression on line 371:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	339426	1
Bin	True	312456	1

"and" expression on line 382:

 bst_trigger = '1' and insert_stuff_bit = '1' 
 <------LHS------>     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	480345	1
Bin	True	False	12982621	1
Bin	True	True	1330833	1

"=" expression on line 382:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11774018	1
Bin	True	14313454	1

"=" expression on line 382:

insert_stuff_bit = '1'

	Evaluated to	Count	Threshold
Bin	False	24276294	1
Bin	True	1811178	1

"=" expression on line 383:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11774018	1
Bin	True	12982621	1

"=" expression on line 386:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	17754792	1
Bin	True	11061222	1

"=" expression on line 387:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	8879123	1
Bin	True	8875669	1

"or" expression on line 390:

 stuff_enable = '1' or bst_trigger = '1' 
 <------LHS------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	8628908	1
Bin	False	True	8598607	1
Bin	True	False	2858932	1

"=" expression on line 390:

stuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	17227515	1
Bin	True	5692363	1

"=" expression on line 390:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11487840	1
Bin	True	11432038	1

"or" expression on line 421:

 enable_prev = '0' or stuff_enable = '0' 
 <------LHS------>    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	6962452	1
Bin	False	True	30484	1
Bin	True	False	25516	1

"=" expression on line 421:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	6992936	1
Bin	True	17257784	1

"=" expression on line 421:

stuff_enable = '0'

	Evaluated to	Count	Threshold
Bin	False	6987968	1
Bin	True	17262752	1

"and" expression on line 422:

 bst_trigger = '1' and insert_stuff_bit = '1' 
 <------LHS------>     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	318627	1
Bin	True	False	3145818	1
Bin	True	True	947582	1

"=" expression on line 422:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2869052	1
Bin	True	4093400	1

"=" expression on line 422:

insert_stuff_bit = '1'

	Evaluated to	Count	Threshold
Bin	False	5696243	1
Bin	True	1266209	1

"=" expression on line 423:

bst_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	2869052	1
Bin	True	3145818	1

"=" expression on line 432:

data_halt_q = data_halt_d

	Evaluated to	Count	Threshold
Bin	False	1267127	1
Bin	True	1268728	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_BIT_STUFFING

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 227 to 229:

Signal assignment statement on line 227:

Signal assignment statement on line 229:

If statement on lines 236 to 238:

Signal assignment statement on line 236:

Signal assignment statement on line 237:

Signal assignment statement on line 238:

Signal assignment statement on line 261:

If statement on lines 269 to 272:

Signal assignment statement on line 269:

Signal assignment statement on line 270:

Signal assignment statement on line 272:

If statement on lines 279 to 285:

Signal assignment statement on line 280:

If statement on lines 282 to 284:

Signal assignment statement on line 283:

If statement on lines 294 to 298:

Signal assignment statement on line 294:

Signal assignment statement on line 298:

If statement on lines 305 to 308:

Signal assignment statement on line 305:

Signal assignment statement on line 308:

Signal assignment statement on line 313:

If statement on lines 321 to 322:

Signal assignment statement on line 321:

Signal assignment statement on line 322:

If statement on lines 331 to 334:

Signal assignment statement on line 331:

Signal assignment statement on line 332:

Signal assignment statement on line 333:

Signal assignment statement on line 334:

If statement on lines 346 to 348:

Signal assignment statement on line 346:

Signal assignment statement on line 348:

If statement on lines 355 to 363:

Signal assignment statement on line 356:

If statement on lines 358 to 362:

Signal assignment statement on line 359:

Signal assignment statement on line 361:

If statement on lines 371 to 373:

Signal assignment statement on line 371:

Signal assignment statement on line 373:

If statement on lines 382 to 384:

Signal assignment statement on line 382:

Signal assignment statement on line 383:

Signal assignment statement on line 384:

If statement on lines 386 to 388:

Signal assignment statement on line 386:

Signal assignment statement on line 387:

Signal assignment statement on line 388:

If statement on lines 390 to 391:

Signal assignment statement on line 390:

Signal assignment statement on line 391:

If statement on lines 421 to 424:

Signal assignment statement on line 421:

Signal assignment statement on line 422:

Signal assignment statement on line 423:

Signal assignment statement on line 424:

If statement on lines 432 to 433:

Signal assignment statement on line 432:

Signal assignment statement on line 433:

Signal assignment statement on line 454:

Signal assignment statement on line 455:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 227:

"if" / "when" / "else" condition on line 236:

"if" / "when" / "else" condition on line 237:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on lines 270 to 271:

"if" / "when" / "else" condition on line 279: