| Current Instance | Statement | Branch | Toggle | Expression | FSM state | Functional | Average |
|---|---|---|---|---|---|---|---|
| CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_OPERATION_CONTROL | 100.0 % (28/28) | 100.0 % (32/32) | 100.0 % (24/24) | 100.0 % (32/32) | 100.0 % (8/8) | N.A. | 100.0 % (124/124) |
| Statement | Branch | Toggle | Expression | FSM state | Functional |
|---|
151: go_to_off <= '1' when (is_bus_off = '1') and (rx_trigger = '1')
152: else
153: '0'; 151: go_to_off <= '1' when (is_bus_off = '1') and (rx_trigger = '1') 153: '0'; 161: next_state <= curr_state; 163: case curr_state is
164: when s_oc_off =>
...
192: end if;
193: end case; 165: if (set_idle = '1') then
166: next_state <= s_oc_idle;
167: end if; 166: next_state <= s_oc_idle; 170: if (go_to_off = '1') then
171: next_state <= s_oc_off;
...
175: next_state <= s_oc_receiver;
176: end if; 171: next_state <= s_oc_off; 173: next_state <= s_oc_transmitter; 175: next_state <= s_oc_receiver; 179: if (go_to_off = '1') then
180: next_state <= s_oc_off;
...
184: next_state <= s_oc_receiver;
185: end if; 180: next_state <= s_oc_off; 182: next_state <= s_oc_idle; 184: next_state <= s_oc_receiver; 188: if (set_idle = '1') then
189: next_state <= s_oc_idle;
190: elsif (set_transmitter = '1') then
191: next_state <= s_oc_transmitter;
192: end if; 189: next_state <= s_oc_idle; 191: next_state <= s_oc_transmitter; 202: is_idle <= '0'; 203: is_transmitter <= '0'; 204: is_receiver <= '0'; 206: case curr_state is
207: when s_oc_off =>
...
213: is_receiver <= '1';
214: end case; 209: is_idle <= '1'; 211: is_transmitter <= '1'; 213: is_receiver <= '1'; 222: if (rst_n = '0') then
223: curr_state <= s_oc_off;
224: elsif (rising_edge(clk_sys)) then
225: curr_state <= next_state;
226: end if; 223: curr_state <= s_oc_off; 225: curr_state <= next_state; 151: go_to_off <= '1' when (is_bus_off = '1') and (rx_trigger = '1') | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 319332 | 1 |
| Bin | False | 20500864 | 1 |
164: when s_oc_off => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_off | 643379 | 1 |
165: if (set_idle = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 6639 | 1 |
| Bin | False | 636740 | 1 |
169: when s_oc_idle => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_idle | 170780 | 1 |
170: if (go_to_off = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 6770 | 1 |
| Bin | False | 164010 | 1 |
172: elsif (set_transmitter = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 20039 | 1 |
| Bin | False | 143971 | 1 |
174: elsif (set_receiver = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 30051 | 1 |
| Bin | False | 113920 | 1 |
178: when s_oc_transmitter => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_transmitter | 121340 | 1 |
179: if (go_to_off = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 112 | 1 |
| Bin | False | 121228 | 1 |
181: elsif (set_idle = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 29498 | 1 |
| Bin | False | 91730 | 1 |
183: elsif (set_receiver = '1' or arbitration_lost = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 1175 | 1 |
| Bin | False | 90555 | 1 |
187: when s_oc_receiver => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_receiver | 147230 | 1 |
188: if (set_idle = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 56670 | 1 |
| Bin | False | 90560 | 1 |
190: elsif (set_transmitter = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 1067 | 1 |
| Bin | False | 89493 | 1 |
207: when s_oc_off => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_off | 8227 | 1 |
208: when s_oc_idle => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_idle | 56100 | 1 |
210: when s_oc_transmitter => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_transmitter | 20560 | 1 |
212: when s_oc_receiver => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_oc_receiver | 30873 | 1 |
222: if (rst_n = '0') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 2422674 | 1 |
| Bin | False | 1094358647 | 1 |
224: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 547174334 | 1 |
| Bin | False | 547184313 | 1 |
CLK_SYS| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
RST_N| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
RX_TRIGGER| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
IS_BUS_OFF| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
ARBITRATION_LOST| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
SET_TRANSMITTER| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
SET_RECEIVER| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
SET_IDLE| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
IS_TRANSMITTER| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20560 | 1 |
| Bin | 1 | 0 | 22161 | 1 |
IS_RECEIVER| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30873 | 1 |
| Bin | 1 | 0 | 32467 | 1 |
IS_IDLE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56100 | 1 |
| Bin | 1 | 0 | 57697 | 1 |
GO_TO_OFF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 319332 | 1 |
| Bin | 1 | 0 | 320933 | 1 |
(is_bus_off = '1') and (rx_trigger = '1')
<-----LHS------> <-----RHS------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 10088548 | 1 |
| Bin | True | False | 320744 | 1 |
| Bin | True | True | 319332 | 1 |
is_bus_off = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 20180120 | 1 |
| Bin | True | 640076 | 1 |
rx_trigger = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 10412316 | 1 |
| Bin | True | 10407880 | 1 |
set_idle = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 636740 | 1 |
| Bin | True | 6639 | 1 |
go_to_off = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 164010 | 1 |
| Bin | True | 6770 | 1 |
set_transmitter = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 143971 | 1 |
| Bin | True | 20039 | 1 |
set_receiver = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 113920 | 1 |
| Bin | True | 30051 | 1 |
go_to_off = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 121228 | 1 |
| Bin | True | 112 | 1 |
set_idle = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 91730 | 1 |
| Bin | True | 29498 | 1 |
set_receiver = '1' or arbitration_lost = '1'
<------LHS-------> <--------RHS---------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 90555 | 1 |
| Bin | False | True | 1066 | 1 |
| Bin | True | False | 109 | 1 |
set_receiver = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 91621 | 1 |
| Bin | True | 109 | 1 |
arbitration_lost = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 90664 | 1 |
| Bin | True | 1066 | 1 |
set_idle = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 90560 | 1 |
| Bin | True | 56670 | 1 |
set_transmitter = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 89493 | 1 |
| Bin | True | 1067 | 1 |
rst_n = '0' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 1094358647 | 1 |
| Bin | True | 2422674 | 1 |
138: signal curr_state : t_operation_control_state; | State | Count | Threshold | |
|---|---|---|---|
| Bin | S_OC_OFF | 8227 | 1 |
| Bin | S_OC_IDLE | 56100 | 1 |
| Bin | S_OC_TRANSMITTER | 20560 | 1 |
| Bin | S_OC_RECEIVER | 30873 | 1 |
139: signal next_state : t_operation_control_state; | State | Count | Threshold | |
|---|---|---|---|
| Bin | S_OC_OFF | 14866 | 1 |
| Bin | S_OC_IDLE | 99467 | 1 |
| Bin | S_OC_TRANSMITTER | 31736 | 1 |
| Bin | S_OC_RECEIVER | 58175 | 1 |