NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_CAN_RX_SIG_SYNC	100.0 % (5/5)	100.0 % (4/4)	100.0 % (10/10)	100.0 % (2/2)	N.A.	N.A.	100.0 % (21/21)
I_BM_TRV_DELAY_MEAS	100.0 % (42/42)	100.0 % (37/37)	100.0 % (190/190)	100.0 % (32/32)	N.A.	N.A.	100.0 % (301/301)
I_BM_DATA_EDGE_DETECTOR	100.0 % (19/19)	100.0 % (12/12)	100.0 % (28/28)	100.0 % (35/35)	N.A.	N.A.	100.0 % (94/94)
I_SHIFT_REGS_RST_REG	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
I_TX_TRIGGER_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
I_BM_SSP_GENERATOR	100.0 % (55/55)	100.0 % (56/56)	100.0 % (262/262)	100.0 % (65/65)	N.A.	N.A.	100.0 % (438/438)
I_BM_TX_DATA_CACHE	100.0 % (15/15)	100.0 % (18/18)	100.0 % (60/60)	100.0 % (12/12)	N.A.	N.A.	100.0 % (105/105)
I_BM_BIT_ERR_DETECTOR	100.0 % (25/25)	100.0 % (24/24)	100.0 % (38/38)	100.0 % (56/56)	N.A.	N.A.	100.0 % (143/143)
I_BM_SAMPLE_MUX	100.0 % (11/11)	100.0 % (10/10)	100.0 % (24/24)	100.0 % (6/6)	N.A.	N.A.	100.0 % (51/51)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP	100.0 % (11/11)	100.0 % (6/6)	100.0 % (118/118)	100.0 % (7/7)	N.A.	N.A.	100.0 % (142/142)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement	Branch	Toggle	Expression	FSM state	Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 313 to 314:

313:    shift_regs_res_d <= '0' when (ssp_reset = '1') else 
314:                        '1';

Count: 68618
Threshold: 1

Signal assignment statement on line 313:

313: shift_regs_res_d <= '0' when (ssp_reset = '1') else
Count: 32708
Threshold: 1

Signal assignment statement on line 314:

314: '1';
Count: 35910
Threshold: 1

If statement on lines 378 to 379:

378:    ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else 
379:                  '0';

Count: 58520
Threshold: 1

Signal assignment statement on line 378:

378: ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else
Count: 3751
Threshold: 1

Signal assignment statement on line 379:

379: '0';
Count: 54769
Threshold: 1

If statement on lines 386 to 388:

386:    tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE) 
387:                          else 
388:                      '0';

Count: 22915997
Threshold: 1

Signal assignment statement on line 386:

386: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)
Count: 194479
Threshold: 1

Signal assignment statement on line 388:

388: '0';
Count: 22721518
Threshold: 1

Signal assignment statement on line 448:

448: can_tx <= tx_data_wbs;
Count: 1276962
Threshold: 1

Signal assignment statement on line 451:

451: rx_data_wbs <= data_rx_synced;
Count: 2819784
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 313:

313: shift_regs_res_d <= '0' when (ssp_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	32708	1
Bin	False	35910	1

"if" / "when" / "else" condition on line 378:

378: ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	3751	1
Bin	False	54769	1

"if" / "when" / "else" condition on line 386:

386: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)

	Evaluated to	Count	Threshold
Bin	True	194479	1
Bin	False	22721518	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CAN_RX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_OFFSET

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_SRC

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TQ_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_DATA_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SSP_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_DELAY_MEAS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BTMC_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DBT_MEASURE_START

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

GEN_FIRST_SSP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CAN_TX

	From	To	Count	Threshold
Bin	0	1	638480	1
Bin	1	0	636881	1

Port:

TRV_DELAY

	Element	From	To	Count	Threshold
Bin	(7)	0	1	23	1
Bin	(7)	1	0	1624	1
Bin	(6)	0	1	38	1
Bin	(6)	1	0	1639	1
Bin	(5)	0	1	69	1
Bin	(5)	1	0	1670	1
Bin	(4)	0	1	86	1
Bin	(4)	1	0	1687	1
Bin	(3)	0	1	77	1
Bin	(3)	1	0	1678	1
Bin	(2)	0	1	85	1
Bin	(2)	1	0	1686	1
Bin	(1)	0	1	2178	1
Bin	(1)	1	0	3779	1
Bin	(0)	0	1	67	1
Bin	(0)	1	0	1668	1

Port:

SYNC_EDGE

	From	To	Count	Threshold
Bin	0	1	1562664	1
Bin	1	0	1564265	1

Port:

RX_DATA_WBS

	From	To	Count	Threshold
Bin	0	1	1409892	1
Bin	1	0	1408291	1

Port:

BIT_ERR

	From	To	Count	Threshold
Bin	0	1	10109	1
Bin	1	0	11710	1

Signal:

DATA_RX_SYNCED

	From	To	Count	Threshold
Bin	0	1	1409892	1
Bin	1	0	1408291	1

Signal:

PREV_SAMPLE

	From	To	Count	Threshold
Bin	0	1	1399038	1
Bin	1	0	1397437	1

Signal:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	195230	1
Bin	1	0	196831	1

Signal:

DATA_TX_DELAYED

	From	To	Count	Threshold
Bin	0	1	100672	1
Bin	1	0	99071	1

Signal:

EDGE_RX_VALID

	From	To	Count	Threshold
Bin	0	1	1408291	1
Bin	1	0	1409892	1

Signal:

EDGE_TX_VALID

	From	To	Count	Threshold
Bin	0	1	638509	1
Bin	1	0	640110	1

Signal:

SSP_DELAY

	Element	From	To	Count	Threshold
Bin	(8)	0	1	15	1
Bin	(8)	1	0	1616	1
Bin	(7)	0	1	32	1
Bin	(7)	1	0	1633	1
Bin	(6)	0	1	44	1
Bin	(6)	1	0	1645	1
Bin	(5)	0	1	66	1
Bin	(5)	1	0	1667	1
Bin	(4)	0	1	60	1
Bin	(4)	1	0	1661	1
Bin	(3)	0	1	268	1
Bin	(3)	1	0	1869	1
Bin	(2)	0	1	942	1
Bin	(2)	1	0	2543	1
Bin	(1)	0	1	240	1
Bin	(1)	1	0	1841	1
Bin	(0)	0	1	918	1
Bin	(0)	1	0	2519	1

Signal:

TX_TRIGGER_Q

	From	To	Count	Threshold
Bin	0	1	11427938	1
Bin	1	0	11429539	1

Signal:

TX_TRIGGER_SSP

	From	To	Count	Threshold
Bin	0	1	194479	1
Bin	1	0	196080	1

Signal:

SHIFT_REGS_RES_D

	From	To	Count	Threshold
Bin	0	1	34309	1
Bin	1	0	32708	1

Signal:

SHIFT_REGS_RES_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	40790	1
Bin	1	0	40779	1

Signal:

SSP_ENABLE

	From	To	Count	Threshold
Bin	0	1	3751	1
Bin	1	0	5352	1

Uncovered expressions:

Excluded expressions:

"and" expression on line 386:

 tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE 
 <------LHS------->     <------------RHS------------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression on line 313:

ssp_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	35910	1
Bin	True	32708	1

"and" expression on line 386:

 tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE 
 <------LHS------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	True	False	11233459	1
Bin	True	True	194479	1

"=" expression on line 386:

tx_trigger_q = '1'

	Evaluated to	Count	Threshold
Bin	False	11488059	1
Bin	True	11427938	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 313 to 314:

Signal assignment statement on line 313:

Signal assignment statement on line 314:

If statement on lines 378 to 379:

Signal assignment statement on line 378:

Signal assignment statement on line 379:

If statement on lines 386 to 388:

Signal assignment statement on line 386:

Signal assignment statement on line 388:

Signal assignment statement on line 448:

Signal assignment statement on line 451:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 313:

"if" / "when" / "else" condition on line 378:

"if" / "when" / "else" condition on line 386:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

"and" expression on line 386:

Covered expressions:

"=" expression on line 313:

"and" expression on line 386:

"=" expression on line 386:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: