NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP

File:  /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/mr_top.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
I_ADDRESS_DECODER_CONTROL_REGISTERS 100.0 % (121/121) 100.0 % (80/80) 100.0 % (252/252) 100.0 % (2/2) N.A. N.A. 100.0 % (455/455)
I_MODE_RST_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_MODE_BMM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_STM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_AFM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_FDE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_TTTM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_ROM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_ACF_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_TSTM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_RXBAM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_TXBBM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_SAM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_MODE_ERFM_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_RTRLE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_RTRTH_REG 100.0 % (18/18) 100.0 % (24/24) 100.0 % (34/34) 100.0 % (19/19) N.A. N.A. 100.0 % (95/95)
I_SETTINGS_ILBP_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_ENA_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_NISOFD_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_PEX_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_TBFBO_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_FDRF_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_SETTINGS_PCHKE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_COMMAND_RXRPMV_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_RRB_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_CDO_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_ERCRST_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_RXFCRST_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_TXFCRST_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_CPEXS_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_CRXPE_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_CTXPE_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_COMMAND_CTXDPE_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_RXI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_TXI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_EWLI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_DOI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_FCSI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_ALI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_BEI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_OFI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_RXFI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_BSI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_RBNEI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_STAT_TXBHCI_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_INT_ENA_SET_INT_ENA_SET_SLICE_1_REG 100.0 % (26/26) 100.0 % (16/16) 100.0 % (58/58) 100.0 % (19/19) N.A. N.A. 100.0 % (119/119)
I_INT_ENA_SET_INT_ENA_SET_SLICE_2_REG 100.0 % (14/14) 100.0 % (8/8) 100.0 % (34/34) 100.0 % (11/11) N.A. N.A. 100.0 % (67/67)
I_INT_ENA_CLR_INT_ENA_CLR_SLICE_1_REG 100.0 % (26/26) 100.0 % (16/16) 100.0 % (58/58) 100.0 % (19/19) N.A. N.A. 100.0 % (119/119)
I_INT_ENA_CLR_INT_ENA_CLR_SLICE_2_REG 100.0 % (14/14) 100.0 % (8/8) 100.0 % (34/34) 100.0 % (11/11) N.A. N.A. 100.0 % (67/67)
I_INT_MASK_SET_INT_MASK_SET_SLICE_1_REG 100.0 % (26/26) 100.0 % (16/16) 100.0 % (58/58) 100.0 % (19/19) N.A. N.A. 100.0 % (119/119)
I_INT_MASK_SET_INT_MASK_SET_SLICE_2_REG 100.0 % (14/14) 100.0 % (8/8) 100.0 % (34/34) 100.0 % (11/11) N.A. N.A. 100.0 % (67/67)
I_INT_MASK_CLR_INT_MASK_CLR_SLICE_1_REG 100.0 % (26/26) 100.0 % (16/16) 100.0 % (58/58) 100.0 % (19/19) N.A. N.A. 100.0 % (119/119)
I_INT_MASK_CLR_INT_MASK_CLR_SLICE_2_REG 100.0 % (14/14) 100.0 % (8/8) 100.0 % (34/34) 100.0 % (11/11) N.A. N.A. 100.0 % (67/67)
I_BTR_PROP_REG 100.0 % (30/30) 100.0 % (42/42) 100.0 % (54/54) 100.0 % (34/34) N.A. N.A. 100.0 % (160/160)
I_BTR_PH1_SLICE_1_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (18/18) 100.0 % (10/10) N.A. N.A. 100.0 % (40/40)
I_BTR_PH1_SLICE_2_REG 100.0 % (22/22) 100.0 % (30/30) 100.0 % (42/42) 100.0 % (26/26) N.A. N.A. 100.0 % (120/120)
I_BTR_PH2_SLICE_1_REG 100.0 % (14/14) 100.0 % (18/18) 100.0 % (30/30) 100.0 % (18/18) N.A. N.A. 100.0 % (80/80)
I_BTR_PH2_SLICE_2_REG 100.0 % (14/14) 100.0 % (18/18) 100.0 % (30/30) 100.0 % (18/18) N.A. N.A. 100.0 % (80/80)
I_BTR_BRP_SLICE_1_REG 100.0 % (22/22) 100.0 % (30/30) 100.0 % (42/42) 100.0 % (26/26) N.A. N.A. 100.0 % (120/120)
I_BTR_BRP_SLICE_2_REG 100.0 % (14/14) 100.0 % (18/18) 100.0 % (30/30) 100.0 % (18/18) N.A. N.A. 100.0 % (80/80)
I_BTR_SJW_REG 100.0 % (22/22) 100.0 % (30/30) 100.0 % (42/42) 100.0 % (26/26) N.A. N.A. 100.0 % (120/120)
I_BTR_FD_PROP_FD_REG 100.0 % (26/26) 100.0 % (36/36) 100.0 % (48/48) 100.0 % (30/30) N.A. N.A. 100.0 % (140/140)
I_BTR_FD_PH1_FD_SLICE_1_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (18/18) 100.0 % (10/10) N.A. N.A. 100.0 % (40/40)
I_BTR_FD_PH1_FD_SLICE_2_REG 100.0 % (18/18) 100.0 % (24/24) 100.0 % (36/36) 100.0 % (22/22) N.A. N.A. 100.0 % (100/100)
I_BTR_FD_PH2_FD_SLICE_1_REG 100.0 % (14/14) 100.0 % (18/18) 100.0 % (30/30) 100.0 % (18/18) N.A. N.A. 100.0 % (80/80)
I_BTR_FD_PH2_FD_SLICE_2_REG 100.0 % (10/10) 100.0 % (12/12) 100.0 % (24/24) 100.0 % (14/14) N.A. N.A. 100.0 % (60/60)
I_BTR_FD_BRP_FD_SLICE_1_REG 100.0 % (22/22) 100.0 % (30/30) 100.0 % (42/42) 100.0 % (26/26) N.A. N.A. 100.0 % (120/120)
I_BTR_FD_BRP_FD_SLICE_2_REG 100.0 % (14/14) 100.0 % (18/18) 100.0 % (30/30) 100.0 % (18/18) N.A. N.A. 100.0 % (80/80)
I_BTR_FD_SJW_FD_REG 100.0 % (22/22) 100.0 % (30/30) 100.0 % (42/42) 100.0 % (26/26) N.A. N.A. 100.0 % (120/120)
I_EWL_EW_LIMIT_REG 100.0 % (34/34) 100.0 % (48/48) 100.0 % (60/60) 100.0 % (38/38) N.A. N.A. 100.0 % (180/180)
I_ERP_ERP_LIMIT_REG 100.0 % (34/34) 100.0 % (48/48) 100.0 % (60/60) 100.0 % (38/38) N.A. N.A. 100.0 % (180/180)
I_CTR_PRES_CTPV_SLICE_1_REG 100.0 % (34/34) 100.0 % (48/48) 100.0 % (60/60) 100.0 % (38/38) N.A. N.A. 100.0 % (180/180)
I_CTR_PRES_CTPV_SLICE_2_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (18/18) 100.0 % (10/10) N.A. N.A. 100.0 % (40/40)
I_CTR_PRES_PTX_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (18/18) 100.0 % (8/8) N.A. N.A. 100.0 % (33/33)
I_CTR_PRES_PRX_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (18/18) 100.0 % (8/8) N.A. N.A. 100.0 % (33/33)
I_CTR_PRES_ENORM_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (18/18) 100.0 % (8/8) N.A. N.A. 100.0 % (33/33)
I_CTR_PRES_EFD_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (18/18) 100.0 % (8/8) N.A. N.A. 100.0 % (33/33)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_2_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_3_T 100.0 % (34/34) 100.0 % (48/48) 100.0 % (58/58) 100.0 % (35/35) N.A. N.A. 100.0 % (175/175)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_4_T 100.0 % (22/22) 100.0 % (30/30) 100.0 % (40/40) 100.0 % (23/23) N.A. N.A. 100.0 % (115/115)
I_FILTER_CONTROL_FANB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FANE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FAFB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FAFE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FBNB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FBNE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FBFB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FBFE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FCNB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FCNE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FCFB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FCFE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FRNB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FRNE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FRFB_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_FILTER_CONTROL_FRFE_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_RX_SETTINGS_RTSOP_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_RX_DATA_ACCESS_SIGNALLER 100.0 % (3/3) 100.0 % (2/2) 100.0 % (18/18) 100.0 % (3/3) N.A. N.A. 100.0 % (26/26)
I_TX_COMMAND_TXCE_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_TX_COMMAND_TXCR_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_TX_COMMAND_TXCA_REG 100.0 % (5/5) 100.0 % (2/2) 100.0 % (16/16) 100.0 % (5/5) N.A. N.A. 100.0 % (28/28)
I_TX_COMMAND_TXB1_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_TX_COMMAND_TXB2_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
G_TX_COMMAND_TXB3_T 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
G_TX_COMMAND_TXB4_T 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
G_TX_COMMAND_TXB5_T 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
G_TX_COMMAND_TXB6_T 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
G_TX_COMMAND_TXB7_T 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
G_TX_COMMAND_TXB8_T 100.0 % (6/6) 100.0 % (6/6) 100.0 % (16/16) 100.0 % (7/7) N.A. N.A. 100.0 % (35/35)
I_TX_PRIORITY_TXT1P_REG 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
I_TX_PRIORITY_TXT2P_REG 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
G_TX_PRIORITY_TXT3P_T 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
G_TX_PRIORITY_TXT4P_T 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
G_TX_PRIORITY_TXT5P_T 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
G_TX_PRIORITY_TXT6P_T 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
G_TX_PRIORITY_TXT7P_T 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
G_TX_PRIORITY_TXT8P_T 100.0 % (14/14) 100.0 % (18/18) 100.0 % (28/28) 100.0 % (15/15) N.A. N.A. 100.0 % (75/75)
I_SSP_CFG_SSP_OFFSET_REG 100.0 % (34/34) 100.0 % (48/48) 100.0 % (60/60) 100.0 % (38/38) N.A. N.A. 100.0 % (180/180)
I_SSP_CFG_SSP_SRC_REG 100.0 % (10/10) 100.0 % (12/12) 100.0 % (24/24) 100.0 % (14/14) N.A. N.A. 100.0 % (60/60)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_COMMAND_TXB5_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_COMMAND_TXB6_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_COMMAND_TXB7_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_COMMAND_TXB8_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_PRIORITY_TXT5P_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_PRIORITY_TXT6P_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_PRIORITY_TXT7P_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_PRIORITY_TXT8P_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_1_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_2_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_COMMAND_TXB3_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_COMMAND_TXB4_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_PRIORITY_TXT3P_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)
G_TX_PRIORITY_TXT4P_F 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP 100.0 % (50/50) 100.0 % (48/48) 100.0 % (3270/3270) 100.0 % (16/16) N.A. 100.0 % (73/73) 100.0 % (3457/3457)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on line 122:

122:    write_en <= be when (write = '1' and cs = '1') else (others => '0'); 
Count: 95053016
Threshold: 1

Signal assignment statement on line 122:

122:    write_en <= be when (write = '1' and cs = '1') else (others => '0'); 
Count: 155958
Threshold: 1

Signal assignment statement on line 122:

122:    write_en <= be when (write = '1' and cs = '1') else (others => '0')
Count: 94897058
Threshold: 1

Sequential statement on lines 3125 to 3332:

3125:    with address(7 downto 2) select r_data_comb <= 
3126:        control_registers_in.version_ver_major & 
...
3331:        control_registers_in.timestamp_high_timestamp_high when "100110", 
3332:        (others => '0') when others; 

Count: 606265423
Threshold: 1

Signal assignment statement on lines 3126 to 3128:

3126:        control_registers_in.version_ver_major & 
3127:        control_registers_in.version_ver_minor & 
3128:        control_registers_in.device_id_device_id when "000000", 

Count: 272544
Threshold: 1

Signal assignment statement on lines 3129 to 3152:

3129:        '0' & '0' & '0' & '0' & 
3130:        control_registers_out_i.settings_pchke & 
...
3151:        control_registers_out_i.mode_bmm & 
3152:        control_registers_out_i.mode_rst when "000001", 

Count: 561262
Threshold: 1

Signal assignment statement on lines 3153 to 3169:

3153:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3154:        control_registers_in.status_sprt & 
...
3168:        control_registers_in.status_dor & 
3169:        control_registers_in.status_rxne when "000010", 

Count: 19393948
Threshold: 1

Signal assignment statement on line 3170:

3170:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000011", 
Count: 300670
Threshold: 1

Signal assignment statement on lines 3171 to 3183:

3171:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3172:        control_registers_in.int_stat_txbhci & 
...
3182:        control_registers_in.int_stat_txi & 
3183:        control_registers_in.int_stat_rxi when "000100", 

Count: 113438
Threshold: 1

Signal assignment statement on lines 3184 to 3185:

3184:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3185:        control_registers_in.int_ena_set_int_ena_set when "000101", 

Count: 68688
Threshold: 1

Signal assignment statement on line 3186:

3186:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000110", 
Count: 56518
Threshold: 1

Signal assignment statement on lines 3187 to 3188:

3187:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3188:        control_registers_in.int_mask_set_int_mask_set when "000111", 

Count: 55613
Threshold: 1

Signal assignment statement on line 3189:

3189:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001000", 
Count: 54663
Threshold: 1

Signal assignment statement on lines 3190 to 3194:

3190:        control_registers_out_i.btr_sjw & 
3191:        control_registers_out_i.btr_brp & 
3192:        control_registers_out_i.btr_ph2 & 
3193:        control_registers_out_i.btr_ph1 & 
3194:        control_registers_out_i.btr_prop when "001001", 

Count: 71676
Threshold: 1

Signal assignment statement on lines 3195 to 3202:

3195:        control_registers_out_i.btr_fd_sjw_fd & 
3196:        control_registers_out_i.btr_fd_brp_fd & 
...
3201:        '0' & 
3202:        control_registers_out_i.btr_fd_prop_fd when "001010", 

Count: 70485
Threshold: 1

Signal assignment statement on lines 3203 to 3208:

3203:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3204:        control_registers_in.fault_state_bof & 
3205:        control_registers_in.fault_state_erp & 
3206:        control_registers_in.fault_state_era & 
3207:        control_registers_out_i.erp_erp_limit & 
3208:        control_registers_out_i.ewl_ew_limit when "001011", 

Count: 284705
Threshold: 1

Signal assignment statement on lines 3209 to 3212:

3209:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3210:        control_registers_in.tec_tec_val & 
3211:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3212:        control_registers_in.rec_rec_val when "001100", 

Count: 80801
Threshold: 1

Signal assignment statement on lines 3213 to 3214:

3213:        control_registers_in.err_fd_err_fd_val & 
3214:        control_registers_in.err_norm_err_norm_val when "001101", 

Count: 56924
Threshold: 1

Signal assignment statement on line 3215:

3215:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001110", 
Count: 158149
Threshold: 1

Signal assignment statement on lines 3216 to 3217:

3216:        '0' & '0' & '0' & 
3217:        control_registers_out_i.filter_a_mask_bit_mask_a_val when "001111", 

Count: 59088
Threshold: 1

Signal assignment statement on lines 3218 to 3219:

3218:        '0' & '0' & '0' & 
3219:        control_registers_out_i.filter_a_val_bit_val_a_val when "010000", 

Count: 58518
Threshold: 1

Signal assignment statement on lines 3220 to 3221:

3220:        '0' & '0' & '0' & 
3221:        control_registers_out_i.filter_b_mask_bit_mask_b_val when "010001", 

Count: 56024
Threshold: 1

Signal assignment statement on lines 3222 to 3223:

3222:        '0' & '0' & '0' & 
3223:        control_registers_out_i.filter_b_val_bit_val_b_val when "010010", 

Count: 56024
Threshold: 1

Signal assignment statement on lines 3224 to 3225:

3224:        '0' & '0' & '0' & 
3225:        control_registers_out_i.filter_c_mask_bit_mask_c_val when "010011", 

Count: 56024
Threshold: 1

Signal assignment statement on lines 3226 to 3227:

3226:        '0' & '0' & '0' & 
3227:        control_registers_out_i.filter_c_val_bit_val_c_val when "010100", 

Count: 53605
Threshold: 1

Signal assignment statement on lines 3228 to 3229:

3228:        '0' & '0' & '0' & 
3229:        control_registers_out_i.filter_ran_low_bit_ran_low_val when "010101", 

Count: 140
Threshold: 1

Signal assignment statement on lines 3230 to 3231:

3230:        '0' & '0' & '0' & 
3231:        control_registers_out_i.filter_ran_high_bit_ran_high_val when "010110", 

Count: 140
Threshold: 1

Signal assignment statement on lines 3232 to 3252:

3232:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3233:        control_registers_in.filter_status_sfr & 
...
3251:        control_registers_out_i.filter_control_fane & 
3252:        control_registers_out_i.filter_control_fanb when "010111", 

Count: 40136
Threshold: 1

Signal assignment statement on lines 3253 to 3256:

3253:        '0' & '0' & '0' & 
3254:        control_registers_in.rx_mem_info_rx_mem_free & 
3255:        '0' & '0' & '0' & 
3256:        control_registers_in.rx_mem_info_rx_buff_size when "011000", 

Count: 25474
Threshold: 1

Signal assignment statement on lines 3257 to 3260:

3257:        '0' & '0' & '0' & '0' & 
3258:        control_registers_in.rx_pointers_rx_rpp & 
3259:        '0' & '0' & '0' & '0' & 
3260:        control_registers_in.rx_pointers_rx_wpp when "011001", 

Count: 25332
Threshold: 1

Signal assignment statement on lines 3261 to 3268:

3261:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3262:        control_registers_out_i.rx_settings_rtsop & 
...
3267:        control_registers_in.rx_status_rxf & 
3268:        control_registers_in.rx_status_rxe when "011010", 

Count: 26872
Threshold: 1

Signal assignment statement on line 3269:

3269:        control_registers_in.rx_data_rx_data when "011011", 
Count: 216248
Threshold: 1

Signal assignment statement on lines 3270 to 3277:

3270:        control_registers_in.tx_status_tx8s & 
3271:        control_registers_in.tx_status_tx7s & 
...
3276:        control_registers_in.tx_status_tx2s & 
3277:        control_registers_in.tx_status_tx1s when "011100", 

Count: 35117
Threshold: 1

Signal assignment statement on lines 3278 to 3280:

3278:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3279:        control_registers_in.txtb_info_txt_buffer_count & 
3280:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "011101", 

Count: 86969
Threshold: 1

Signal assignment statement on lines 3281 to 3296:

3281:        '0' & 
3282:        control_registers_out_i.tx_priority_txt8p & 
...
3295:        '0' & 
3296:        control_registers_out_i.tx_priority_txt1p when "011110", 

Count: 8132
Threshold: 1

Signal assignment statement on lines 3297 to 3305:

3297:        '0' & '0' & 
3298:        control_registers_in.ts_info_ts_bits & 
...
3304:        control_registers_in.err_capt_err_erp & 
3305:        control_registers_in.err_capt_err_pos when "011111", 

Count: 3540
Threshold: 1

Signal assignment statement on lines 3306 to 3310:

3306:        '0' & '0' & '0' & '0' & '0' & '0' & 
3307:        control_registers_out_i.ssp_cfg_ssp_src & 
3308:        control_registers_out_i.ssp_cfg_ssp_offset & 
3309:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3310:        control_registers_in.trv_delay_trv_delay_value when "100000", 

Count: 11866
Threshold: 1

Signal assignment statement on line 3311:

3311:        control_registers_in.rx_fr_ctr_rx_fr_ctr_val when "100001", 
Count: 2350
Threshold: 1

Signal assignment statement on line 3312:

3312:        control_registers_in.tx_fr_ctr_tx_fr_ctr_val when "100010", 
Count: 2268
Threshold: 1

Signal assignment statement on lines 3313 to 3328:

3313:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
3314:        control_registers_in.debug_register_pc_sof & 
...
3327:        control_registers_in.debug_register_destuff_count & 
3328:        control_registers_in.debug_register_stuff_count when "100011", 

Count: 33715028
Threshold: 1

Signal assignment statement on line 3329:

3329:        control_registers_in.yolo_reg_yolo_val when "100100", 
Count: 90
Threshold: 1

Signal assignment statement on line 3330:

3330:        control_registers_in.timestamp_low_timestamp_low when "100101", 
Count: 7870
Threshold: 1

Signal assignment statement on line 3331:

3331:        control_registers_in.timestamp_high_timestamp_high when "100110", 
Count: 7870
Threshold: 1

Signal assignment statement on line 3332:

3332:        (others => '0') when others; 
Count: 550110614
Threshold: 1

If statement on lines 3339 to 3345:

3339:        if (rst_n = '0') then 
3340:            r_data <= (others => '0'); 
...
3344:            end if; 
3345:        end if; 

Count: 61946861
Threshold: 1

Signal assignment statement on line 3340:

3340:            r_data <= (others => '0'); 
Count: 17946
Threshold: 1

If statement on lines 3342 to 3344:

3342:            if (cs = '1' and read = '1') then 
3343:                r_data <= r_data_comb and read_data_mask_n; 
3344:            end if; 

Count: 30959021
Threshold: 1

Signal assignment statement on line 3343:

3343:                r_data <= r_data_comb and read_data_mask_n; 
Count: 19507038
Threshold: 1

Signal assignment statement on lines 3352 to 3355:

3352:      be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &  
3353:      be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &  
3354:      be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &  
3355:      be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ; 

Count: 55725271
Threshold: 1

Signal assignment statement on line 3357:

3357:    Control_registers_out <= Control_registers_out_i
Count: 500536
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 122:

122:    write_en <= be when (write = '1' and cs = '1') else (others => '0'); 
Evaluated toCountThreshold
BinTrue1559581
BinFalse948970581

"case" / "with" / "select" choice on line 3128:

3128:        control_registers_in.device_id_device_id when "000000"
Choice ofCountThreshold
Bin"000000"2725441

"case" / "with" / "select" choice on line 3152:

3152:        control_registers_out_i.mode_rst when "000001"
Choice ofCountThreshold
Bin"000001"5612621

"case" / "with" / "select" choice on line 3169:

3169:        control_registers_in.status_rxne when "000010"
Choice ofCountThreshold
Bin"000010"193939481

"case" / "with" / "select" choice on line 3170:

3170:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000011"
Choice ofCountThreshold
Bin"000011"3006701

"case" / "with" / "select" choice on line 3183:

3183:        control_registers_in.int_stat_rxi when "000100"
Choice ofCountThreshold
Bin"000100"1134381

"case" / "with" / "select" choice on line 3185:

3185:        control_registers_in.int_ena_set_int_ena_set when "000101"
Choice ofCountThreshold
Bin"000101"686881

"case" / "with" / "select" choice on line 3186:

3186:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000110"
Choice ofCountThreshold
Bin"000110"565181

"case" / "with" / "select" choice on line 3188:

3188:        control_registers_in.int_mask_set_int_mask_set when "000111"
Choice ofCountThreshold
Bin"000111"556131

"case" / "with" / "select" choice on line 3189:

3189:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001000"
Choice ofCountThreshold
Bin"001000"546631

"case" / "with" / "select" choice on line 3194:

3194:        control_registers_out_i.btr_prop when "001001"
Choice ofCountThreshold
Bin"001001"716761

"case" / "with" / "select" choice on line 3202:

3202:        control_registers_out_i.btr_fd_prop_fd when "001010"
Choice ofCountThreshold
Bin"001010"704851

"case" / "with" / "select" choice on line 3208:

3208:        control_registers_out_i.ewl_ew_limit when "001011"
Choice ofCountThreshold
Bin"001011"2847051

"case" / "with" / "select" choice on line 3212:

3212:        control_registers_in.rec_rec_val when "001100"
Choice ofCountThreshold
Bin"001100"808011

"case" / "with" / "select" choice on line 3214:

3214:        control_registers_in.err_norm_err_norm_val when "001101"
Choice ofCountThreshold
Bin"001101"569241

"case" / "with" / "select" choice on line 3215:

3215:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001110"
Choice ofCountThreshold
Bin"001110"1581491

"case" / "with" / "select" choice on line 3217:

3217:        control_registers_out_i.filter_a_mask_bit_mask_a_val when "001111"
Choice ofCountThreshold
Bin"001111"590881

"case" / "with" / "select" choice on line 3219:

3219:        control_registers_out_i.filter_a_val_bit_val_a_val when "010000"
Choice ofCountThreshold
Bin"010000"585181

"case" / "with" / "select" choice on line 3221:

3221:        control_registers_out_i.filter_b_mask_bit_mask_b_val when "010001"
Choice ofCountThreshold
Bin"010001"560241

"case" / "with" / "select" choice on line 3223:

3223:        control_registers_out_i.filter_b_val_bit_val_b_val when "010010"
Choice ofCountThreshold
Bin"010010"560241

"case" / "with" / "select" choice on line 3225:

3225:        control_registers_out_i.filter_c_mask_bit_mask_c_val when "010011"
Choice ofCountThreshold
Bin"010011"560241

"case" / "with" / "select" choice on line 3227:

3227:        control_registers_out_i.filter_c_val_bit_val_c_val when "010100"
Choice ofCountThreshold
Bin"010100"536051

"case" / "with" / "select" choice on line 3229:

3229:        control_registers_out_i.filter_ran_low_bit_ran_low_val when "010101"
Choice ofCountThreshold
Bin"010101"1401

"case" / "with" / "select" choice on line 3231:

3231:        control_registers_out_i.filter_ran_high_bit_ran_high_val when "010110"
Choice ofCountThreshold
Bin"010110"1401

"case" / "with" / "select" choice on line 3252:

3252:        control_registers_out_i.filter_control_fanb when "010111"
Choice ofCountThreshold
Bin"010111"401361

"case" / "with" / "select" choice on line 3256:

3256:        control_registers_in.rx_mem_info_rx_buff_size when "011000"
Choice ofCountThreshold
Bin"011000"254741

"case" / "with" / "select" choice on line 3260:

3260:        control_registers_in.rx_pointers_rx_wpp when "011001"
Choice ofCountThreshold
Bin"011001"253321

"case" / "with" / "select" choice on line 3268:

3268:        control_registers_in.rx_status_rxe when "011010"
Choice ofCountThreshold
Bin"011010"268721

"case" / "with" / "select" choice on line 3269:

3269:        control_registers_in.rx_data_rx_data when "011011"
Choice ofCountThreshold
Bin"011011"2162481

"case" / "with" / "select" choice on line 3277:

3277:        control_registers_in.tx_status_tx1s when "011100"
Choice ofCountThreshold
Bin"011100"351171

"case" / "with" / "select" choice on line 3280:

3280:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "011101"
Choice ofCountThreshold
Bin"011101"869691

"case" / "with" / "select" choice on line 3296:

3296:        control_registers_out_i.tx_priority_txt1p when "011110"
Choice ofCountThreshold
Bin"011110"81321

"case" / "with" / "select" choice on line 3305:

3305:        control_registers_in.err_capt_err_pos when "011111"
Choice ofCountThreshold
Bin"011111"35401

"case" / "with" / "select" choice on line 3310:

3310:        control_registers_in.trv_delay_trv_delay_value when "100000"
Choice ofCountThreshold
Bin"100000"118661

"case" / "with" / "select" choice on line 3311:

3311:        control_registers_in.rx_fr_ctr_rx_fr_ctr_val when "100001"
Choice ofCountThreshold
Bin"100001"23501

"case" / "with" / "select" choice on line 3312:

3312:        control_registers_in.tx_fr_ctr_tx_fr_ctr_val when "100010"
Choice ofCountThreshold
Bin"100010"22681

"case" / "with" / "select" choice on line 3328:

3328:        control_registers_in.debug_register_stuff_count when "100011"
Choice ofCountThreshold
Bin"100011"337150281

"case" / "with" / "select" choice on line 3329:

3329:        control_registers_in.yolo_reg_yolo_val when "100100"
Choice ofCountThreshold
Bin"100100"901

"case" / "with" / "select" choice on line 3330:

3330:        control_registers_in.timestamp_low_timestamp_low when "100101"
Choice ofCountThreshold
Bin"100101"78701

"case" / "with" / "select" choice on line 3331:

3331:        control_registers_in.timestamp_high_timestamp_high when "100110"
Choice ofCountThreshold
Bin"100110"78701

"case" / "with" / "select" choice on line 3332:

3332:        (others => '0') when others
Choice ofCountThreshold
Binothers5501106141

"if" / "when" / "else" condition on line 3339:

3339:        if (rst_n = '0') then 
Evaluated toCountThreshold
BinTrue179461
BinFalse619289151

"if" / "when" / "else" condition on line 3341:

3341:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue309590211
BinFalse309698941

"if" / "when" / "else" condition on line 3342:

3342:            if (cs = '1' and read = '1') then 
Evaluated toCountThreshold
BinTrue195070381
BinFalse114519831

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RST_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 ADDRESS
ElementFromToCountThresholdExcluded due to
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 W_DATA
ElementFromToCountThresholdExcluded due to
Bin(31)0101Exclude file
Bin(31)1001Exclude file
Bin(30)0101Exclude file
Bin(30)1001Exclude file
Bin(29)0101Exclude file
Bin(29)1001Exclude file
Bin(28)0101Exclude file
Bin(28)1001Exclude file
Bin(27)0101Exclude file
Bin(27)1001Exclude file
Bin(26)0101Exclude file
Bin(26)1001Exclude file
Bin(25)0101Exclude file
Bin(25)1001Exclude file
Bin(24)0101Exclude file
Bin(24)1001Exclude file
Bin(23)0101Exclude file
Bin(23)1001Exclude file
Bin(22)0101Exclude file
Bin(22)1001Exclude file
Bin(21)0101Exclude file
Bin(21)1001Exclude file
Bin(20)0101Exclude file
Bin(20)1001Exclude file
Bin(19)0101Exclude file
Bin(19)1001Exclude file
Bin(18)0101Exclude file
Bin(18)1001Exclude file
Bin(17)0101Exclude file
Bin(17)1001Exclude file
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 READ
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 WRITE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 BE
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 LOCK_1
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 LOCK_2
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 CONTROL_REGISTERS_IN
ElementFromToCountThresholdExcluded due to
BinDEVICE_ID_DEVICE_ID(15)1001Exclude file
BinDEVICE_ID_DEVICE_ID(14)1001Exclude file
BinDEVICE_ID_DEVICE_ID(13)0101Exclude file
BinDEVICE_ID_DEVICE_ID(12)0101Exclude file
BinDEVICE_ID_DEVICE_ID(11)1001Exclude file
BinDEVICE_ID_DEVICE_ID(10)0101Exclude file
BinDEVICE_ID_DEVICE_ID(9)1001Exclude file
BinDEVICE_ID_DEVICE_ID(8)0101Exclude file
BinDEVICE_ID_DEVICE_ID(7)1001Exclude file
BinDEVICE_ID_DEVICE_ID(6)1001Exclude file
BinDEVICE_ID_DEVICE_ID(5)1001Exclude file
BinDEVICE_ID_DEVICE_ID(4)1001Exclude file
BinDEVICE_ID_DEVICE_ID(3)1001Exclude file
BinDEVICE_ID_DEVICE_ID(2)1001Exclude file
BinDEVICE_ID_DEVICE_ID(1)0101Exclude file
BinDEVICE_ID_DEVICE_ID(0)1001Exclude file
BinVERSION_VER_MINOR(7)0101Exclude file
BinVERSION_VER_MINOR(6)0101Exclude file
BinVERSION_VER_MINOR(5)0101Exclude file
BinVERSION_VER_MINOR(4)0101Exclude file
BinVERSION_VER_MINOR(3)0101Exclude file
BinVERSION_VER_MINOR(2)1001Exclude file
BinVERSION_VER_MINOR(1)1001Exclude file
BinVERSION_VER_MINOR(0)1001Exclude file
BinVERSION_VER_MAJOR(7)0101Exclude file
BinVERSION_VER_MAJOR(6)0101Exclude file
BinVERSION_VER_MAJOR(5)0101Exclude file
BinVERSION_VER_MAJOR(4)0101Exclude file
BinVERSION_VER_MAJOR(3)0101Exclude file
BinVERSION_VER_MAJOR(2)0101Exclude file
BinVERSION_VER_MAJOR(1)1001Exclude file
BinVERSION_VER_MAJOR(0)0101Exclude file
BinSTATUS_STRGS1001Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(11)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(10)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(9)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(8)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(6)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(4)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(3)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(2)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(1)0101Exclude file
BinRX_MEM_INFO_RX_BUFF_SIZE(0)0101Exclude file
BinTXTB_INFO_TXT_BUFFER_COUNT(0)0101Exclude file
BinTS_INFO_TS_BITS(5)1001Exclude file
BinTS_INFO_TS_BITS(4)1001Exclude file
BinTS_INFO_TS_BITS(3)1001Exclude file
BinTS_INFO_TS_BITS(2)1001Exclude file
BinTS_INFO_TS_BITS(1)1001Exclude file
BinTS_INFO_TS_BITS(0)1001Exclude file
BinYOLO_REG_YOLO_VAL(31)1001Exclude file
BinYOLO_REG_YOLO_VAL(30)1001Exclude file
BinYOLO_REG_YOLO_VAL(29)0101Exclude file
BinYOLO_REG_YOLO_VAL(28)1001Exclude file
BinYOLO_REG_YOLO_VAL(27)1001Exclude file
BinYOLO_REG_YOLO_VAL(26)1001Exclude file
BinYOLO_REG_YOLO_VAL(25)1001Exclude file
BinYOLO_REG_YOLO_VAL(24)0101Exclude file
BinYOLO_REG_YOLO_VAL(23)1001Exclude file
BinYOLO_REG_YOLO_VAL(22)0101Exclude file
BinYOLO_REG_YOLO_VAL(21)1001Exclude file
BinYOLO_REG_YOLO_VAL(20)0101Exclude file
BinYOLO_REG_YOLO_VAL(19)1001Exclude file
BinYOLO_REG_YOLO_VAL(18)1001Exclude file
BinYOLO_REG_YOLO_VAL(17)0101Exclude file
BinYOLO_REG_YOLO_VAL(16)1001Exclude file
BinYOLO_REG_YOLO_VAL(15)1001Exclude file
BinYOLO_REG_YOLO_VAL(14)0101Exclude file
BinYOLO_REG_YOLO_VAL(13)1001Exclude file
BinYOLO_REG_YOLO_VAL(12)1001Exclude file
BinYOLO_REG_YOLO_VAL(11)1001Exclude file
BinYOLO_REG_YOLO_VAL(10)1001Exclude file
BinYOLO_REG_YOLO_VAL(9)1001Exclude file
BinYOLO_REG_YOLO_VAL(8)0101Exclude file
BinYOLO_REG_YOLO_VAL(7)1001Exclude file
BinYOLO_REG_YOLO_VAL(6)1001Exclude file
BinYOLO_REG_YOLO_VAL(5)1001Exclude file
BinYOLO_REG_YOLO_VAL(4)0101Exclude file
BinYOLO_REG_YOLO_VAL(3)1001Exclude file
BinYOLO_REG_YOLO_VAL(2)1001Exclude file
BinYOLO_REG_YOLO_VAL(1)1001Exclude file
BinYOLO_REG_YOLO_VAL(0)1001Exclude file

Covered toggles:

Port:

 R_DATA
ElementFromToCountThreshold
Bin(31)0149471
Bin(31)1065481
Bin(30)0160391
Bin(30)1076401
Bin(29)0158421
Bin(29)1074431
Bin(28)01114531
Bin(28)10130541
Bin(27)01134931
Bin(27)10150941
Bin(26)01113571
Bin(26)10129581
Bin(25)01178091
Bin(25)10194101
Bin(24)01168001
Bin(24)10184011
Bin(23)01198731
Bin(23)10214741
Bin(22)01283371
Bin(22)10299371
Bin(21)01170441
Bin(21)10186451
Bin(20)01219981
Bin(20)10235991
Bin(19)01225971
Bin(19)10241981
Bin(18)01749541
Bin(18)10765551
Bin(17)01632211
Bin(17)10648221
Bin(16)01635711
Bin(16)10651621
Bin(15)01305051
Bin(15)10320961
Bin(14)01223151
Bin(14)10239161
Bin(13)01246401
Bin(13)10262411
Bin(12)01318141
Bin(12)10334151
Bin(11)01329271
Bin(11)10345281
Bin(10)01334401
Bin(10)10350411
Bin(9)01344691
Bin(9)10360681
Bin(8)01328231
Bin(8)10344231
Bin(7)01582281
Bin(7)10598291
Bin(6)01554331
Bin(6)10570241
Bin(5)01677191
Bin(5)10693101
Bin(4)01671621
Bin(4)10687611
Bin(3)01770751
Bin(3)10786761
Bin(2)01614101
Bin(2)10630111
Bin(1)01436511
Bin(1)10452521
Bin(0)01495061
Bin(0)10511071

Port:

 CONTROL_REGISTERS_OUT
ElementFromToCountThreshold
BinMODE_RST018681
BinMODE_RST10328771
BinMODE_BMM01151
BinMODE_BMM1016161
BinMODE_STM011601
BinMODE_STM1017611
BinMODE_AFM01681
BinMODE_AFM1016691
BinMODE_FDE0118011
BinMODE_FDE102001
BinMODE_TTTM01551
BinMODE_TTTM1016561
BinMODE_ROM01511
BinMODE_ROM1016521
BinMODE_ACF01191
BinMODE_ACF1016201
BinMODE_TSTM0110271
BinMODE_TSTM1026271
BinMODE_RXBAM0117311
BinMODE_RXBAM101301
BinMODE_TXBBM01331
BinMODE_TXBBM1016341
BinMODE_SAM01551
BinMODE_SAM1016561
BinMODE_ERFM011531
BinMODE_ERFM1017541
BinSETTINGS_RTRLE0124541
BinSETTINGS_RTRLE1040551
BinSETTINGS_RTRTH(3)01221
BinSETTINGS_RTRTH(3)1016231
BinSETTINGS_RTRTH(2)01541
BinSETTINGS_RTRTH(2)1016551
BinSETTINGS_RTRTH(1)01221
BinSETTINGS_RTRTH(1)1016231
BinSETTINGS_RTRTH(0)01531
BinSETTINGS_RTRTH(0)1016541
BinSETTINGS_ILBP011301
BinSETTINGS_ILBP1017311
BinSETTINGS_ENA0164831
BinSETTINGS_ENA1080721
BinSETTINGS_NISOFD011301
BinSETTINGS_NISOFD1017311
BinSETTINGS_PEX01721
BinSETTINGS_PEX1016731
BinSETTINGS_TBFBO0125331
BinSETTINGS_TBFBO109441
BinSETTINGS_FDRF0141
BinSETTINGS_FDRF1016051
BinSETTINGS_PCHKE011241
BinSETTINGS_PCHKE1017251
BinCOMMAND_RXRPMV01211
BinCOMMAND_RXRPMV1030641
BinCOMMAND_RRB014601
BinCOMMAND_RRB1030641
BinCOMMAND_CDO01201
BinCOMMAND_CDO1030641
BinCOMMAND_ERCRST011701
BinCOMMAND_ERCRST1030641
BinCOMMAND_RXFCRST011241
BinCOMMAND_RXFCRST1030641
BinCOMMAND_TXFCRST011241
BinCOMMAND_TXFCRST1030641
BinCOMMAND_CPEXS01601
BinCOMMAND_CPEXS1030641
BinCOMMAND_CRXPE01401
BinCOMMAND_CRXPE1030641
BinCOMMAND_CTXPE014401
BinCOMMAND_CTXPE1030641
BinCOMMAND_CTXDPE01401
BinCOMMAND_CTXDPE1030641
BinINT_STAT_RXI01401
BinINT_STAT_RXI1017481
BinINT_STAT_TXI01421
BinINT_STAT_TXI1017481
BinINT_STAT_EWLI01301
BinINT_STAT_EWLI1017481
BinINT_STAT_DOI01161
BinINT_STAT_DOI1017481
BinINT_STAT_FCSI01801
BinINT_STAT_FCSI1017481
BinINT_STAT_ALI0151
BinINT_STAT_ALI1017481
BinINT_STAT_BEI01151
BinINT_STAT_BEI1017481
BinINT_STAT_OFI0151
BinINT_STAT_OFI1017481
BinINT_STAT_RXFI01151
BinINT_STAT_RXFI1017481
BinINT_STAT_BSI01431
BinINT_STAT_BSI1017481
BinINT_STAT_RBNEI01501
BinINT_STAT_RBNEI1017481
BinINT_STAT_TXBHCI01521
BinINT_STAT_TXBHCI1017481
BinINT_ENA_SET_INT_ENA_SET(11)01661
BinINT_ENA_SET_INT_ENA_SET(11)1021431
BinINT_ENA_SET_INT_ENA_SET(10)01301
BinINT_ENA_SET_INT_ENA_SET(10)1021431
BinINT_ENA_SET_INT_ENA_SET(9)01501
BinINT_ENA_SET_INT_ENA_SET(9)1021431
BinINT_ENA_SET_INT_ENA_SET(8)01151
BinINT_ENA_SET_INT_ENA_SET(8)1021431
BinINT_ENA_SET_INT_ENA_SET(7)01151
BinINT_ENA_SET_INT_ENA_SET(7)1021431
BinINT_ENA_SET_INT_ENA_SET(6)01151
BinINT_ENA_SET_INT_ENA_SET(6)1021431
BinINT_ENA_SET_INT_ENA_SET(5)01151
BinINT_ENA_SET_INT_ENA_SET(5)1021431
BinINT_ENA_SET_INT_ENA_SET(4)01151
BinINT_ENA_SET_INT_ENA_SET(4)1021431
BinINT_ENA_SET_INT_ENA_SET(3)01151
BinINT_ENA_SET_INT_ENA_SET(3)1021431
BinINT_ENA_SET_INT_ENA_SET(2)01201
BinINT_ENA_SET_INT_ENA_SET(2)1021431
BinINT_ENA_SET_INT_ENA_SET(1)01201
BinINT_ENA_SET_INT_ENA_SET(1)1021431
BinINT_ENA_SET_INT_ENA_SET(0)01201
BinINT_ENA_SET_INT_ENA_SET(0)1021431
BinINT_ENA_CLR_INT_ENA_CLR(11)014761
BinINT_ENA_CLR_INT_ENA_CLR(11)1021431
BinINT_ENA_CLR_INT_ENA_CLR(10)015121
BinINT_ENA_CLR_INT_ENA_CLR(10)1021431
BinINT_ENA_CLR_INT_ENA_CLR(9)014921
BinINT_ENA_CLR_INT_ENA_CLR(9)1021431
BinINT_ENA_CLR_INT_ENA_CLR(8)015271
BinINT_ENA_CLR_INT_ENA_CLR(8)1021431
BinINT_ENA_CLR_INT_ENA_CLR(7)015271
BinINT_ENA_CLR_INT_ENA_CLR(7)1021431
BinINT_ENA_CLR_INT_ENA_CLR(6)015271
BinINT_ENA_CLR_INT_ENA_CLR(6)1021431
BinINT_ENA_CLR_INT_ENA_CLR(5)015271
BinINT_ENA_CLR_INT_ENA_CLR(5)1021431
BinINT_ENA_CLR_INT_ENA_CLR(4)015271
BinINT_ENA_CLR_INT_ENA_CLR(4)1021431
BinINT_ENA_CLR_INT_ENA_CLR(3)015271
BinINT_ENA_CLR_INT_ENA_CLR(3)1021431
BinINT_ENA_CLR_INT_ENA_CLR(2)015221
BinINT_ENA_CLR_INT_ENA_CLR(2)1021431
BinINT_ENA_CLR_INT_ENA_CLR(1)015221
BinINT_ENA_CLR_INT_ENA_CLR(1)1021431
BinINT_ENA_CLR_INT_ENA_CLR(0)015221
BinINT_ENA_CLR_INT_ENA_CLR(0)1021431
BinINT_MASK_SET_INT_MASK_SET(11)01661
BinINT_MASK_SET_INT_MASK_SET(11)1020761
BinINT_MASK_SET_INT_MASK_SET(10)01401
BinINT_MASK_SET_INT_MASK_SET(10)1020761
BinINT_MASK_SET_INT_MASK_SET(9)01501
BinINT_MASK_SET_INT_MASK_SET(9)1020761
BinINT_MASK_SET_INT_MASK_SET(8)01151
BinINT_MASK_SET_INT_MASK_SET(8)1020761
BinINT_MASK_SET_INT_MASK_SET(7)01101
BinINT_MASK_SET_INT_MASK_SET(7)1020761
BinINT_MASK_SET_INT_MASK_SET(6)01101
BinINT_MASK_SET_INT_MASK_SET(6)1020761
BinINT_MASK_SET_INT_MASK_SET(5)01101
BinINT_MASK_SET_INT_MASK_SET(5)1020761
BinINT_MASK_SET_INT_MASK_SET(4)01101
BinINT_MASK_SET_INT_MASK_SET(4)1020761
BinINT_MASK_SET_INT_MASK_SET(3)01101
BinINT_MASK_SET_INT_MASK_SET(3)1020761
BinINT_MASK_SET_INT_MASK_SET(2)01101
BinINT_MASK_SET_INT_MASK_SET(2)1020761
BinINT_MASK_SET_INT_MASK_SET(1)01101
BinINT_MASK_SET_INT_MASK_SET(1)1020761
BinINT_MASK_SET_INT_MASK_SET(0)01101
BinINT_MASK_SET_INT_MASK_SET(0)1020761
BinINT_MASK_CLR_INT_MASK_CLR(11)014091
BinINT_MASK_CLR_INT_MASK_CLR(11)1020761
BinINT_MASK_CLR_INT_MASK_CLR(10)014351
BinINT_MASK_CLR_INT_MASK_CLR(10)1020761
BinINT_MASK_CLR_INT_MASK_CLR(9)014251
BinINT_MASK_CLR_INT_MASK_CLR(9)1020761
BinINT_MASK_CLR_INT_MASK_CLR(8)014601
BinINT_MASK_CLR_INT_MASK_CLR(8)1020761
BinINT_MASK_CLR_INT_MASK_CLR(7)014651
BinINT_MASK_CLR_INT_MASK_CLR(7)1020761
BinINT_MASK_CLR_INT_MASK_CLR(6)014651
BinINT_MASK_CLR_INT_MASK_CLR(6)1020761
BinINT_MASK_CLR_INT_MASK_CLR(5)014651
BinINT_MASK_CLR_INT_MASK_CLR(5)1020761
BinINT_MASK_CLR_INT_MASK_CLR(4)014651
BinINT_MASK_CLR_INT_MASK_CLR(4)1020761
BinINT_MASK_CLR_INT_MASK_CLR(3)014651
BinINT_MASK_CLR_INT_MASK_CLR(3)1020761
BinINT_MASK_CLR_INT_MASK_CLR(2)014651
BinINT_MASK_CLR_INT_MASK_CLR(2)1020761
BinINT_MASK_CLR_INT_MASK_CLR(1)014651
BinINT_MASK_CLR_INT_MASK_CLR(1)1020761
BinINT_MASK_CLR_INT_MASK_CLR(0)014651
BinINT_MASK_CLR_INT_MASK_CLR(0)1020761
BinBTR_PROP(6)012051
BinBTR_PROP(6)1018041
BinBTR_PROP(5)013131
BinBTR_PROP(5)1019111
BinBTR_PROP(4)012281
BinBTR_PROP(4)1018261
BinBTR_PROP(3)012721
BinBTR_PROP(3)1018701
BinBTR_PROP(2)0138201
BinBTR_PROP(2)1022201
BinBTR_PROP(1)012651
BinBTR_PROP(1)1018631
BinBTR_PROP(0)0117951
BinBTR_PROP(0)101951
BinBTR_PH1(5)013171
BinBTR_PH1(5)1019161
BinBTR_PH1(4)012531
BinBTR_PH1(4)1018521
BinBTR_PH1(3)012631
BinBTR_PH1(3)1018621
BinBTR_PH1(2)0113051
BinBTR_PH1(2)1028961
BinBTR_PH1(1)0119251
BinBTR_PH1(1)103251
BinBTR_PH1(0)0120911
BinBTR_PH1(0)104921
BinBTR_PH2(5)012061
BinBTR_PH2(5)1018051
BinBTR_PH2(4)013461
BinBTR_PH2(4)1019441
BinBTR_PH2(3)013151
BinBTR_PH2(3)1019141
BinBTR_PH2(2)0138741
BinBTR_PH2(2)1022751
BinBTR_PH2(1)0134121
BinBTR_PH2(1)1050031
BinBTR_PH2(0)0121581
BinBTR_PH2(0)105571
BinBTR_BRP(7)01141
BinBTR_BRP(7)1016151
BinBTR_BRP(6)01121
BinBTR_BRP(6)1016131
BinBTR_BRP(5)01121
BinBTR_BRP(5)1016131
BinBTR_BRP(4)01161
BinBTR_BRP(4)1016171
BinBTR_BRP(3)0148311
BinBTR_BRP(3)1032421
BinBTR_BRP(2)019291
BinBTR_BRP(2)1025231
BinBTR_BRP(1)0147621
BinBTR_BRP(1)1031701
BinBTR_BRP(0)0123161
BinBTR_BRP(0)1039141
BinBTR_SJW(4)012091
BinBTR_SJW(4)1018071
BinBTR_SJW(3)012661
BinBTR_SJW(3)1018641
BinBTR_SJW(2)019651
BinBTR_SJW(2)1025631
BinBTR_SJW(1)0126231
BinBTR_SJW(1)1010311
BinBTR_SJW(0)0131161
BinBTR_SJW(0)1047141
BinBTR_FD_PROP_FD(5)012431
BinBTR_FD_PROP_FD(5)1018411
BinBTR_FD_PROP_FD(4)012911
BinBTR_FD_PROP_FD(4)1018891
BinBTR_FD_PROP_FD(3)012731
BinBTR_FD_PROP_FD(3)1018711
BinBTR_FD_PROP_FD(2)0111951
BinBTR_FD_PROP_FD(2)1027841
BinBTR_FD_PROP_FD(1)0147061
BinBTR_FD_PROP_FD(1)1031141
BinBTR_FD_PROP_FD(0)0138901
BinBTR_FD_PROP_FD(0)1022891
BinBTR_FD_PH1_FD(4)012531
BinBTR_FD_PH1_FD(4)1018521
BinBTR_FD_PH1_FD(3)012991
BinBTR_FD_PH1_FD(3)1018981
BinBTR_FD_PH1_FD(2)0111761
BinBTR_FD_PH1_FD(2)1027661
BinBTR_FD_PH1_FD(1)0117041
BinBTR_FD_PH1_FD(1)101041
BinBTR_FD_PH1_FD(0)0138471
BinBTR_FD_PH1_FD(0)1022471
BinBTR_FD_PH2_FD(4)012811
BinBTR_FD_PH2_FD(4)1018801
BinBTR_FD_PH2_FD(3)013171
BinBTR_FD_PH2_FD(3)1019161
BinBTR_FD_PH2_FD(2)0112091
BinBTR_FD_PH2_FD(2)1027991
BinBTR_FD_PH2_FD(1)0117251
BinBTR_FD_PH2_FD(1)101251
BinBTR_FD_PH2_FD(0)0138681
BinBTR_FD_PH2_FD(0)1022671
BinBTR_FD_BRP_FD(7)01181
BinBTR_FD_BRP_FD(7)1016191
BinBTR_FD_BRP_FD(6)01301
BinBTR_FD_BRP_FD(6)1016311
BinBTR_FD_BRP_FD(5)01171
BinBTR_FD_BRP_FD(5)1016181
BinBTR_FD_BRP_FD(4)01271
BinBTR_FD_BRP_FD(4)1016281
BinBTR_FD_BRP_FD(3)01281
BinBTR_FD_BRP_FD(3)1016291
BinBTR_FD_BRP_FD(2)0148431
BinBTR_FD_BRP_FD(2)1032541
BinBTR_FD_BRP_FD(1)017641
BinBTR_FD_BRP_FD(1)1023631
BinBTR_FD_BRP_FD(0)0125981
BinBTR_FD_BRP_FD(0)1041891
BinBTR_FD_SJW_FD(4)012381
BinBTR_FD_SJW_FD(4)1018361
BinBTR_FD_SJW_FD(3)012821
BinBTR_FD_SJW_FD(3)1018801
BinBTR_FD_SJW_FD(2)019241
BinBTR_FD_SJW_FD(2)1025221
BinBTR_FD_SJW_FD(1)0125571
BinBTR_FD_SJW_FD(1)109651
BinBTR_FD_SJW_FD(0)019591
BinBTR_FD_SJW_FD(0)1025571
BinEWL_EW_LIMIT(7)01891
BinEWL_EW_LIMIT(7)1016901
BinEWL_EW_LIMIT(6)0116801
BinEWL_EW_LIMIT(6)10791
BinEWL_EW_LIMIT(5)0116721
BinEWL_EW_LIMIT(5)10711
BinEWL_EW_LIMIT(4)01781
BinEWL_EW_LIMIT(4)1016791
BinEWL_EW_LIMIT(3)01821
BinEWL_EW_LIMIT(3)1016831
BinEWL_EW_LIMIT(2)01851
BinEWL_EW_LIMIT(2)1016861
BinEWL_EW_LIMIT(1)01861
BinEWL_EW_LIMIT(1)1016871
BinEWL_EW_LIMIT(0)01871
BinEWL_EW_LIMIT(0)1016881
BinERP_ERP_LIMIT(7)0117431
BinERP_ERP_LIMIT(7)101421
BinERP_ERP_LIMIT(6)01241
BinERP_ERP_LIMIT(6)1016251
BinERP_ERP_LIMIT(5)01211
BinERP_ERP_LIMIT(5)1016221
BinERP_ERP_LIMIT(4)01271
BinERP_ERP_LIMIT(4)1016281
BinERP_ERP_LIMIT(3)01211
BinERP_ERP_LIMIT(3)1016221
BinERP_ERP_LIMIT(2)01251
BinERP_ERP_LIMIT(2)1016261
BinERP_ERP_LIMIT(1)01231
BinERP_ERP_LIMIT(1)1016241
BinERP_ERP_LIMIT(0)01211
BinERP_ERP_LIMIT(0)1016221
BinCTR_PRES_CTPV(8)012561
BinCTR_PRES_CTPV(8)1018571
BinCTR_PRES_CTPV(7)0126871
BinCTR_PRES_CTPV(7)1042881
BinCTR_PRES_CTPV(6)017031
BinCTR_PRES_CTPV(6)1023041
BinCTR_PRES_CTPV(5)0127281
BinCTR_PRES_CTPV(5)1043291
BinCTR_PRES_CTPV(4)0128391
BinCTR_PRES_CTPV(4)1044401
BinCTR_PRES_CTPV(3)019191
BinCTR_PRES_CTPV(3)1025201
BinCTR_PRES_CTPV(2)0128911
BinCTR_PRES_CTPV(2)1044921
BinCTR_PRES_CTPV(1)0110031
BinCTR_PRES_CTPV(1)1026041
BinCTR_PRES_CTPV(0)017501
BinCTR_PRES_CTPV(0)1023511
BinCTR_PRES_PTX01193641
BinCTR_PRES_PTX10455441
BinCTR_PRES_PRX01197591
BinCTR_PRES_PRX10455441
BinCTR_PRES_ENORM0166081
BinCTR_PRES_ENORM10455441
BinCTR_PRES_EFD0166081
BinCTR_PRES_EFD10455441
BinFILTER_A_MASK_BIT_MASK_A_VAL(28)013901
BinFILTER_A_MASK_BIT_MASK_A_VAL(28)1019911
BinFILTER_A_MASK_BIT_MASK_A_VAL(27)013651
BinFILTER_A_MASK_BIT_MASK_A_VAL(27)1019661
BinFILTER_A_MASK_BIT_MASK_A_VAL(26)013421
BinFILTER_A_MASK_BIT_MASK_A_VAL(26)1019431
BinFILTER_A_MASK_BIT_MASK_A_VAL(25)013281
BinFILTER_A_MASK_BIT_MASK_A_VAL(25)1019291
BinFILTER_A_MASK_BIT_MASK_A_VAL(24)013991
BinFILTER_A_MASK_BIT_MASK_A_VAL(24)1020001
BinFILTER_A_MASK_BIT_MASK_A_VAL(23)013621
BinFILTER_A_MASK_BIT_MASK_A_VAL(23)1019631
BinFILTER_A_MASK_BIT_MASK_A_VAL(22)013671
BinFILTER_A_MASK_BIT_MASK_A_VAL(22)1019681
BinFILTER_A_MASK_BIT_MASK_A_VAL(21)013451
BinFILTER_A_MASK_BIT_MASK_A_VAL(21)1019461
BinFILTER_A_MASK_BIT_MASK_A_VAL(20)013941
BinFILTER_A_MASK_BIT_MASK_A_VAL(20)1019951
BinFILTER_A_MASK_BIT_MASK_A_VAL(19)013801
BinFILTER_A_MASK_BIT_MASK_A_VAL(19)1019811
BinFILTER_A_MASK_BIT_MASK_A_VAL(18)013881
BinFILTER_A_MASK_BIT_MASK_A_VAL(18)1019891
BinFILTER_A_MASK_BIT_MASK_A_VAL(17)011041
BinFILTER_A_MASK_BIT_MASK_A_VAL(17)1017051
BinFILTER_A_MASK_BIT_MASK_A_VAL(16)01981
BinFILTER_A_MASK_BIT_MASK_A_VAL(16)1016991
BinFILTER_A_MASK_BIT_MASK_A_VAL(15)01981
BinFILTER_A_MASK_BIT_MASK_A_VAL(15)1016991
BinFILTER_A_MASK_BIT_MASK_A_VAL(14)011301
BinFILTER_A_MASK_BIT_MASK_A_VAL(14)1017311
BinFILTER_A_MASK_BIT_MASK_A_VAL(13)01901
BinFILTER_A_MASK_BIT_MASK_A_VAL(13)1016911
BinFILTER_A_MASK_BIT_MASK_A_VAL(12)011011
BinFILTER_A_MASK_BIT_MASK_A_VAL(12)1017021
BinFILTER_A_MASK_BIT_MASK_A_VAL(11)01771
BinFILTER_A_MASK_BIT_MASK_A_VAL(11)1016781
BinFILTER_A_MASK_BIT_MASK_A_VAL(10)012461
BinFILTER_A_MASK_BIT_MASK_A_VAL(10)1018471
BinFILTER_A_MASK_BIT_MASK_A_VAL(9)012851
BinFILTER_A_MASK_BIT_MASK_A_VAL(9)1018861
BinFILTER_A_MASK_BIT_MASK_A_VAL(8)012381
BinFILTER_A_MASK_BIT_MASK_A_VAL(8)1018391
BinFILTER_A_MASK_BIT_MASK_A_VAL(7)012571
BinFILTER_A_MASK_BIT_MASK_A_VAL(7)1018581
BinFILTER_A_MASK_BIT_MASK_A_VAL(6)012571
BinFILTER_A_MASK_BIT_MASK_A_VAL(6)1018581
BinFILTER_A_MASK_BIT_MASK_A_VAL(5)012511
BinFILTER_A_MASK_BIT_MASK_A_VAL(5)1018521
BinFILTER_A_MASK_BIT_MASK_A_VAL(4)012751
BinFILTER_A_MASK_BIT_MASK_A_VAL(4)1018761
BinFILTER_A_MASK_BIT_MASK_A_VAL(3)012861
BinFILTER_A_MASK_BIT_MASK_A_VAL(3)1018871
BinFILTER_A_MASK_BIT_MASK_A_VAL(2)012641
BinFILTER_A_MASK_BIT_MASK_A_VAL(2)1018651
BinFILTER_A_MASK_BIT_MASK_A_VAL(1)012441
BinFILTER_A_MASK_BIT_MASK_A_VAL(1)1018451
BinFILTER_A_MASK_BIT_MASK_A_VAL(0)012821
BinFILTER_A_MASK_BIT_MASK_A_VAL(0)1018831
BinFILTER_A_VAL_BIT_VAL_A_VAL(28)017641
BinFILTER_A_VAL_BIT_VAL_A_VAL(28)1023651
BinFILTER_A_VAL_BIT_VAL_A_VAL(27)017991
BinFILTER_A_VAL_BIT_VAL_A_VAL(27)1024001
BinFILTER_A_VAL_BIT_VAL_A_VAL(26)018201
BinFILTER_A_VAL_BIT_VAL_A_VAL(26)1024211
BinFILTER_A_VAL_BIT_VAL_A_VAL(25)018091
BinFILTER_A_VAL_BIT_VAL_A_VAL(25)1024101
BinFILTER_A_VAL_BIT_VAL_A_VAL(24)017661
BinFILTER_A_VAL_BIT_VAL_A_VAL(24)1023671
BinFILTER_A_VAL_BIT_VAL_A_VAL(23)018061
BinFILTER_A_VAL_BIT_VAL_A_VAL(23)1024071
BinFILTER_A_VAL_BIT_VAL_A_VAL(22)018081
BinFILTER_A_VAL_BIT_VAL_A_VAL(22)1024091
BinFILTER_A_VAL_BIT_VAL_A_VAL(21)017941
BinFILTER_A_VAL_BIT_VAL_A_VAL(21)1023951
BinFILTER_A_VAL_BIT_VAL_A_VAL(20)018331
BinFILTER_A_VAL_BIT_VAL_A_VAL(20)1024341
BinFILTER_A_VAL_BIT_VAL_A_VAL(19)018231
BinFILTER_A_VAL_BIT_VAL_A_VAL(19)1024241
BinFILTER_A_VAL_BIT_VAL_A_VAL(18)018231
BinFILTER_A_VAL_BIT_VAL_A_VAL(18)1024241
BinFILTER_A_VAL_BIT_VAL_A_VAL(17)014101
BinFILTER_A_VAL_BIT_VAL_A_VAL(17)1020111
BinFILTER_A_VAL_BIT_VAL_A_VAL(16)013851
BinFILTER_A_VAL_BIT_VAL_A_VAL(16)1019861
BinFILTER_A_VAL_BIT_VAL_A_VAL(15)013911
BinFILTER_A_VAL_BIT_VAL_A_VAL(15)1019921
BinFILTER_A_VAL_BIT_VAL_A_VAL(14)014491
BinFILTER_A_VAL_BIT_VAL_A_VAL(14)1020501
BinFILTER_A_VAL_BIT_VAL_A_VAL(13)013971
BinFILTER_A_VAL_BIT_VAL_A_VAL(13)1019981
BinFILTER_A_VAL_BIT_VAL_A_VAL(12)013801
BinFILTER_A_VAL_BIT_VAL_A_VAL(12)1019811
BinFILTER_A_VAL_BIT_VAL_A_VAL(11)014421
BinFILTER_A_VAL_BIT_VAL_A_VAL(11)1020431
BinFILTER_A_VAL_BIT_VAL_A_VAL(10)013941
BinFILTER_A_VAL_BIT_VAL_A_VAL(10)1019951
BinFILTER_A_VAL_BIT_VAL_A_VAL(9)013981
BinFILTER_A_VAL_BIT_VAL_A_VAL(9)1019991
BinFILTER_A_VAL_BIT_VAL_A_VAL(8)013771
BinFILTER_A_VAL_BIT_VAL_A_VAL(8)1019781
BinFILTER_A_VAL_BIT_VAL_A_VAL(7)013601
BinFILTER_A_VAL_BIT_VAL_A_VAL(7)1019611
BinFILTER_A_VAL_BIT_VAL_A_VAL(6)013931
BinFILTER_A_VAL_BIT_VAL_A_VAL(6)1019941
BinFILTER_A_VAL_BIT_VAL_A_VAL(5)014031
BinFILTER_A_VAL_BIT_VAL_A_VAL(5)1020041
BinFILTER_A_VAL_BIT_VAL_A_VAL(4)014051
BinFILTER_A_VAL_BIT_VAL_A_VAL(4)1020061
BinFILTER_A_VAL_BIT_VAL_A_VAL(3)013971
BinFILTER_A_VAL_BIT_VAL_A_VAL(3)1019981
BinFILTER_A_VAL_BIT_VAL_A_VAL(2)014101
BinFILTER_A_VAL_BIT_VAL_A_VAL(2)1020111
BinFILTER_A_VAL_BIT_VAL_A_VAL(1)014021
BinFILTER_A_VAL_BIT_VAL_A_VAL(1)1020031
BinFILTER_A_VAL_BIT_VAL_A_VAL(0)014221
BinFILTER_A_VAL_BIT_VAL_A_VAL(0)1020231
BinFILTER_B_MASK_BIT_MASK_B_VAL(28)01961
BinFILTER_B_MASK_BIT_MASK_B_VAL(28)1016971
BinFILTER_B_MASK_BIT_MASK_B_VAL(27)01961
BinFILTER_B_MASK_BIT_MASK_B_VAL(27)1016971
BinFILTER_B_MASK_BIT_MASK_B_VAL(26)01951
BinFILTER_B_MASK_BIT_MASK_B_VAL(26)1016961
BinFILTER_B_MASK_BIT_MASK_B_VAL(25)01961
BinFILTER_B_MASK_BIT_MASK_B_VAL(25)1016971
BinFILTER_B_MASK_BIT_MASK_B_VAL(24)011031
BinFILTER_B_MASK_BIT_MASK_B_VAL(24)1017041
BinFILTER_B_MASK_BIT_MASK_B_VAL(23)011011
BinFILTER_B_MASK_BIT_MASK_B_VAL(23)1017021
BinFILTER_B_MASK_BIT_MASK_B_VAL(22)011041
BinFILTER_B_MASK_BIT_MASK_B_VAL(22)1017051
BinFILTER_B_MASK_BIT_MASK_B_VAL(21)01901
BinFILTER_B_MASK_BIT_MASK_B_VAL(21)1016911
BinFILTER_B_MASK_BIT_MASK_B_VAL(20)01921
BinFILTER_B_MASK_BIT_MASK_B_VAL(20)1016931
BinFILTER_B_MASK_BIT_MASK_B_VAL(19)01811
BinFILTER_B_MASK_BIT_MASK_B_VAL(19)1016821
BinFILTER_B_MASK_BIT_MASK_B_VAL(18)011071
BinFILTER_B_MASK_BIT_MASK_B_VAL(18)1017081
BinFILTER_B_MASK_BIT_MASK_B_VAL(17)01161
BinFILTER_B_MASK_BIT_MASK_B_VAL(17)1016171
BinFILTER_B_MASK_BIT_MASK_B_VAL(16)01191
BinFILTER_B_MASK_BIT_MASK_B_VAL(16)1016201
BinFILTER_B_MASK_BIT_MASK_B_VAL(15)01281
BinFILTER_B_MASK_BIT_MASK_B_VAL(15)1016291
BinFILTER_B_MASK_BIT_MASK_B_VAL(14)01371
BinFILTER_B_MASK_BIT_MASK_B_VAL(14)1016381
BinFILTER_B_MASK_BIT_MASK_B_VAL(13)01351
BinFILTER_B_MASK_BIT_MASK_B_VAL(13)1016361
BinFILTER_B_MASK_BIT_MASK_B_VAL(12)01231
BinFILTER_B_MASK_BIT_MASK_B_VAL(12)1016241
BinFILTER_B_MASK_BIT_MASK_B_VAL(11)01211
BinFILTER_B_MASK_BIT_MASK_B_VAL(11)1016221
BinFILTER_B_MASK_BIT_MASK_B_VAL(10)01601
BinFILTER_B_MASK_BIT_MASK_B_VAL(10)1016611
BinFILTER_B_MASK_BIT_MASK_B_VAL(9)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(9)1016711
BinFILTER_B_MASK_BIT_MASK_B_VAL(8)01671
BinFILTER_B_MASK_BIT_MASK_B_VAL(8)1016681
BinFILTER_B_MASK_BIT_MASK_B_VAL(7)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(7)1016711
BinFILTER_B_MASK_BIT_MASK_B_VAL(6)01631
BinFILTER_B_MASK_BIT_MASK_B_VAL(6)1016641
BinFILTER_B_MASK_BIT_MASK_B_VAL(5)01621
BinFILTER_B_MASK_BIT_MASK_B_VAL(5)1016631
BinFILTER_B_MASK_BIT_MASK_B_VAL(4)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(4)1016711
BinFILTER_B_MASK_BIT_MASK_B_VAL(3)01621
BinFILTER_B_MASK_BIT_MASK_B_VAL(3)1016631
BinFILTER_B_MASK_BIT_MASK_B_VAL(2)01711
BinFILTER_B_MASK_BIT_MASK_B_VAL(2)1016721
BinFILTER_B_MASK_BIT_MASK_B_VAL(1)01671
BinFILTER_B_MASK_BIT_MASK_B_VAL(1)1016681
BinFILTER_B_MASK_BIT_MASK_B_VAL(0)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(0)1016711
BinFILTER_B_VAL_BIT_VAL_B_VAL(28)011961
BinFILTER_B_VAL_BIT_VAL_B_VAL(28)1017971
BinFILTER_B_VAL_BIT_VAL_B_VAL(27)011961
BinFILTER_B_VAL_BIT_VAL_B_VAL(27)1017971
BinFILTER_B_VAL_BIT_VAL_B_VAL(26)012171
BinFILTER_B_VAL_BIT_VAL_B_VAL(26)1018181
BinFILTER_B_VAL_BIT_VAL_B_VAL(25)011831
BinFILTER_B_VAL_BIT_VAL_B_VAL(25)1017841
BinFILTER_B_VAL_BIT_VAL_B_VAL(24)012181
BinFILTER_B_VAL_BIT_VAL_B_VAL(24)1018191
BinFILTER_B_VAL_BIT_VAL_B_VAL(23)012061
BinFILTER_B_VAL_BIT_VAL_B_VAL(23)1018071
BinFILTER_B_VAL_BIT_VAL_B_VAL(22)012001
BinFILTER_B_VAL_BIT_VAL_B_VAL(22)1018011
BinFILTER_B_VAL_BIT_VAL_B_VAL(21)012251
BinFILTER_B_VAL_BIT_VAL_B_VAL(21)1018261
BinFILTER_B_VAL_BIT_VAL_B_VAL(20)012291
BinFILTER_B_VAL_BIT_VAL_B_VAL(20)1018301
BinFILTER_B_VAL_BIT_VAL_B_VAL(19)012011
BinFILTER_B_VAL_BIT_VAL_B_VAL(19)1018021
BinFILTER_B_VAL_BIT_VAL_B_VAL(18)012091
BinFILTER_B_VAL_BIT_VAL_B_VAL(18)1018101
BinFILTER_B_VAL_BIT_VAL_B_VAL(17)01871
BinFILTER_B_VAL_BIT_VAL_B_VAL(17)1016881
BinFILTER_B_VAL_BIT_VAL_B_VAL(16)011041
BinFILTER_B_VAL_BIT_VAL_B_VAL(16)1017051
BinFILTER_B_VAL_BIT_VAL_B_VAL(15)01911
BinFILTER_B_VAL_BIT_VAL_B_VAL(15)1016921
BinFILTER_B_VAL_BIT_VAL_B_VAL(14)011061
BinFILTER_B_VAL_BIT_VAL_B_VAL(14)1017071
BinFILTER_B_VAL_BIT_VAL_B_VAL(13)011031
BinFILTER_B_VAL_BIT_VAL_B_VAL(13)1017041
BinFILTER_B_VAL_BIT_VAL_B_VAL(12)011081
BinFILTER_B_VAL_BIT_VAL_B_VAL(12)1017091
BinFILTER_B_VAL_BIT_VAL_B_VAL(11)011071
BinFILTER_B_VAL_BIT_VAL_B_VAL(11)1017081
BinFILTER_B_VAL_BIT_VAL_B_VAL(10)01931
BinFILTER_B_VAL_BIT_VAL_B_VAL(10)1016941
BinFILTER_B_VAL_BIT_VAL_B_VAL(9)011011
BinFILTER_B_VAL_BIT_VAL_B_VAL(9)1017021
BinFILTER_B_VAL_BIT_VAL_B_VAL(8)01981
BinFILTER_B_VAL_BIT_VAL_B_VAL(8)1016991
BinFILTER_B_VAL_BIT_VAL_B_VAL(7)01961
BinFILTER_B_VAL_BIT_VAL_B_VAL(7)1016971
BinFILTER_B_VAL_BIT_VAL_B_VAL(6)01861
BinFILTER_B_VAL_BIT_VAL_B_VAL(6)1016871
BinFILTER_B_VAL_BIT_VAL_B_VAL(5)011051
BinFILTER_B_VAL_BIT_VAL_B_VAL(5)1017061
BinFILTER_B_VAL_BIT_VAL_B_VAL(4)011141
BinFILTER_B_VAL_BIT_VAL_B_VAL(4)1017151
BinFILTER_B_VAL_BIT_VAL_B_VAL(3)01921
BinFILTER_B_VAL_BIT_VAL_B_VAL(3)1016931
BinFILTER_B_VAL_BIT_VAL_B_VAL(2)011151
BinFILTER_B_VAL_BIT_VAL_B_VAL(2)1017161
BinFILTER_B_VAL_BIT_VAL_B_VAL(1)01931
BinFILTER_B_VAL_BIT_VAL_B_VAL(1)1016941
BinFILTER_B_VAL_BIT_VAL_B_VAL(0)011081
BinFILTER_B_VAL_BIT_VAL_B_VAL(0)1017091
BinFILTER_C_MASK_BIT_MASK_C_VAL(28)01851
BinFILTER_C_MASK_BIT_MASK_C_VAL(28)1016861
BinFILTER_C_MASK_BIT_MASK_C_VAL(27)01951
BinFILTER_C_MASK_BIT_MASK_C_VAL(27)1016961
BinFILTER_C_MASK_BIT_MASK_C_VAL(26)01891
BinFILTER_C_MASK_BIT_MASK_C_VAL(26)1016901
BinFILTER_C_MASK_BIT_MASK_C_VAL(25)01821
BinFILTER_C_MASK_BIT_MASK_C_VAL(25)1016831
BinFILTER_C_MASK_BIT_MASK_C_VAL(24)011081
BinFILTER_C_MASK_BIT_MASK_C_VAL(24)1017091
BinFILTER_C_MASK_BIT_MASK_C_VAL(23)01791
BinFILTER_C_MASK_BIT_MASK_C_VAL(23)1016801
BinFILTER_C_MASK_BIT_MASK_C_VAL(22)011011
BinFILTER_C_MASK_BIT_MASK_C_VAL(22)1017021
BinFILTER_C_MASK_BIT_MASK_C_VAL(21)011051
BinFILTER_C_MASK_BIT_MASK_C_VAL(21)1017061
BinFILTER_C_MASK_BIT_MASK_C_VAL(20)01921
BinFILTER_C_MASK_BIT_MASK_C_VAL(20)1016931
BinFILTER_C_MASK_BIT_MASK_C_VAL(19)01851
BinFILTER_C_MASK_BIT_MASK_C_VAL(19)1016861
BinFILTER_C_MASK_BIT_MASK_C_VAL(18)01991
BinFILTER_C_MASK_BIT_MASK_C_VAL(18)1017001
BinFILTER_C_MASK_BIT_MASK_C_VAL(17)01191
BinFILTER_C_MASK_BIT_MASK_C_VAL(17)1016201
BinFILTER_C_MASK_BIT_MASK_C_VAL(16)01201
BinFILTER_C_MASK_BIT_MASK_C_VAL(16)1016211
BinFILTER_C_MASK_BIT_MASK_C_VAL(15)01341
BinFILTER_C_MASK_BIT_MASK_C_VAL(15)1016351
BinFILTER_C_MASK_BIT_MASK_C_VAL(14)01271
BinFILTER_C_MASK_BIT_MASK_C_VAL(14)1016281
BinFILTER_C_MASK_BIT_MASK_C_VAL(13)01281
BinFILTER_C_MASK_BIT_MASK_C_VAL(13)1016291
BinFILTER_C_MASK_BIT_MASK_C_VAL(12)01221
BinFILTER_C_MASK_BIT_MASK_C_VAL(12)1016231
BinFILTER_C_MASK_BIT_MASK_C_VAL(11)01141
BinFILTER_C_MASK_BIT_MASK_C_VAL(11)1016151
BinFILTER_C_MASK_BIT_MASK_C_VAL(10)01671
BinFILTER_C_MASK_BIT_MASK_C_VAL(10)1016681
BinFILTER_C_MASK_BIT_MASK_C_VAL(9)01671
BinFILTER_C_MASK_BIT_MASK_C_VAL(9)1016681
BinFILTER_C_MASK_BIT_MASK_C_VAL(8)01681
BinFILTER_C_MASK_BIT_MASK_C_VAL(8)1016691
BinFILTER_C_MASK_BIT_MASK_C_VAL(7)01621
BinFILTER_C_MASK_BIT_MASK_C_VAL(7)1016631
BinFILTER_C_MASK_BIT_MASK_C_VAL(6)01631
BinFILTER_C_MASK_BIT_MASK_C_VAL(6)1016641
BinFILTER_C_MASK_BIT_MASK_C_VAL(5)01631
BinFILTER_C_MASK_BIT_MASK_C_VAL(5)1016641
BinFILTER_C_MASK_BIT_MASK_C_VAL(4)01661
BinFILTER_C_MASK_BIT_MASK_C_VAL(4)1016671
BinFILTER_C_MASK_BIT_MASK_C_VAL(3)01681
BinFILTER_C_MASK_BIT_MASK_C_VAL(3)1016691
BinFILTER_C_MASK_BIT_MASK_C_VAL(2)01601
BinFILTER_C_MASK_BIT_MASK_C_VAL(2)1016611
BinFILTER_C_MASK_BIT_MASK_C_VAL(1)01771
BinFILTER_C_MASK_BIT_MASK_C_VAL(1)1016781
BinFILTER_C_MASK_BIT_MASK_C_VAL(0)01671
BinFILTER_C_MASK_BIT_MASK_C_VAL(0)1016681
BinFILTER_C_VAL_BIT_VAL_C_VAL(28)011841
BinFILTER_C_VAL_BIT_VAL_C_VAL(28)1017851
BinFILTER_C_VAL_BIT_VAL_C_VAL(27)011881
BinFILTER_C_VAL_BIT_VAL_C_VAL(27)1017891
BinFILTER_C_VAL_BIT_VAL_C_VAL(26)012011
BinFILTER_C_VAL_BIT_VAL_C_VAL(26)1018021
BinFILTER_C_VAL_BIT_VAL_C_VAL(25)011961
BinFILTER_C_VAL_BIT_VAL_C_VAL(25)1017971
BinFILTER_C_VAL_BIT_VAL_C_VAL(24)011931
BinFILTER_C_VAL_BIT_VAL_C_VAL(24)1017941
BinFILTER_C_VAL_BIT_VAL_C_VAL(23)011981
BinFILTER_C_VAL_BIT_VAL_C_VAL(23)1017991
BinFILTER_C_VAL_BIT_VAL_C_VAL(22)011901
BinFILTER_C_VAL_BIT_VAL_C_VAL(22)1017911
BinFILTER_C_VAL_BIT_VAL_C_VAL(21)012041
BinFILTER_C_VAL_BIT_VAL_C_VAL(21)1018051
BinFILTER_C_VAL_BIT_VAL_C_VAL(20)012251
BinFILTER_C_VAL_BIT_VAL_C_VAL(20)1018261
BinFILTER_C_VAL_BIT_VAL_C_VAL(19)012011
BinFILTER_C_VAL_BIT_VAL_C_VAL(19)1018021
BinFILTER_C_VAL_BIT_VAL_C_VAL(18)012061
BinFILTER_C_VAL_BIT_VAL_C_VAL(18)1018071
BinFILTER_C_VAL_BIT_VAL_C_VAL(17)01941
BinFILTER_C_VAL_BIT_VAL_C_VAL(17)1016951
BinFILTER_C_VAL_BIT_VAL_C_VAL(16)01971
BinFILTER_C_VAL_BIT_VAL_C_VAL(16)1016981
BinFILTER_C_VAL_BIT_VAL_C_VAL(15)011041
BinFILTER_C_VAL_BIT_VAL_C_VAL(15)1017051
BinFILTER_C_VAL_BIT_VAL_C_VAL(14)01931
BinFILTER_C_VAL_BIT_VAL_C_VAL(14)1016941
BinFILTER_C_VAL_BIT_VAL_C_VAL(13)011081
BinFILTER_C_VAL_BIT_VAL_C_VAL(13)1017091
BinFILTER_C_VAL_BIT_VAL_C_VAL(12)01981
BinFILTER_C_VAL_BIT_VAL_C_VAL(12)1016991
BinFILTER_C_VAL_BIT_VAL_C_VAL(11)011071
BinFILTER_C_VAL_BIT_VAL_C_VAL(11)1017081
BinFILTER_C_VAL_BIT_VAL_C_VAL(10)011041
BinFILTER_C_VAL_BIT_VAL_C_VAL(10)1017051
BinFILTER_C_VAL_BIT_VAL_C_VAL(9)011131
BinFILTER_C_VAL_BIT_VAL_C_VAL(9)1017141
BinFILTER_C_VAL_BIT_VAL_C_VAL(8)01961
BinFILTER_C_VAL_BIT_VAL_C_VAL(8)1016971
BinFILTER_C_VAL_BIT_VAL_C_VAL(7)01911
BinFILTER_C_VAL_BIT_VAL_C_VAL(7)1016921
BinFILTER_C_VAL_BIT_VAL_C_VAL(6)01901
BinFILTER_C_VAL_BIT_VAL_C_VAL(6)1016911
BinFILTER_C_VAL_BIT_VAL_C_VAL(5)01991
BinFILTER_C_VAL_BIT_VAL_C_VAL(5)1017001
BinFILTER_C_VAL_BIT_VAL_C_VAL(4)011001
BinFILTER_C_VAL_BIT_VAL_C_VAL(4)1017011
BinFILTER_C_VAL_BIT_VAL_C_VAL(3)01891
BinFILTER_C_VAL_BIT_VAL_C_VAL(3)1016901
BinFILTER_C_VAL_BIT_VAL_C_VAL(2)011071
BinFILTER_C_VAL_BIT_VAL_C_VAL(2)1017081
BinFILTER_C_VAL_BIT_VAL_C_VAL(1)011101
BinFILTER_C_VAL_BIT_VAL_C_VAL(1)1017111
BinFILTER_C_VAL_BIT_VAL_C_VAL(0)011101
BinFILTER_C_VAL_BIT_VAL_C_VAL(0)1017111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)0121
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)1016031
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)0121
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)1016031
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)0121
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)1016031
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)0121
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)1016031
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)0121
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)1016031
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)1016021
BinFILTER_CONTROL_FANB0120521
BinFILTER_CONTROL_FANB104511
BinFILTER_CONTROL_FANE0120291
BinFILTER_CONTROL_FANE104281
BinFILTER_CONTROL_FAFB0120601
BinFILTER_CONTROL_FAFB104591
BinFILTER_CONTROL_FAFE0120291
BinFILTER_CONTROL_FAFE104281
BinFILTER_CONTROL_FBNB011061
BinFILTER_CONTROL_FBNB1017071
BinFILTER_CONTROL_FBNE011051
BinFILTER_CONTROL_FBNE1017061
BinFILTER_CONTROL_FBFB011071
BinFILTER_CONTROL_FBFB1017081
BinFILTER_CONTROL_FBFE011051
BinFILTER_CONTROL_FBFE1017061
BinFILTER_CONTROL_FCNB011061
BinFILTER_CONTROL_FCNB1017071
BinFILTER_CONTROL_FCNE011051
BinFILTER_CONTROL_FCNE1017061
BinFILTER_CONTROL_FCFB011071
BinFILTER_CONTROL_FCFB1017081
BinFILTER_CONTROL_FCFE011051
BinFILTER_CONTROL_FCFE1017061
BinFILTER_CONTROL_FRNB0161
BinFILTER_CONTROL_FRNB1016071
BinFILTER_CONTROL_FRNE0151
BinFILTER_CONTROL_FRNE1016061
BinFILTER_CONTROL_FRFB0161
BinFILTER_CONTROL_FRFB1016071
BinFILTER_CONTROL_FRFE0151
BinFILTER_CONTROL_FRFE1016061
BinRX_SETTINGS_RTSOP0151
BinRX_SETTINGS_RTSOP1016061
BinRX_DATA_READ01510131
BinRX_DATA_READ10526141
BinTX_COMMAND_TXCE013541
BinTX_COMMAND_TXCE10252911
BinTX_COMMAND_TXCR01216021
BinTX_COMMAND_TXCR10252911
BinTX_COMMAND_TXCA0117341
BinTX_COMMAND_TXCA10252911
BinTX_COMMAND_TXB10165541
BinTX_COMMAND_TXB11081511
BinTX_COMMAND_TXB20155851
BinTX_COMMAND_TXB21071861
BinTX_COMMAND_TXB3013191
BinTX_COMMAND_TXB31019201
BinTX_COMMAND_TXB4013481
BinTX_COMMAND_TXB41019491
BinTX_COMMAND_TXB501841
BinTX_COMMAND_TXB51016851
BinTX_COMMAND_TXB601641
BinTX_COMMAND_TXB61016651
BinTX_COMMAND_TXB701761
BinTX_COMMAND_TXB71016771
BinTX_COMMAND_TXB801681
BinTX_COMMAND_TXB81016691
BinTX_PRIORITY_TXT1P(2)011111
BinTX_PRIORITY_TXT1P(2)1017121
BinTX_PRIORITY_TXT1P(1)011131
BinTX_PRIORITY_TXT1P(1)1017141
BinTX_PRIORITY_TXT1P(0)0117211
BinTX_PRIORITY_TXT1P(0)101201
BinTX_PRIORITY_TXT2P(2)01931
BinTX_PRIORITY_TXT2P(2)1016941
BinTX_PRIORITY_TXT2P(1)011211
BinTX_PRIORITY_TXT2P(1)1017221
BinTX_PRIORITY_TXT2P(0)011191
BinTX_PRIORITY_TXT2P(0)1017201
BinTX_PRIORITY_TXT3P(2)01841
BinTX_PRIORITY_TXT3P(2)1016851
BinTX_PRIORITY_TXT3P(1)01921
BinTX_PRIORITY_TXT3P(1)1016931
BinTX_PRIORITY_TXT3P(0)011021
BinTX_PRIORITY_TXT3P(0)1017031
BinTX_PRIORITY_TXT4P(2)01851
BinTX_PRIORITY_TXT4P(2)1016861
BinTX_PRIORITY_TXT4P(1)011001
BinTX_PRIORITY_TXT4P(1)1017011
BinTX_PRIORITY_TXT4P(0)01871
BinTX_PRIORITY_TXT4P(0)1016881
BinTX_PRIORITY_TXT5P(2)01271
BinTX_PRIORITY_TXT5P(2)1016281
BinTX_PRIORITY_TXT5P(1)01291
BinTX_PRIORITY_TXT5P(1)1016301
BinTX_PRIORITY_TXT5P(0)01221
BinTX_PRIORITY_TXT5P(0)1016231
BinTX_PRIORITY_TXT6P(2)01171
BinTX_PRIORITY_TXT6P(2)1016181
BinTX_PRIORITY_TXT6P(1)01191
BinTX_PRIORITY_TXT6P(1)1016201
BinTX_PRIORITY_TXT6P(0)01231
BinTX_PRIORITY_TXT6P(0)1016241
BinTX_PRIORITY_TXT7P(2)01231
BinTX_PRIORITY_TXT7P(2)1016241
BinTX_PRIORITY_TXT7P(1)01221
BinTX_PRIORITY_TXT7P(1)1016231
BinTX_PRIORITY_TXT7P(0)01301
BinTX_PRIORITY_TXT7P(0)1016311
BinTX_PRIORITY_TXT8P(2)01251
BinTX_PRIORITY_TXT8P(2)1016261
BinTX_PRIORITY_TXT8P(1)01251
BinTX_PRIORITY_TXT8P(1)1016261
BinTX_PRIORITY_TXT8P(0)01201
BinTX_PRIORITY_TXT8P(0)1016211
BinSSP_CFG_SSP_OFFSET(7)01251
BinSSP_CFG_SSP_OFFSET(7)1016261
BinSSP_CFG_SSP_OFFSET(6)01271
BinSSP_CFG_SSP_OFFSET(6)1016281
BinSSP_CFG_SSP_OFFSET(5)01461
BinSSP_CFG_SSP_OFFSET(5)1016471
BinSSP_CFG_SSP_OFFSET(4)01531
BinSSP_CFG_SSP_OFFSET(4)1016541
BinSSP_CFG_SSP_OFFSET(3)0143031
BinSSP_CFG_SSP_OFFSET(3)1027141
BinSSP_CFG_SSP_OFFSET(2)015271
BinSSP_CFG_SSP_OFFSET(2)1021281
BinSSP_CFG_SSP_OFFSET(1)0129001
BinSSP_CFG_SSP_OFFSET(1)1013111
BinSSP_CFG_SSP_OFFSET(0)0123971
BinSSP_CFG_SSP_OFFSET(0)1039981
BinSSP_CFG_SSP_SRC(1)01451
BinSSP_CFG_SSP_SRC(1)1016461
BinSSP_CFG_SSP_SRC(0)018141
BinSSP_CFG_SSP_SRC(0)1024031

Port:

 CONTROL_REGISTERS_IN
ElementFromToCountThreshold
BinDEVICE_ID_DEVICE_ID(15)0116011
BinDEVICE_ID_DEVICE_ID(14)0116011
BinDEVICE_ID_DEVICE_ID(13)1016011
BinDEVICE_ID_DEVICE_ID(12)1016011
BinDEVICE_ID_DEVICE_ID(11)0116011
BinDEVICE_ID_DEVICE_ID(10)1016011
BinDEVICE_ID_DEVICE_ID(9)0116011
BinDEVICE_ID_DEVICE_ID(8)1016011
BinDEVICE_ID_DEVICE_ID(7)0116011
BinDEVICE_ID_DEVICE_ID(6)0116011
BinDEVICE_ID_DEVICE_ID(5)0116011
BinDEVICE_ID_DEVICE_ID(4)0116011
BinDEVICE_ID_DEVICE_ID(3)0116011
BinDEVICE_ID_DEVICE_ID(2)0116011
BinDEVICE_ID_DEVICE_ID(1)1016011
BinDEVICE_ID_DEVICE_ID(0)0116011
BinVERSION_VER_MINOR(7)1016011
BinVERSION_VER_MINOR(6)1016011
BinVERSION_VER_MINOR(5)1016011
BinVERSION_VER_MINOR(4)1016011
BinVERSION_VER_MINOR(3)1016011
BinVERSION_VER_MINOR(2)0116011
BinVERSION_VER_MINOR(1)0116011
BinVERSION_VER_MINOR(0)0116011
BinVERSION_VER_MAJOR(7)1016011
BinVERSION_VER_MAJOR(6)1016011
BinVERSION_VER_MAJOR(5)1016011
BinVERSION_VER_MAJOR(4)1016011
BinVERSION_VER_MAJOR(3)1016011
BinVERSION_VER_MAJOR(2)1016011
BinVERSION_VER_MAJOR(1)0116011
BinVERSION_VER_MAJOR(0)1016011
BinSTATUS_RXNE0189521
BinSTATUS_RXNE1089501
BinSTATUS_DOR01311
BinSTATUS_DOR1016321
BinSTATUS_TXNF0124781
BinSTATUS_TXNF1024781
BinSTATUS_EFT01273581
BinSTATUS_EFT10289531
BinSTATUS_RXS01308731
BinSTATUS_RXS10324671
BinSTATUS_TXS01205601
BinSTATUS_TXS10221611
BinSTATUS_EWL017801
BinSTATUS_EWL1023801
BinSTATUS_IDLE01516611
BinSTATUS_IDLE10516681
BinSTATUS_PEXS01751
BinSTATUS_PEXS1016761
BinSTATUS_RXPE01131
BinSTATUS_RXPE1016141
BinSTATUS_TXPE013011
BinSTATUS_TXPE1019021
BinSTATUS_TXDPE01441
BinSTATUS_TXDPE1016451
BinSTATUS_STCNT016601
BinSTATUS_STCNT109411
BinSTATUS_STRGS0116011
BinSTATUS_SPRT016601
BinSTATUS_SPRT109411
BinINT_STAT_RXI018061
BinINT_STAT_RXI1024051
BinINT_STAT_TXI0112141
BinINT_STAT_TXI1028111
BinINT_STAT_EWLI015941
BinINT_STAT_EWLI1021941
BinINT_STAT_DOI01211
BinINT_STAT_DOI1016221
BinINT_STAT_FCSI0133041
BinINT_STAT_FCSI1048931
BinINT_STAT_ALI011001
BinINT_STAT_ALI1016991
BinINT_STAT_BEI0114171
BinINT_STAT_BEI1030101
BinINT_STAT_OFI011521
BinINT_STAT_OFI1017531
BinINT_STAT_RXFI01201
BinINT_STAT_RXFI1016211
BinINT_STAT_BSI0113111
BinINT_STAT_BSI1029051
BinINT_STAT_RBNEI019341
BinINT_STAT_RBNEI1025331
BinINT_STAT_TXBHCI0116791
BinINT_STAT_TXBHCI1032761
BinINT_ENA_SET_INT_ENA_SET(11)01661
BinINT_ENA_SET_INT_ENA_SET(11)1016671
BinINT_ENA_SET_INT_ENA_SET(10)01301
BinINT_ENA_SET_INT_ENA_SET(10)1016311
BinINT_ENA_SET_INT_ENA_SET(9)01501
BinINT_ENA_SET_INT_ENA_SET(9)1016511
BinINT_ENA_SET_INT_ENA_SET(8)01151
BinINT_ENA_SET_INT_ENA_SET(8)1016161
BinINT_ENA_SET_INT_ENA_SET(7)01151
BinINT_ENA_SET_INT_ENA_SET(7)1016161
BinINT_ENA_SET_INT_ENA_SET(6)01151
BinINT_ENA_SET_INT_ENA_SET(6)1016161
BinINT_ENA_SET_INT_ENA_SET(5)01151
BinINT_ENA_SET_INT_ENA_SET(5)1016161
BinINT_ENA_SET_INT_ENA_SET(4)01151
BinINT_ENA_SET_INT_ENA_SET(4)1016161
BinINT_ENA_SET_INT_ENA_SET(3)01151
BinINT_ENA_SET_INT_ENA_SET(3)1016161
BinINT_ENA_SET_INT_ENA_SET(2)01201
BinINT_ENA_SET_INT_ENA_SET(2)1016211
BinINT_ENA_SET_INT_ENA_SET(1)01151
BinINT_ENA_SET_INT_ENA_SET(1)1016161
BinINT_ENA_SET_INT_ENA_SET(0)01151
BinINT_ENA_SET_INT_ENA_SET(0)1016161
BinINT_MASK_SET_INT_MASK_SET(11)01221
BinINT_MASK_SET_INT_MASK_SET(11)1016231
BinINT_MASK_SET_INT_MASK_SET(10)01201
BinINT_MASK_SET_INT_MASK_SET(10)1016211
BinINT_MASK_SET_INT_MASK_SET(9)01201
BinINT_MASK_SET_INT_MASK_SET(9)1016211
BinINT_MASK_SET_INT_MASK_SET(8)0151
BinINT_MASK_SET_INT_MASK_SET(8)1016061
BinINT_MASK_SET_INT_MASK_SET(7)0151
BinINT_MASK_SET_INT_MASK_SET(7)1016061
BinINT_MASK_SET_INT_MASK_SET(6)0151
BinINT_MASK_SET_INT_MASK_SET(6)1016061
BinINT_MASK_SET_INT_MASK_SET(5)0151
BinINT_MASK_SET_INT_MASK_SET(5)1016061
BinINT_MASK_SET_INT_MASK_SET(4)0151
BinINT_MASK_SET_INT_MASK_SET(4)1016061
BinINT_MASK_SET_INT_MASK_SET(3)0151
BinINT_MASK_SET_INT_MASK_SET(3)1016061
BinINT_MASK_SET_INT_MASK_SET(2)0151
BinINT_MASK_SET_INT_MASK_SET(2)1016061
BinINT_MASK_SET_INT_MASK_SET(1)01101
BinINT_MASK_SET_INT_MASK_SET(1)1016111
BinINT_MASK_SET_INT_MASK_SET(0)01101
BinINT_MASK_SET_INT_MASK_SET(0)1016111
BinFAULT_STATE_ERA0184261
BinFAULT_STATE_ERA1084151
BinFAULT_STATE_ERP017711
BinFAULT_STATE_ERP1023721
BinFAULT_STATE_BOF0182271
BinFAULT_STATE_BOF1082381
BinREC_REC_VAL(8)011301
BinREC_REC_VAL(8)1017311
BinREC_REC_VAL(7)013501
BinREC_REC_VAL(7)1019511
BinREC_REC_VAL(6)012551
BinREC_REC_VAL(6)1018541
BinREC_REC_VAL(5)013631
BinREC_REC_VAL(5)1019631
BinREC_REC_VAL(4)014971
BinREC_REC_VAL(4)1020981
BinREC_REC_VAL(3)016851
BinREC_REC_VAL(3)1022851
BinREC_REC_VAL(2)016171
BinREC_REC_VAL(2)1022181
BinREC_REC_VAL(1)0111911
BinREC_REC_VAL(1)1027921
BinREC_REC_VAL(0)01112161
BinREC_REC_VAL(0)10128091
BinTEC_TEC_VAL(8)012491
BinTEC_TEC_VAL(8)1018501
BinTEC_TEC_VAL(7)015171
BinTEC_TEC_VAL(7)1021181
BinTEC_TEC_VAL(6)015011
BinTEC_TEC_VAL(6)1021021
BinTEC_TEC_VAL(5)018051
BinTEC_TEC_VAL(5)1024061
BinTEC_TEC_VAL(4)0119331
BinTEC_TEC_VAL(4)1035341
BinTEC_TEC_VAL(3)01127431
BinTEC_TEC_VAL(3)10143441
BinTEC_TEC_VAL(2)0129551
BinTEC_TEC_VAL(2)1045561
BinTEC_TEC_VAL(1)0133241
BinTEC_TEC_VAL(1)1049251
BinTEC_TEC_VAL(0)0135241
BinTEC_TEC_VAL(0)1051251
BinERR_NORM_ERR_NORM_VAL(15)01691
BinERR_NORM_ERR_NORM_VAL(15)1016671
BinERR_NORM_ERR_NORM_VAL(14)01671
BinERR_NORM_ERR_NORM_VAL(14)1016681
BinERR_NORM_ERR_NORM_VAL(13)01641
BinERR_NORM_ERR_NORM_VAL(13)1016611
BinERR_NORM_ERR_NORM_VAL(12)01621
BinERR_NORM_ERR_NORM_VAL(12)1016591
BinERR_NORM_ERR_NORM_VAL(11)01641
BinERR_NORM_ERR_NORM_VAL(11)1016641
BinERR_NORM_ERR_NORM_VAL(10)01691
BinERR_NORM_ERR_NORM_VAL(10)1016681
BinERR_NORM_ERR_NORM_VAL(9)01631
BinERR_NORM_ERR_NORM_VAL(9)1016621
BinERR_NORM_ERR_NORM_VAL(8)01711
BinERR_NORM_ERR_NORM_VAL(8)1016711
BinERR_NORM_ERR_NORM_VAL(7)01751
BinERR_NORM_ERR_NORM_VAL(7)1016731
BinERR_NORM_ERR_NORM_VAL(6)01971
BinERR_NORM_ERR_NORM_VAL(6)1016961
BinERR_NORM_ERR_NORM_VAL(5)011551
BinERR_NORM_ERR_NORM_VAL(5)1017521
BinERR_NORM_ERR_NORM_VAL(4)012761
BinERR_NORM_ERR_NORM_VAL(4)1018761
BinERR_NORM_ERR_NORM_VAL(3)016081
BinERR_NORM_ERR_NORM_VAL(3)1022051
BinERR_NORM_ERR_NORM_VAL(2)0113611
BinERR_NORM_ERR_NORM_VAL(2)1029581
BinERR_NORM_ERR_NORM_VAL(1)0130821
BinERR_NORM_ERR_NORM_VAL(1)1046781
BinERR_NORM_ERR_NORM_VAL(0)01117271
BinERR_NORM_ERR_NORM_VAL(0)10133231
BinERR_FD_ERR_FD_VAL(15)01631
BinERR_FD_ERR_FD_VAL(15)1016611
BinERR_FD_ERR_FD_VAL(14)01681
BinERR_FD_ERR_FD_VAL(14)1016671
BinERR_FD_ERR_FD_VAL(13)01671
BinERR_FD_ERR_FD_VAL(13)1016651
BinERR_FD_ERR_FD_VAL(12)01651
BinERR_FD_ERR_FD_VAL(12)1016651
BinERR_FD_ERR_FD_VAL(11)01611
BinERR_FD_ERR_FD_VAL(11)1016581
BinERR_FD_ERR_FD_VAL(10)01641
BinERR_FD_ERR_FD_VAL(10)1016611
BinERR_FD_ERR_FD_VAL(9)01751
BinERR_FD_ERR_FD_VAL(9)1016731
BinERR_FD_ERR_FD_VAL(8)01851
BinERR_FD_ERR_FD_VAL(8)1016821
BinERR_FD_ERR_FD_VAL(7)01981
BinERR_FD_ERR_FD_VAL(7)1016961
BinERR_FD_ERR_FD_VAL(6)011331
BinERR_FD_ERR_FD_VAL(6)1017321
BinERR_FD_ERR_FD_VAL(5)012091
BinERR_FD_ERR_FD_VAL(5)1018051
BinERR_FD_ERR_FD_VAL(4)013521
BinERR_FD_ERR_FD_VAL(4)1019521
BinERR_FD_ERR_FD_VAL(3)016801
BinERR_FD_ERR_FD_VAL(3)1022781
BinERR_FD_ERR_FD_VAL(2)0112951
BinERR_FD_ERR_FD_VAL(2)1028951
BinERR_FD_ERR_FD_VAL(1)0125231
BinERR_FD_ERR_FD_VAL(1)1041201
BinERR_FD_ERR_FD_VAL(0)0155891
BinERR_FD_ERR_FD_VAL(0)1071871
BinFILTER_STATUS_SFA016601
BinFILTER_STATUS_SFA109411
BinFILTER_STATUS_SFB011651
BinFILTER_STATUS_SFB1014361
BinFILTER_STATUS_SFC011651
BinFILTER_STATUS_SFC1014361
BinFILTER_STATUS_SFR011651
BinFILTER_STATUS_SFR1014361
BinRX_MEM_INFO_RX_BUFF_SIZE(12)011651
BinRX_MEM_INFO_RX_BUFF_SIZE(12)1014361
BinRX_MEM_INFO_RX_BUFF_SIZE(11)1016011
BinRX_MEM_INFO_RX_BUFF_SIZE(10)1016011
BinRX_MEM_INFO_RX_BUFF_SIZE(9)1016011
BinRX_MEM_INFO_RX_BUFF_SIZE(8)1016011
BinRX_MEM_INFO_RX_BUFF_SIZE(7)014951
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BinTX_FR_CTR_TX_FR_CTR_VAL(5)011261
BinTX_FR_CTR_TX_FR_CTR_VAL(5)1017271
BinTX_FR_CTR_TX_FR_CTR_VAL(4)011541
BinTX_FR_CTR_TX_FR_CTR_VAL(4)1017551
BinTX_FR_CTR_TX_FR_CTR_VAL(3)012611
BinTX_FR_CTR_TX_FR_CTR_VAL(3)1018621
BinTX_FR_CTR_TX_FR_CTR_VAL(2)016031
BinTX_FR_CTR_TX_FR_CTR_VAL(2)1022041
BinTX_FR_CTR_TX_FR_CTR_VAL(1)0110751
BinTX_FR_CTR_TX_FR_CTR_VAL(1)1026761
BinTX_FR_CTR_TX_FR_CTR_VAL(0)0122171
BinTX_FR_CTR_TX_FR_CTR_VAL(0)1038181
BinDEBUG_REGISTER_STUFF_COUNT(2)01337931
BinDEBUG_REGISTER_STUFF_COUNT(2)10353931
BinDEBUG_REGISTER_STUFF_COUNT(1)01717461
BinDEBUG_REGISTER_STUFF_COUNT(1)10733461
BinDEBUG_REGISTER_STUFF_COUNT(0)011424711
BinDEBUG_REGISTER_STUFF_COUNT(0)101440711
BinDEBUG_REGISTER_DESTUFF_COUNT(2)011171671
BinDEBUG_REGISTER_DESTUFF_COUNT(2)101187661
BinDEBUG_REGISTER_DESTUFF_COUNT(1)012432441
BinDEBUG_REGISTER_DESTUFF_COUNT(1)102448411
BinDEBUG_REGISTER_DESTUFF_COUNT(0)014870331
BinDEBUG_REGISTER_DESTUFF_COUNT(0)104886291
BinDEBUG_REGISTER_PC_ARB01559101
BinDEBUG_REGISTER_PC_ARB10575111
BinDEBUG_REGISTER_PC_CON01512661
BinDEBUG_REGISTER_PC_CON10528671
BinDEBUG_REGISTER_PC_DAT01366551
BinDEBUG_REGISTER_PC_DAT10382561
BinDEBUG_REGISTER_PC_STC01130171
BinDEBUG_REGISTER_PC_STC10146181
BinDEBUG_REGISTER_PC_CRC01311641
BinDEBUG_REGISTER_PC_CRC10327651
BinDEBUG_REGISTER_PC_CRCD01297021
BinDEBUG_REGISTER_PC_CRCD10313031
BinDEBUG_REGISTER_PC_ACK01295481
BinDEBUG_REGISTER_PC_ACK10311491
BinDEBUG_REGISTER_PC_ACKD01281201
BinDEBUG_REGISTER_PC_ACKD10297211
BinDEBUG_REGISTER_PC_EOF01272251
BinDEBUG_REGISTER_PC_EOF10288261
BinDEBUG_REGISTER_PC_INT01519041
BinDEBUG_REGISTER_PC_INT10535041
BinDEBUG_REGISTER_PC_SUSP0128491
BinDEBUG_REGISTER_PC_SUSP1044501
BinDEBUG_REGISTER_PC_OVR015291
BinDEBUG_REGISTER_PC_OVR1021301
BinDEBUG_REGISTER_PC_SOF01251481
BinDEBUG_REGISTER_PC_SOF10267491
BinYOLO_REG_YOLO_VAL(31)0116011
BinYOLO_REG_YOLO_VAL(30)0116011
BinYOLO_REG_YOLO_VAL(29)1016011
BinYOLO_REG_YOLO_VAL(28)0116011
BinYOLO_REG_YOLO_VAL(27)0116011
BinYOLO_REG_YOLO_VAL(26)0116011
BinYOLO_REG_YOLO_VAL(25)0116011
BinYOLO_REG_YOLO_VAL(24)1016011
BinYOLO_REG_YOLO_VAL(23)0116011
BinYOLO_REG_YOLO_VAL(22)1016011
BinYOLO_REG_YOLO_VAL(21)0116011
BinYOLO_REG_YOLO_VAL(20)1016011
BinYOLO_REG_YOLO_VAL(19)0116011
BinYOLO_REG_YOLO_VAL(18)0116011
BinYOLO_REG_YOLO_VAL(17)1016011
BinYOLO_REG_YOLO_VAL(16)0116011
BinYOLO_REG_YOLO_VAL(15)0116011
BinYOLO_REG_YOLO_VAL(14)1016011
BinYOLO_REG_YOLO_VAL(13)0116011
BinYOLO_REG_YOLO_VAL(12)0116011
BinYOLO_REG_YOLO_VAL(11)0116011
BinYOLO_REG_YOLO_VAL(10)0116011
BinYOLO_REG_YOLO_VAL(9)0116011
BinYOLO_REG_YOLO_VAL(8)1016011
BinYOLO_REG_YOLO_VAL(7)0116011
BinYOLO_REG_YOLO_VAL(6)0116011
BinYOLO_REG_YOLO_VAL(5)0116011
BinYOLO_REG_YOLO_VAL(4)1016011
BinYOLO_REG_YOLO_VAL(3)0116011
BinYOLO_REG_YOLO_VAL(2)0116011
BinYOLO_REG_YOLO_VAL(1)0116011
BinYOLO_REG_YOLO_VAL(0)0116011
BinTIMESTAMP_LOW_TIMESTAMP_LOW(31)01381
BinTIMESTAMP_LOW_TIMESTAMP_LOW(31)1016361
BinTIMESTAMP_LOW_TIMESTAMP_LOW(30)01611
BinTIMESTAMP_LOW_TIMESTAMP_LOW(30)1016511
BinTIMESTAMP_LOW_TIMESTAMP_LOW(29)01591
BinTIMESTAMP_LOW_TIMESTAMP_LOW(29)1016541
BinTIMESTAMP_LOW_TIMESTAMP_LOW(28)01611
BinTIMESTAMP_LOW_TIMESTAMP_LOW(28)1016551
BinTIMESTAMP_LOW_TIMESTAMP_LOW(27)01651
BinTIMESTAMP_LOW_TIMESTAMP_LOW(27)1016561
BinTIMESTAMP_LOW_TIMESTAMP_LOW(26)01651
BinTIMESTAMP_LOW_TIMESTAMP_LOW(26)1016581
BinTIMESTAMP_LOW_TIMESTAMP_LOW(25)01631
BinTIMESTAMP_LOW_TIMESTAMP_LOW(25)1016551
BinTIMESTAMP_LOW_TIMESTAMP_LOW(24)01691
BinTIMESTAMP_LOW_TIMESTAMP_LOW(24)1016561
BinTIMESTAMP_LOW_TIMESTAMP_LOW(23)01771
BinTIMESTAMP_LOW_TIMESTAMP_LOW(23)1016601
BinTIMESTAMP_LOW_TIMESTAMP_LOW(22)011101
BinTIMESTAMP_LOW_TIMESTAMP_LOW(22)1016751
BinTIMESTAMP_LOW_TIMESTAMP_LOW(21)011561
BinTIMESTAMP_LOW_TIMESTAMP_LOW(21)1017191
BinTIMESTAMP_LOW_TIMESTAMP_LOW(20)012571
BinTIMESTAMP_LOW_TIMESTAMP_LOW(20)1018061
BinTIMESTAMP_LOW_TIMESTAMP_LOW(19)015541
BinTIMESTAMP_LOW_TIMESTAMP_LOW(19)1020001
BinTIMESTAMP_LOW_TIMESTAMP_LOW(18)0110081
BinTIMESTAMP_LOW_TIMESTAMP_LOW(18)1024831
BinTIMESTAMP_LOW_TIMESTAMP_LOW(17)0120831
BinTIMESTAMP_LOW_TIMESTAMP_LOW(17)1034341
BinTIMESTAMP_LOW_TIMESTAMP_LOW(16)0141941
BinTIMESTAMP_LOW_TIMESTAMP_LOW(16)1054561
BinTIMESTAMP_LOW_TIMESTAMP_LOW(15)0183211
BinTIMESTAMP_LOW_TIMESTAMP_LOW(15)1095801
BinTIMESTAMP_LOW_TIMESTAMP_LOW(14)01167181
BinTIMESTAMP_LOW_TIMESTAMP_LOW(14)10178461
BinTIMESTAMP_LOW_TIMESTAMP_LOW(13)01334481
BinTIMESTAMP_LOW_TIMESTAMP_LOW(13)10345131
BinTIMESTAMP_LOW_TIMESTAMP_LOW(12)01669411
BinTIMESTAMP_LOW_TIMESTAMP_LOW(12)10679071
BinTIMESTAMP_LOW_TIMESTAMP_LOW(11)011338901
BinTIMESTAMP_LOW_TIMESTAMP_LOW(11)101347891
BinTIMESTAMP_LOW_TIMESTAMP_LOW(10)012678191
BinTIMESTAMP_LOW_TIMESTAMP_LOW(10)102686291
BinTIMESTAMP_LOW_TIMESTAMP_LOW(9)015355621
BinTIMESTAMP_LOW_TIMESTAMP_LOW(9)105363781
BinTIMESTAMP_LOW_TIMESTAMP_LOW(8)0110711381
BinTIMESTAMP_LOW_TIMESTAMP_LOW(8)1010719051
BinTIMESTAMP_LOW_TIMESTAMP_LOW(7)0121421511
BinTIMESTAMP_LOW_TIMESTAMP_LOW(7)1021429811
BinTIMESTAMP_LOW_TIMESTAMP_LOW(6)0142842531
BinTIMESTAMP_LOW_TIMESTAMP_LOW(6)1042850901
BinTIMESTAMP_LOW_TIMESTAMP_LOW(5)0185684941
BinTIMESTAMP_LOW_TIMESTAMP_LOW(5)1085692881
BinTIMESTAMP_LOW_TIMESTAMP_LOW(4)01171369451
BinTIMESTAMP_LOW_TIMESTAMP_LOW(4)10171377261
BinTIMESTAMP_LOW_TIMESTAMP_LOW(3)01342737761
BinTIMESTAMP_LOW_TIMESTAMP_LOW(3)10342746221
BinTIMESTAMP_LOW_TIMESTAMP_LOW(2)01685475501
BinTIMESTAMP_LOW_TIMESTAMP_LOW(2)10685483331
BinTIMESTAMP_LOW_TIMESTAMP_LOW(1)011370950311
BinTIMESTAMP_LOW_TIMESTAMP_LOW(1)101370958331
BinTIMESTAMP_LOW_TIMESTAMP_LOW(0)012741900401
BinTIMESTAMP_LOW_TIMESTAMP_LOW(0)102741908181
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(31)01171
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(31)1016161
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(30)01651
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(30)1016571
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(29)01661
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(29)1016611
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(28)01721
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(28)1016611
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(27)01711
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(27)1016591
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(26)01741
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(26)1016631
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(25)01631
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(25)1016581
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(24)01771
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(24)1016651
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(23)01641
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(23)1016551
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(22)01721
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(22)1016631
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(21)01711
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(21)1016651
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(20)01691
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(20)1016591
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(19)01671
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(19)1016561
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(18)01681
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(18)1016591
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(17)01651
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(17)1016541
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(16)01681
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(16)1016611
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(15)01641
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(15)1016541
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(14)01701
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(14)1016601
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(13)01571
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(13)1016511
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(12)01711
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(12)1016661
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(11)01631
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(11)1016531
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(10)01651
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(10)1016591
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(9)01751
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(9)1016661
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(8)01661
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(8)1016591
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(7)01631
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(7)1016551
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(6)01651
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(6)1016541
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(5)01671
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(5)1016551
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(4)01591
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(4)1016511
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(3)01651
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(3)1016571
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(2)01681
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(2)1016551
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(1)01671
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(1)1016581
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(0)01741
BinTIMESTAMP_HIGH_TIMESTAMP_HIGH(0)1016671

Signal:

 REG_SEL
ElementFromToCountThreshold
Bin(38)0139351
Bin(38)1044214841
Bin(37)0139351
Bin(37)1044175421
Bin(36)01451
Bin(36)1044138321
Bin(35)01101644301
Bin(35)10290446391
Bin(34)0111221
Bin(34)1044967151
Bin(33)0111221
Bin(33)1044269791
Bin(32)0134591
Bin(32)10393242861
Bin(31)015371
Bin(31)10393272081
Bin(30)0140661
Bin(30)10393236791
Bin(29)01282121
Bin(29)10392995331
Bin(28)0182041
Bin(28)10393195411
Bin(27)01510131
Bin(27)10392767321
Bin(26)01132231
Bin(26)10393145221
Bin(25)01124181
Bin(25)10392904911
Bin(24)01124181
Bin(24)10245967871
Bin(23)01200681
Bin(23)10393076771
Bin(22)01701
Bin(22)10355766731
Bin(21)01701
Bin(21)10355597051
Bin(20)0128351
Bin(20)10392956001
Bin(19)0128351
Bin(19)10355592661
Bin(18)0128351
Bin(18)10355640941
Bin(17)0128351
Bin(17)10355592661
Bin(16)0140821
Bin(16)10393222491
Bin(15)0140821
Bin(15)10393222451
Bin(14)01441531
Bin(14)10392835921
Bin(13)0121921
Bin(13)10392636911
Bin(12)01140661
Bin(12)10363940231
Bin(11)011122441
Bin(11)10392155011
Bin(10)0167111
Bin(10)10393210341
Bin(9)0166211
Bin(9)10393211241
Bin(8)014851
Bin(8)10393272601
Bin(7)015651
Bin(7)10393271801
Bin(6)015521
Bin(6)10393271931
Bin(5)016321
Bin(5)10393271131
Bin(4)0121541
Bin(4)10393255911
Bin(3)0114731
Bin(3)10393262721
Bin(2)0190478131
Bin(2)10302799321
Bin(1)01755351
Bin(1)10392522101
Bin(0)01251
Bin(0)10393277201

Signal:

 R_DATA_COMB
ElementFromToCountThreshold
Bin(31)01223551
Bin(31)10239561
Bin(30)01198041
Bin(30)10214051
Bin(29)01276781
Bin(29)10292791
Bin(28)01928481
Bin(28)10944491
Bin(27)01584301
Bin(27)10600311
Bin(26)01299121
Bin(26)10315131
Bin(25)013519471
Bin(25)103519471
Bin(24)01406691
Bin(24)10422701
Bin(23)01486381
Bin(23)10502391
Bin(22)011641201
Bin(22)101657211
Bin(21)01685401
Bin(21)10701411
Bin(20)01792351
Bin(20)10808361
Bin(19)01951791
Bin(19)10967801
Bin(18)0188566221
Bin(18)1088566221
Bin(17)0198352131
Bin(17)1098352131
Bin(16)0188260911
Bin(16)1088260911
Bin(15)015098121
Bin(15)105098121
Bin(14)0110739561
Bin(14)1010739561
Bin(13)012404881
Bin(13)102420891
Bin(12)012591891
Bin(12)102607901
Bin(11)014028801
Bin(11)104028801
Bin(10)0141879921
Bin(10)1041895931
Bin(9)0111155611
Bin(9)1011155611
Bin(8)0143328541
Bin(8)1043344551
Bin(7)0126064771
Bin(7)1026064771
Bin(6)0160184411
Bin(6)1060184411
Bin(5)01103848541
Bin(5)10103848541
Bin(4)0165313581
Bin(4)1065313581
Bin(3)01111197331
Bin(3)10111197331
Bin(2)01103768331
Bin(2)10103768331
Bin(1)0124240271
Bin(1)1024256281
Bin(0)0153533101
Bin(0)1053533101

Signal:

 READ_DATA_MASK_N
ElementFromToCountThreshold
Bin(31)01278234161
Bin(31)10384191
Bin(30)01278234161
Bin(30)10384191
Bin(29)01278234161
Bin(29)10384191
Bin(28)01278234161
Bin(28)10384191
Bin(27)01278234161
Bin(27)10384191
Bin(26)01278234161
Bin(26)10384191
Bin(25)01278234161
Bin(25)10384191
Bin(24)01278234161
Bin(24)10384191
Bin(23)01278237981
Bin(23)10380371
Bin(22)01278237981
Bin(22)10380371
Bin(21)01278237981
Bin(21)10380371
Bin(20)01278237981
Bin(20)10380371
Bin(19)01278237981
Bin(19)10380371
Bin(18)01278237981
Bin(18)10380371
Bin(17)01278237981
Bin(17)10380371
Bin(16)01278237981
Bin(16)10380371
Bin(15)01277256151
Bin(15)101362201
Bin(14)01277256151
Bin(14)101362201
Bin(13)01277256151
Bin(13)101362201
Bin(12)01277256151
Bin(12)101362201
Bin(11)01277256151
Bin(11)101362201
Bin(10)01277256151
Bin(10)101362201
Bin(9)01277256151
Bin(9)101362201
Bin(8)01277256151
Bin(8)101362201
Bin(7)01277268431
Bin(7)101349921
Bin(6)01277268431
Bin(6)101349921
Bin(5)01277268431
Bin(5)101349921
Bin(4)01277268431
Bin(4)101349921
Bin(3)01277268431
Bin(3)101349921
Bin(2)01277268431
Bin(2)101349921
Bin(1)01277268431
Bin(1)101349921
Bin(0)01277268431
Bin(0)101349921

Signal:

 CONTROL_REGISTERS_OUT_I
ElementFromToCountThreshold
BinMODE_RST018681
BinMODE_RST10328771
BinMODE_BMM01151
BinMODE_BMM1016161
BinMODE_STM011601
BinMODE_STM1017611
BinMODE_AFM01681
BinMODE_AFM1016691
BinMODE_FDE0118011
BinMODE_FDE102001
BinMODE_TTTM01551
BinMODE_TTTM1016561
BinMODE_ROM01511
BinMODE_ROM1016521
BinMODE_ACF01191
BinMODE_ACF1016201
BinMODE_TSTM0110271
BinMODE_TSTM1026271
BinMODE_RXBAM0117311
BinMODE_RXBAM101301
BinMODE_TXBBM01331
BinMODE_TXBBM1016341
BinMODE_SAM01551
BinMODE_SAM1016561
BinMODE_ERFM011531
BinMODE_ERFM1017541
BinSETTINGS_RTRLE0124541
BinSETTINGS_RTRLE1040551
BinSETTINGS_RTRTH(3)01221
BinSETTINGS_RTRTH(3)1016231
BinSETTINGS_RTRTH(2)01541
BinSETTINGS_RTRTH(2)1016551
BinSETTINGS_RTRTH(1)01221
BinSETTINGS_RTRTH(1)1016231
BinSETTINGS_RTRTH(0)01531
BinSETTINGS_RTRTH(0)1016541
BinSETTINGS_ILBP011301
BinSETTINGS_ILBP1017311
BinSETTINGS_ENA0164831
BinSETTINGS_ENA1080721
BinSETTINGS_NISOFD011301
BinSETTINGS_NISOFD1017311
BinSETTINGS_PEX01721
BinSETTINGS_PEX1016731
BinSETTINGS_TBFBO0125331
BinSETTINGS_TBFBO109441
BinSETTINGS_FDRF0141
BinSETTINGS_FDRF1016051
BinSETTINGS_PCHKE011241
BinSETTINGS_PCHKE1017251
BinCOMMAND_RXRPMV01211
BinCOMMAND_RXRPMV1030641
BinCOMMAND_RRB014601
BinCOMMAND_RRB1030641
BinCOMMAND_CDO01201
BinCOMMAND_CDO1030641
BinCOMMAND_ERCRST011701
BinCOMMAND_ERCRST1030641
BinCOMMAND_RXFCRST011241
BinCOMMAND_RXFCRST1030641
BinCOMMAND_TXFCRST011241
BinCOMMAND_TXFCRST1030641
BinCOMMAND_CPEXS01601
BinCOMMAND_CPEXS1030641
BinCOMMAND_CRXPE01401
BinCOMMAND_CRXPE1030641
BinCOMMAND_CTXPE014401
BinCOMMAND_CTXPE1030641
BinCOMMAND_CTXDPE01401
BinCOMMAND_CTXDPE1030641
BinINT_STAT_RXI01401
BinINT_STAT_RXI1017481
BinINT_STAT_TXI01421
BinINT_STAT_TXI1017481
BinINT_STAT_EWLI01301
BinINT_STAT_EWLI1017481
BinINT_STAT_DOI01161
BinINT_STAT_DOI1017481
BinINT_STAT_FCSI01801
BinINT_STAT_FCSI1017481
BinINT_STAT_ALI0151
BinINT_STAT_ALI1017481
BinINT_STAT_BEI01151
BinINT_STAT_BEI1017481
BinINT_STAT_OFI0151
BinINT_STAT_OFI1017481
BinINT_STAT_RXFI01151
BinINT_STAT_RXFI1017481
BinINT_STAT_BSI01431
BinINT_STAT_BSI1017481
BinINT_STAT_RBNEI01501
BinINT_STAT_RBNEI1017481
BinINT_STAT_TXBHCI01521
BinINT_STAT_TXBHCI1017481
BinINT_ENA_SET_INT_ENA_SET(11)01661
BinINT_ENA_SET_INT_ENA_SET(11)1022781
BinINT_ENA_SET_INT_ENA_SET(10)01301
BinINT_ENA_SET_INT_ENA_SET(10)1022781
BinINT_ENA_SET_INT_ENA_SET(9)01501
BinINT_ENA_SET_INT_ENA_SET(9)1022781
BinINT_ENA_SET_INT_ENA_SET(8)01151
BinINT_ENA_SET_INT_ENA_SET(8)1022781
BinINT_ENA_SET_INT_ENA_SET(7)01151
BinINT_ENA_SET_INT_ENA_SET(7)1023041
BinINT_ENA_SET_INT_ENA_SET(6)01151
BinINT_ENA_SET_INT_ENA_SET(6)1023041
BinINT_ENA_SET_INT_ENA_SET(5)01151
BinINT_ENA_SET_INT_ENA_SET(5)1023041
BinINT_ENA_SET_INT_ENA_SET(4)01151
BinINT_ENA_SET_INT_ENA_SET(4)1023041
BinINT_ENA_SET_INT_ENA_SET(3)01151
BinINT_ENA_SET_INT_ENA_SET(3)1023041
BinINT_ENA_SET_INT_ENA_SET(2)01201
BinINT_ENA_SET_INT_ENA_SET(2)1023041
BinINT_ENA_SET_INT_ENA_SET(1)01201
BinINT_ENA_SET_INT_ENA_SET(1)1023041
BinINT_ENA_SET_INT_ENA_SET(0)01201
BinINT_ENA_SET_INT_ENA_SET(0)1023041
BinINT_ENA_CLR_INT_ENA_CLR(11)014761
BinINT_ENA_CLR_INT_ENA_CLR(11)1021431
BinINT_ENA_CLR_INT_ENA_CLR(10)015121
BinINT_ENA_CLR_INT_ENA_CLR(10)1021431
BinINT_ENA_CLR_INT_ENA_CLR(9)014921
BinINT_ENA_CLR_INT_ENA_CLR(9)1021431
BinINT_ENA_CLR_INT_ENA_CLR(8)015271
BinINT_ENA_CLR_INT_ENA_CLR(8)1021431
BinINT_ENA_CLR_INT_ENA_CLR(7)015271
BinINT_ENA_CLR_INT_ENA_CLR(7)1021431
BinINT_ENA_CLR_INT_ENA_CLR(6)015271
BinINT_ENA_CLR_INT_ENA_CLR(6)1021431
BinINT_ENA_CLR_INT_ENA_CLR(5)015271
BinINT_ENA_CLR_INT_ENA_CLR(5)1021431
BinINT_ENA_CLR_INT_ENA_CLR(4)015271
BinINT_ENA_CLR_INT_ENA_CLR(4)1021431
BinINT_ENA_CLR_INT_ENA_CLR(3)015271
BinINT_ENA_CLR_INT_ENA_CLR(3)1021431
BinINT_ENA_CLR_INT_ENA_CLR(2)015221
BinINT_ENA_CLR_INT_ENA_CLR(2)1021431
BinINT_ENA_CLR_INT_ENA_CLR(1)015221
BinINT_ENA_CLR_INT_ENA_CLR(1)1021431
BinINT_ENA_CLR_INT_ENA_CLR(0)015221
BinINT_ENA_CLR_INT_ENA_CLR(0)1021431
BinINT_MASK_SET_INT_MASK_SET(11)01661
BinINT_MASK_SET_INT_MASK_SET(11)1021561
BinINT_MASK_SET_INT_MASK_SET(10)01401
BinINT_MASK_SET_INT_MASK_SET(10)1021561
BinINT_MASK_SET_INT_MASK_SET(9)01501
BinINT_MASK_SET_INT_MASK_SET(9)1021561
BinINT_MASK_SET_INT_MASK_SET(8)01151
BinINT_MASK_SET_INT_MASK_SET(8)1021561
BinINT_MASK_SET_INT_MASK_SET(7)01101
BinINT_MASK_SET_INT_MASK_SET(7)1022471
BinINT_MASK_SET_INT_MASK_SET(6)01101
BinINT_MASK_SET_INT_MASK_SET(6)1022471
BinINT_MASK_SET_INT_MASK_SET(5)01101
BinINT_MASK_SET_INT_MASK_SET(5)1022471
BinINT_MASK_SET_INT_MASK_SET(4)01101
BinINT_MASK_SET_INT_MASK_SET(4)1022471
BinINT_MASK_SET_INT_MASK_SET(3)01101
BinINT_MASK_SET_INT_MASK_SET(3)1022471
BinINT_MASK_SET_INT_MASK_SET(2)01101
BinINT_MASK_SET_INT_MASK_SET(2)1022471
BinINT_MASK_SET_INT_MASK_SET(1)01101
BinINT_MASK_SET_INT_MASK_SET(1)1022471
BinINT_MASK_SET_INT_MASK_SET(0)01101
BinINT_MASK_SET_INT_MASK_SET(0)1022471
BinINT_MASK_CLR_INT_MASK_CLR(11)014091
BinINT_MASK_CLR_INT_MASK_CLR(11)1020761
BinINT_MASK_CLR_INT_MASK_CLR(10)014351
BinINT_MASK_CLR_INT_MASK_CLR(10)1020761
BinINT_MASK_CLR_INT_MASK_CLR(9)014251
BinINT_MASK_CLR_INT_MASK_CLR(9)1020761
BinINT_MASK_CLR_INT_MASK_CLR(8)014601
BinINT_MASK_CLR_INT_MASK_CLR(8)1020761
BinINT_MASK_CLR_INT_MASK_CLR(7)014651
BinINT_MASK_CLR_INT_MASK_CLR(7)1020761
BinINT_MASK_CLR_INT_MASK_CLR(6)014651
BinINT_MASK_CLR_INT_MASK_CLR(6)1020761
BinINT_MASK_CLR_INT_MASK_CLR(5)014651
BinINT_MASK_CLR_INT_MASK_CLR(5)1020761
BinINT_MASK_CLR_INT_MASK_CLR(4)014651
BinINT_MASK_CLR_INT_MASK_CLR(4)1020761
BinINT_MASK_CLR_INT_MASK_CLR(3)014651
BinINT_MASK_CLR_INT_MASK_CLR(3)1020761
BinINT_MASK_CLR_INT_MASK_CLR(2)014651
BinINT_MASK_CLR_INT_MASK_CLR(2)1020761
BinINT_MASK_CLR_INT_MASK_CLR(1)014651
BinINT_MASK_CLR_INT_MASK_CLR(1)1020761
BinINT_MASK_CLR_INT_MASK_CLR(0)014651
BinINT_MASK_CLR_INT_MASK_CLR(0)1020761
BinBTR_PROP(6)012051
BinBTR_PROP(6)1018041
BinBTR_PROP(5)013131
BinBTR_PROP(5)1019111
BinBTR_PROP(4)012281
BinBTR_PROP(4)1018261
BinBTR_PROP(3)012721
BinBTR_PROP(3)1018701
BinBTR_PROP(2)0138201
BinBTR_PROP(2)1022201
BinBTR_PROP(1)012651
BinBTR_PROP(1)1018631
BinBTR_PROP(0)0117951
BinBTR_PROP(0)101951
BinBTR_PH1(5)013261
BinBTR_PH1(5)1019641
BinBTR_PH1(4)012881
BinBTR_PH1(4)1019091
BinBTR_PH1(3)013161
BinBTR_PH1(3)1019541
BinBTR_PH1(2)0114111
BinBTR_PH1(2)1030411
BinBTR_PH1(1)0121751
BinBTR_PH1(1)105351
BinBTR_PH1(0)0144851
BinBTR_PH1(0)104921
BinBTR_PH2(5)012691
BinBTR_PH2(5)1077701
BinBTR_PH2(4)015051
BinBTR_PH2(4)1081361
BinBTR_PH2(3)017001
BinBTR_PH2(3)1082161
BinBTR_PH2(2)0138791
BinBTR_PH2(2)1022761
BinBTR_PH2(1)0134181
BinBTR_PH2(1)1050091
BinBTR_PH2(0)0121581
BinBTR_PH2(0)105571
BinBTR_BRP(7)01141
BinBTR_BRP(7)1081601
BinBTR_BRP(6)01121
BinBTR_BRP(6)1081581
BinBTR_BRP(5)01121
BinBTR_BRP(5)1081581
BinBTR_BRP(4)01161
BinBTR_BRP(4)1016271
BinBTR_BRP(3)0148411
BinBTR_BRP(3)1032421
BinBTR_BRP(2)019291
BinBTR_BRP(2)1025331
BinBTR_BRP(1)0147721
BinBTR_BRP(1)1031701
BinBTR_BRP(0)0123161
BinBTR_BRP(0)1039241
BinBTR_SJW(4)012091
BinBTR_SJW(4)1018071
BinBTR_SJW(3)012661
BinBTR_SJW(3)1018641
BinBTR_SJW(2)019651
BinBTR_SJW(2)1025631
BinBTR_SJW(1)0126231
BinBTR_SJW(1)1010311
BinBTR_SJW(0)0131161
BinBTR_SJW(0)1047141
BinBTR_FD_PROP_FD(5)012431
BinBTR_FD_PROP_FD(5)1018411
BinBTR_FD_PROP_FD(4)012911
BinBTR_FD_PROP_FD(4)1018891
BinBTR_FD_PROP_FD(3)012731
BinBTR_FD_PROP_FD(3)1018711
BinBTR_FD_PROP_FD(2)0111951
BinBTR_FD_PROP_FD(2)1027841
BinBTR_FD_PROP_FD(1)0147061
BinBTR_FD_PROP_FD(1)1031141
BinBTR_FD_PROP_FD(0)0138901
BinBTR_FD_PROP_FD(0)1022891
BinBTR_FD_PH1_FD(4)012561
BinBTR_FD_PH1_FD(4)1059871
BinBTR_FD_PH1_FD(3)013031
BinBTR_FD_PH1_FD(3)1060401
BinBTR_FD_PH1_FD(2)0111841
BinBTR_FD_PH1_FD(2)1069111
BinBTR_FD_PH1_FD(1)0158561
BinBTR_FD_PH1_FD(1)101331
BinBTR_FD_PH1_FD(0)0160191
BinBTR_FD_PH1_FD(0)1022931
BinBTR_FD_PH2_FD(4)013211
BinBTR_FD_PH2_FD(4)1079021
BinBTR_FD_PH2_FD(3)014051
BinBTR_FD_PH2_FD(3)1079301
BinBTR_FD_PH2_FD(2)0112131
BinBTR_FD_PH2_FD(2)1028191
BinBTR_FD_PH2_FD(1)0117271
BinBTR_FD_PH2_FD(1)101251
BinBTR_FD_PH2_FD(0)0138831
BinBTR_FD_PH2_FD(0)1022901
BinBTR_FD_BRP_FD(7)01181
BinBTR_FD_BRP_FD(7)1081401
BinBTR_FD_BRP_FD(6)01301
BinBTR_FD_BRP_FD(6)1081521
BinBTR_FD_BRP_FD(5)01171
BinBTR_FD_BRP_FD(5)1081391
BinBTR_FD_BRP_FD(4)01271
BinBTR_FD_BRP_FD(4)1016381
BinBTR_FD_BRP_FD(3)01281
BinBTR_FD_BRP_FD(3)1016291
BinBTR_FD_BRP_FD(2)0148431
BinBTR_FD_BRP_FD(2)1032641
BinBTR_FD_BRP_FD(1)017641
BinBTR_FD_BRP_FD(1)1023631
BinBTR_FD_BRP_FD(0)0125981
BinBTR_FD_BRP_FD(0)1041991
BinBTR_FD_SJW_FD(4)012381
BinBTR_FD_SJW_FD(4)1018361
BinBTR_FD_SJW_FD(3)012821
BinBTR_FD_SJW_FD(3)1018801
BinBTR_FD_SJW_FD(2)019241
BinBTR_FD_SJW_FD(2)1025221
BinBTR_FD_SJW_FD(1)0125571
BinBTR_FD_SJW_FD(1)109651
BinBTR_FD_SJW_FD(0)019591
BinBTR_FD_SJW_FD(0)1025571
BinEWL_EW_LIMIT(7)01891
BinEWL_EW_LIMIT(7)1016901
BinEWL_EW_LIMIT(6)0116801
BinEWL_EW_LIMIT(6)10791
BinEWL_EW_LIMIT(5)0116721
BinEWL_EW_LIMIT(5)10711
BinEWL_EW_LIMIT(4)01781
BinEWL_EW_LIMIT(4)1016791
BinEWL_EW_LIMIT(3)01821
BinEWL_EW_LIMIT(3)1016831
BinEWL_EW_LIMIT(2)01851
BinEWL_EW_LIMIT(2)1016861
BinEWL_EW_LIMIT(1)01861
BinEWL_EW_LIMIT(1)1016871
BinEWL_EW_LIMIT(0)01871
BinEWL_EW_LIMIT(0)1016881
BinERP_ERP_LIMIT(7)0117431
BinERP_ERP_LIMIT(7)101421
BinERP_ERP_LIMIT(6)01241
BinERP_ERP_LIMIT(6)1016251
BinERP_ERP_LIMIT(5)01211
BinERP_ERP_LIMIT(5)1016221
BinERP_ERP_LIMIT(4)01271
BinERP_ERP_LIMIT(4)1016281
BinERP_ERP_LIMIT(3)01211
BinERP_ERP_LIMIT(3)1016221
BinERP_ERP_LIMIT(2)01251
BinERP_ERP_LIMIT(2)1016261
BinERP_ERP_LIMIT(1)01231
BinERP_ERP_LIMIT(1)1016241
BinERP_ERP_LIMIT(0)01211
BinERP_ERP_LIMIT(0)1016221
BinCTR_PRES_CTPV(8)013651
BinCTR_PRES_CTPV(8)1087471
BinCTR_PRES_CTPV(7)0126871
BinCTR_PRES_CTPV(7)1043181
BinCTR_PRES_CTPV(6)017031
BinCTR_PRES_CTPV(6)1023351
BinCTR_PRES_CTPV(5)0127281
BinCTR_PRES_CTPV(5)1043531
BinCTR_PRES_CTPV(4)0128391
BinCTR_PRES_CTPV(4)1044641
BinCTR_PRES_CTPV(3)019201
BinCTR_PRES_CTPV(3)1025461
BinCTR_PRES_CTPV(2)0128911
BinCTR_PRES_CTPV(2)1045271
BinCTR_PRES_CTPV(1)0110041
BinCTR_PRES_CTPV(1)1026261
BinCTR_PRES_CTPV(0)017501
BinCTR_PRES_CTPV(0)1023741
BinCTR_PRES_PTX01193641
BinCTR_PRES_PTX10455441
BinCTR_PRES_PRX01197591
BinCTR_PRES_PRX10455441
BinCTR_PRES_ENORM0166081
BinCTR_PRES_ENORM10455441
BinCTR_PRES_EFD0166081
BinCTR_PRES_EFD10455441
BinFILTER_A_MASK_BIT_MASK_A_VAL(28)013901
BinFILTER_A_MASK_BIT_MASK_A_VAL(28)1024081
BinFILTER_A_MASK_BIT_MASK_A_VAL(27)013651
BinFILTER_A_MASK_BIT_MASK_A_VAL(27)1022511
BinFILTER_A_MASK_BIT_MASK_A_VAL(26)013421
BinFILTER_A_MASK_BIT_MASK_A_VAL(26)1022771
BinFILTER_A_MASK_BIT_MASK_A_VAL(25)013281
BinFILTER_A_MASK_BIT_MASK_A_VAL(25)1022991
BinFILTER_A_MASK_BIT_MASK_A_VAL(24)013991
BinFILTER_A_MASK_BIT_MASK_A_VAL(24)1024021
BinFILTER_A_MASK_BIT_MASK_A_VAL(23)013621
BinFILTER_A_MASK_BIT_MASK_A_VAL(23)1021801
BinFILTER_A_MASK_BIT_MASK_A_VAL(22)013671
BinFILTER_A_MASK_BIT_MASK_A_VAL(22)1023251
BinFILTER_A_MASK_BIT_MASK_A_VAL(21)013451
BinFILTER_A_MASK_BIT_MASK_A_VAL(21)1022211
BinFILTER_A_MASK_BIT_MASK_A_VAL(20)013941
BinFILTER_A_MASK_BIT_MASK_A_VAL(20)1021871
BinFILTER_A_MASK_BIT_MASK_A_VAL(19)013801
BinFILTER_A_MASK_BIT_MASK_A_VAL(19)1022511
BinFILTER_A_MASK_BIT_MASK_A_VAL(18)013881
BinFILTER_A_MASK_BIT_MASK_A_VAL(18)1023521
BinFILTER_A_MASK_BIT_MASK_A_VAL(17)011041
BinFILTER_A_MASK_BIT_MASK_A_VAL(17)1018201
BinFILTER_A_MASK_BIT_MASK_A_VAL(16)01981
BinFILTER_A_MASK_BIT_MASK_A_VAL(16)1017881
BinFILTER_A_MASK_BIT_MASK_A_VAL(15)01981
BinFILTER_A_MASK_BIT_MASK_A_VAL(15)1019561
BinFILTER_A_MASK_BIT_MASK_A_VAL(14)011301
BinFILTER_A_MASK_BIT_MASK_A_VAL(14)1022181
BinFILTER_A_MASK_BIT_MASK_A_VAL(13)01901
BinFILTER_A_MASK_BIT_MASK_A_VAL(13)1021921
BinFILTER_A_MASK_BIT_MASK_A_VAL(12)011011
BinFILTER_A_MASK_BIT_MASK_A_VAL(12)1020971
BinFILTER_A_MASK_BIT_MASK_A_VAL(11)01771
BinFILTER_A_MASK_BIT_MASK_A_VAL(11)1020651
BinFILTER_A_MASK_BIT_MASK_A_VAL(10)012461
BinFILTER_A_MASK_BIT_MASK_A_VAL(10)1025561
BinFILTER_A_MASK_BIT_MASK_A_VAL(9)012851
BinFILTER_A_MASK_BIT_MASK_A_VAL(9)1023351
BinFILTER_A_MASK_BIT_MASK_A_VAL(8)012381
BinFILTER_A_MASK_BIT_MASK_A_VAL(8)1023321
BinFILTER_A_MASK_BIT_MASK_A_VAL(7)012571
BinFILTER_A_MASK_BIT_MASK_A_VAL(7)1023231
BinFILTER_A_MASK_BIT_MASK_A_VAL(6)012571
BinFILTER_A_MASK_BIT_MASK_A_VAL(6)1024331
BinFILTER_A_MASK_BIT_MASK_A_VAL(5)012511
BinFILTER_A_MASK_BIT_MASK_A_VAL(5)1023951
BinFILTER_A_MASK_BIT_MASK_A_VAL(4)012751
BinFILTER_A_MASK_BIT_MASK_A_VAL(4)1028491
BinFILTER_A_MASK_BIT_MASK_A_VAL(3)012861
BinFILTER_A_MASK_BIT_MASK_A_VAL(3)1023941
BinFILTER_A_MASK_BIT_MASK_A_VAL(2)012641
BinFILTER_A_MASK_BIT_MASK_A_VAL(2)1022061
BinFILTER_A_MASK_BIT_MASK_A_VAL(1)012441
BinFILTER_A_MASK_BIT_MASK_A_VAL(1)1024761
BinFILTER_A_MASK_BIT_MASK_A_VAL(0)012821
BinFILTER_A_MASK_BIT_MASK_A_VAL(0)1024881
BinFILTER_A_VAL_BIT_VAL_A_VAL(28)017641
BinFILTER_A_VAL_BIT_VAL_A_VAL(28)1024361
BinFILTER_A_VAL_BIT_VAL_A_VAL(27)017991
BinFILTER_A_VAL_BIT_VAL_A_VAL(27)1024651
BinFILTER_A_VAL_BIT_VAL_A_VAL(26)018201
BinFILTER_A_VAL_BIT_VAL_A_VAL(26)1024841
BinFILTER_A_VAL_BIT_VAL_A_VAL(25)018091
BinFILTER_A_VAL_BIT_VAL_A_VAL(25)1024771
BinFILTER_A_VAL_BIT_VAL_A_VAL(24)017661
BinFILTER_A_VAL_BIT_VAL_A_VAL(24)1024361
BinFILTER_A_VAL_BIT_VAL_A_VAL(23)018061
BinFILTER_A_VAL_BIT_VAL_A_VAL(23)1024331
BinFILTER_A_VAL_BIT_VAL_A_VAL(22)018081
BinFILTER_A_VAL_BIT_VAL_A_VAL(22)1024311
BinFILTER_A_VAL_BIT_VAL_A_VAL(21)017941
BinFILTER_A_VAL_BIT_VAL_A_VAL(21)1024191
BinFILTER_A_VAL_BIT_VAL_A_VAL(20)018331
BinFILTER_A_VAL_BIT_VAL_A_VAL(20)1024621
BinFILTER_A_VAL_BIT_VAL_A_VAL(19)018231
BinFILTER_A_VAL_BIT_VAL_A_VAL(19)1024451
BinFILTER_A_VAL_BIT_VAL_A_VAL(18)018231
BinFILTER_A_VAL_BIT_VAL_A_VAL(18)1024511
BinFILTER_A_VAL_BIT_VAL_A_VAL(17)014101
BinFILTER_A_VAL_BIT_VAL_A_VAL(17)1020151
BinFILTER_A_VAL_BIT_VAL_A_VAL(16)013851
BinFILTER_A_VAL_BIT_VAL_A_VAL(16)1019901
BinFILTER_A_VAL_BIT_VAL_A_VAL(15)013911
BinFILTER_A_VAL_BIT_VAL_A_VAL(15)1028291
BinFILTER_A_VAL_BIT_VAL_A_VAL(14)014491
BinFILTER_A_VAL_BIT_VAL_A_VAL(14)1028551
BinFILTER_A_VAL_BIT_VAL_A_VAL(13)013971
BinFILTER_A_VAL_BIT_VAL_A_VAL(13)1028031
BinFILTER_A_VAL_BIT_VAL_A_VAL(12)013801
BinFILTER_A_VAL_BIT_VAL_A_VAL(12)1027221
BinFILTER_A_VAL_BIT_VAL_A_VAL(11)014421
BinFILTER_A_VAL_BIT_VAL_A_VAL(11)1029761
BinFILTER_A_VAL_BIT_VAL_A_VAL(10)013941
BinFILTER_A_VAL_BIT_VAL_A_VAL(10)1026721
BinFILTER_A_VAL_BIT_VAL_A_VAL(9)013981
BinFILTER_A_VAL_BIT_VAL_A_VAL(9)1023881
BinFILTER_A_VAL_BIT_VAL_A_VAL(8)013771
BinFILTER_A_VAL_BIT_VAL_A_VAL(8)1030071
BinFILTER_A_VAL_BIT_VAL_A_VAL(7)013601
BinFILTER_A_VAL_BIT_VAL_A_VAL(7)1026061
BinFILTER_A_VAL_BIT_VAL_A_VAL(6)013931
BinFILTER_A_VAL_BIT_VAL_A_VAL(6)1026711
BinFILTER_A_VAL_BIT_VAL_A_VAL(5)014031
BinFILTER_A_VAL_BIT_VAL_A_VAL(5)1028731
BinFILTER_A_VAL_BIT_VAL_A_VAL(4)014051
BinFILTER_A_VAL_BIT_VAL_A_VAL(4)1028751
BinFILTER_A_VAL_BIT_VAL_A_VAL(3)013971
BinFILTER_A_VAL_BIT_VAL_A_VAL(3)1026111
BinFILTER_A_VAL_BIT_VAL_A_VAL(2)014101
BinFILTER_A_VAL_BIT_VAL_A_VAL(2)1025281
BinFILTER_A_VAL_BIT_VAL_A_VAL(1)014021
BinFILTER_A_VAL_BIT_VAL_A_VAL(1)1027441
BinFILTER_A_VAL_BIT_VAL_A_VAL(0)014221
BinFILTER_A_VAL_BIT_VAL_A_VAL(0)1026681
BinFILTER_B_MASK_BIT_MASK_B_VAL(28)01961
BinFILTER_B_MASK_BIT_MASK_B_VAL(28)1017861
BinFILTER_B_MASK_BIT_MASK_B_VAL(27)01961
BinFILTER_B_MASK_BIT_MASK_B_VAL(27)1018131
BinFILTER_B_MASK_BIT_MASK_B_VAL(26)01951
BinFILTER_B_MASK_BIT_MASK_B_VAL(26)1017761
BinFILTER_B_MASK_BIT_MASK_B_VAL(25)01961
BinFILTER_B_MASK_BIT_MASK_B_VAL(25)1017891
BinFILTER_B_MASK_BIT_MASK_B_VAL(24)011031
BinFILTER_B_MASK_BIT_MASK_B_VAL(24)1018311
BinFILTER_B_MASK_BIT_MASK_B_VAL(23)011011
BinFILTER_B_MASK_BIT_MASK_B_VAL(23)1017521
BinFILTER_B_MASK_BIT_MASK_B_VAL(22)011041
BinFILTER_B_MASK_BIT_MASK_B_VAL(22)1017911
BinFILTER_B_MASK_BIT_MASK_B_VAL(21)01901
BinFILTER_B_MASK_BIT_MASK_B_VAL(21)1017431
BinFILTER_B_MASK_BIT_MASK_B_VAL(20)01921
BinFILTER_B_MASK_BIT_MASK_B_VAL(20)1017691
BinFILTER_B_MASK_BIT_MASK_B_VAL(19)01811
BinFILTER_B_MASK_BIT_MASK_B_VAL(19)1017281
BinFILTER_B_MASK_BIT_MASK_B_VAL(18)011071
BinFILTER_B_MASK_BIT_MASK_B_VAL(18)1017661
BinFILTER_B_MASK_BIT_MASK_B_VAL(17)01161
BinFILTER_B_MASK_BIT_MASK_B_VAL(17)1016471
BinFILTER_B_MASK_BIT_MASK_B_VAL(16)01191
BinFILTER_B_MASK_BIT_MASK_B_VAL(16)1016421
BinFILTER_B_MASK_BIT_MASK_B_VAL(15)01281
BinFILTER_B_MASK_BIT_MASK_B_VAL(15)1016721
BinFILTER_B_MASK_BIT_MASK_B_VAL(14)01371
BinFILTER_B_MASK_BIT_MASK_B_VAL(14)1017671
BinFILTER_B_MASK_BIT_MASK_B_VAL(13)01351
BinFILTER_B_MASK_BIT_MASK_B_VAL(13)1017511
BinFILTER_B_MASK_BIT_MASK_B_VAL(12)01231
BinFILTER_B_MASK_BIT_MASK_B_VAL(12)1018071
BinFILTER_B_MASK_BIT_MASK_B_VAL(11)01211
BinFILTER_B_MASK_BIT_MASK_B_VAL(11)1017491
BinFILTER_B_MASK_BIT_MASK_B_VAL(10)01601
BinFILTER_B_MASK_BIT_MASK_B_VAL(10)1017421
BinFILTER_B_MASK_BIT_MASK_B_VAL(9)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(9)1017281
BinFILTER_B_MASK_BIT_MASK_B_VAL(8)01671
BinFILTER_B_MASK_BIT_MASK_B_VAL(8)1017911
BinFILTER_B_MASK_BIT_MASK_B_VAL(7)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(7)1018281
BinFILTER_B_MASK_BIT_MASK_B_VAL(6)01631
BinFILTER_B_MASK_BIT_MASK_B_VAL(6)1018751
BinFILTER_B_MASK_BIT_MASK_B_VAL(5)01621
BinFILTER_B_MASK_BIT_MASK_B_VAL(5)1017881
BinFILTER_B_MASK_BIT_MASK_B_VAL(4)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(4)1017941
BinFILTER_B_MASK_BIT_MASK_B_VAL(3)01621
BinFILTER_B_MASK_BIT_MASK_B_VAL(3)1017881
BinFILTER_B_MASK_BIT_MASK_B_VAL(2)01711
BinFILTER_B_MASK_BIT_MASK_B_VAL(2)1017671
BinFILTER_B_MASK_BIT_MASK_B_VAL(1)01671
BinFILTER_B_MASK_BIT_MASK_B_VAL(1)1018891
BinFILTER_B_MASK_BIT_MASK_B_VAL(0)01701
BinFILTER_B_MASK_BIT_MASK_B_VAL(0)1018781
BinFILTER_B_VAL_BIT_VAL_B_VAL(28)011961
BinFILTER_B_VAL_BIT_VAL_B_VAL(28)1018121
BinFILTER_B_VAL_BIT_VAL_B_VAL(27)011961
BinFILTER_B_VAL_BIT_VAL_B_VAL(27)1018121
BinFILTER_B_VAL_BIT_VAL_B_VAL(26)012171
BinFILTER_B_VAL_BIT_VAL_B_VAL(26)1018331
BinFILTER_B_VAL_BIT_VAL_B_VAL(25)011831
BinFILTER_B_VAL_BIT_VAL_B_VAL(25)1017931
BinFILTER_B_VAL_BIT_VAL_B_VAL(24)012181
BinFILTER_B_VAL_BIT_VAL_B_VAL(24)1018331
BinFILTER_B_VAL_BIT_VAL_B_VAL(23)012061
BinFILTER_B_VAL_BIT_VAL_B_VAL(23)1018071
BinFILTER_B_VAL_BIT_VAL_B_VAL(22)012001
BinFILTER_B_VAL_BIT_VAL_B_VAL(22)1018011
BinFILTER_B_VAL_BIT_VAL_B_VAL(21)012251
BinFILTER_B_VAL_BIT_VAL_B_VAL(21)1018261
BinFILTER_B_VAL_BIT_VAL_B_VAL(20)012291
BinFILTER_B_VAL_BIT_VAL_B_VAL(20)1018301
BinFILTER_B_VAL_BIT_VAL_B_VAL(19)012011
BinFILTER_B_VAL_BIT_VAL_B_VAL(19)1018021
BinFILTER_B_VAL_BIT_VAL_B_VAL(18)012091
BinFILTER_B_VAL_BIT_VAL_B_VAL(18)1018101
BinFILTER_B_VAL_BIT_VAL_B_VAL(17)01871
BinFILTER_B_VAL_BIT_VAL_B_VAL(17)1016881
BinFILTER_B_VAL_BIT_VAL_B_VAL(16)011041
BinFILTER_B_VAL_BIT_VAL_B_VAL(16)1017051
BinFILTER_B_VAL_BIT_VAL_B_VAL(15)01911
BinFILTER_B_VAL_BIT_VAL_B_VAL(15)1018561
BinFILTER_B_VAL_BIT_VAL_B_VAL(14)011061
BinFILTER_B_VAL_BIT_VAL_B_VAL(14)1018391
BinFILTER_B_VAL_BIT_VAL_B_VAL(13)011031
BinFILTER_B_VAL_BIT_VAL_B_VAL(13)1019641
BinFILTER_B_VAL_BIT_VAL_B_VAL(12)011081
BinFILTER_B_VAL_BIT_VAL_B_VAL(12)1019051
BinFILTER_B_VAL_BIT_VAL_B_VAL(11)011071
BinFILTER_B_VAL_BIT_VAL_B_VAL(11)1020001
BinFILTER_B_VAL_BIT_VAL_B_VAL(10)01931
BinFILTER_B_VAL_BIT_VAL_B_VAL(10)1017621
BinFILTER_B_VAL_BIT_VAL_B_VAL(9)011011
BinFILTER_B_VAL_BIT_VAL_B_VAL(9)1018021
BinFILTER_B_VAL_BIT_VAL_B_VAL(8)01981
BinFILTER_B_VAL_BIT_VAL_B_VAL(8)1019591
BinFILTER_B_VAL_BIT_VAL_B_VAL(7)01961
BinFILTER_B_VAL_BIT_VAL_B_VAL(7)1018611
BinFILTER_B_VAL_BIT_VAL_B_VAL(6)01861
BinFILTER_B_VAL_BIT_VAL_B_VAL(6)1018191
BinFILTER_B_VAL_BIT_VAL_B_VAL(5)011051
BinFILTER_B_VAL_BIT_VAL_B_VAL(5)1018701
BinFILTER_B_VAL_BIT_VAL_B_VAL(4)011141
BinFILTER_B_VAL_BIT_VAL_B_VAL(4)1019431
BinFILTER_B_VAL_BIT_VAL_B_VAL(3)01921
BinFILTER_B_VAL_BIT_VAL_B_VAL(3)1017931
BinFILTER_B_VAL_BIT_VAL_B_VAL(2)011151
BinFILTER_B_VAL_BIT_VAL_B_VAL(2)1018481
BinFILTER_B_VAL_BIT_VAL_B_VAL(1)01931
BinFILTER_B_VAL_BIT_VAL_B_VAL(1)1018901
BinFILTER_B_VAL_BIT_VAL_B_VAL(0)011081
BinFILTER_B_VAL_BIT_VAL_B_VAL(0)1019691
BinFILTER_C_MASK_BIT_MASK_C_VAL(28)01851
BinFILTER_C_MASK_BIT_MASK_C_VAL(28)1017341
BinFILTER_C_MASK_BIT_MASK_C_VAL(27)01951
BinFILTER_C_MASK_BIT_MASK_C_VAL(27)1017561
BinFILTER_C_MASK_BIT_MASK_C_VAL(26)01891
BinFILTER_C_MASK_BIT_MASK_C_VAL(26)1017921
BinFILTER_C_MASK_BIT_MASK_C_VAL(25)01821
BinFILTER_C_MASK_BIT_MASK_C_VAL(25)1017431
BinFILTER_C_MASK_BIT_MASK_C_VAL(24)011081
BinFILTER_C_MASK_BIT_MASK_C_VAL(24)1018031
BinFILTER_C_MASK_BIT_MASK_C_VAL(23)01791
BinFILTER_C_MASK_BIT_MASK_C_VAL(23)1017191
BinFILTER_C_MASK_BIT_MASK_C_VAL(22)011011
BinFILTER_C_MASK_BIT_MASK_C_VAL(22)1017691
BinFILTER_C_MASK_BIT_MASK_C_VAL(21)011051
BinFILTER_C_MASK_BIT_MASK_C_VAL(21)1017971
BinFILTER_C_MASK_BIT_MASK_C_VAL(20)01921
BinFILTER_C_MASK_BIT_MASK_C_VAL(20)1017761
BinFILTER_C_MASK_BIT_MASK_C_VAL(19)01851
BinFILTER_C_MASK_BIT_MASK_C_VAL(19)1017431
BinFILTER_C_MASK_BIT_MASK_C_VAL(18)01991
BinFILTER_C_MASK_BIT_MASK_C_VAL(18)1017511
BinFILTER_C_MASK_BIT_MASK_C_VAL(17)01191
BinFILTER_C_MASK_BIT_MASK_C_VAL(17)1016411
BinFILTER_C_MASK_BIT_MASK_C_VAL(16)01201
BinFILTER_C_MASK_BIT_MASK_C_VAL(16)1016361
BinFILTER_C_MASK_BIT_MASK_C_VAL(15)01341
BinFILTER_C_MASK_BIT_MASK_C_VAL(15)1016771
BinFILTER_C_MASK_BIT_MASK_C_VAL(14)01271
BinFILTER_C_MASK_BIT_MASK_C_VAL(14)1017001
BinFILTER_C_MASK_BIT_MASK_C_VAL(13)01281
BinFILTER_C_MASK_BIT_MASK_C_VAL(13)1016711
BinFILTER_C_MASK_BIT_MASK_C_VAL(12)01221
BinFILTER_C_MASK_BIT_MASK_C_VAL(12)1018211
BinFILTER_C_MASK_BIT_MASK_C_VAL(11)01141
BinFILTER_C_MASK_BIT_MASK_C_VAL(11)1017451
BinFILTER_C_MASK_BIT_MASK_C_VAL(10)01671
BinFILTER_C_MASK_BIT_MASK_C_VAL(10)1017141
BinFILTER_C_MASK_BIT_MASK_C_VAL(9)01671
BinFILTER_C_MASK_BIT_MASK_C_VAL(9)1018181
BinFILTER_C_MASK_BIT_MASK_C_VAL(8)01681
BinFILTER_C_MASK_BIT_MASK_C_VAL(8)1017211
BinFILTER_C_MASK_BIT_MASK_C_VAL(7)01621
BinFILTER_C_MASK_BIT_MASK_C_VAL(7)1017871
BinFILTER_C_MASK_BIT_MASK_C_VAL(6)01631
BinFILTER_C_MASK_BIT_MASK_C_VAL(6)1018721
BinFILTER_C_MASK_BIT_MASK_C_VAL(5)01631
BinFILTER_C_MASK_BIT_MASK_C_VAL(5)1018601
BinFILTER_C_MASK_BIT_MASK_C_VAL(4)01661
BinFILTER_C_MASK_BIT_MASK_C_VAL(4)1017911
BinFILTER_C_MASK_BIT_MASK_C_VAL(3)01681
BinFILTER_C_MASK_BIT_MASK_C_VAL(3)1018611
BinFILTER_C_MASK_BIT_MASK_C_VAL(2)01601
BinFILTER_C_MASK_BIT_MASK_C_VAL(2)1017831
BinFILTER_C_MASK_BIT_MASK_C_VAL(1)01771
BinFILTER_C_MASK_BIT_MASK_C_VAL(1)1018321
BinFILTER_C_MASK_BIT_MASK_C_VAL(0)01671
BinFILTER_C_MASK_BIT_MASK_C_VAL(0)1017861
BinFILTER_C_VAL_BIT_VAL_C_VAL(28)011841
BinFILTER_C_VAL_BIT_VAL_C_VAL(28)1018001
BinFILTER_C_VAL_BIT_VAL_C_VAL(27)011881
BinFILTER_C_VAL_BIT_VAL_C_VAL(27)1018021
BinFILTER_C_VAL_BIT_VAL_C_VAL(26)012011
BinFILTER_C_VAL_BIT_VAL_C_VAL(26)1018231
BinFILTER_C_VAL_BIT_VAL_C_VAL(25)011961
BinFILTER_C_VAL_BIT_VAL_C_VAL(25)1018101
BinFILTER_C_VAL_BIT_VAL_C_VAL(24)011931
BinFILTER_C_VAL_BIT_VAL_C_VAL(24)1018071
BinFILTER_C_VAL_BIT_VAL_C_VAL(23)011981
BinFILTER_C_VAL_BIT_VAL_C_VAL(23)1018031
BinFILTER_C_VAL_BIT_VAL_C_VAL(22)011901
BinFILTER_C_VAL_BIT_VAL_C_VAL(22)1017931
BinFILTER_C_VAL_BIT_VAL_C_VAL(21)012041
BinFILTER_C_VAL_BIT_VAL_C_VAL(21)1018071
BinFILTER_C_VAL_BIT_VAL_C_VAL(20)012251
BinFILTER_C_VAL_BIT_VAL_C_VAL(20)1018281
BinFILTER_C_VAL_BIT_VAL_C_VAL(19)012011
BinFILTER_C_VAL_BIT_VAL_C_VAL(19)1018061
BinFILTER_C_VAL_BIT_VAL_C_VAL(18)012061
BinFILTER_C_VAL_BIT_VAL_C_VAL(18)1018111
BinFILTER_C_VAL_BIT_VAL_C_VAL(17)01941
BinFILTER_C_VAL_BIT_VAL_C_VAL(17)1016971
BinFILTER_C_VAL_BIT_VAL_C_VAL(16)01971
BinFILTER_C_VAL_BIT_VAL_C_VAL(16)1017001
BinFILTER_C_VAL_BIT_VAL_C_VAL(15)011041
BinFILTER_C_VAL_BIT_VAL_C_VAL(15)1018381
BinFILTER_C_VAL_BIT_VAL_C_VAL(14)01931
BinFILTER_C_VAL_BIT_VAL_C_VAL(14)1018911
BinFILTER_C_VAL_BIT_VAL_C_VAL(13)011081
BinFILTER_C_VAL_BIT_VAL_C_VAL(13)1019701
BinFILTER_C_VAL_BIT_VAL_C_VAL(12)01981
BinFILTER_C_VAL_BIT_VAL_C_VAL(12)1018321
BinFILTER_C_VAL_BIT_VAL_C_VAL(11)011071
BinFILTER_C_VAL_BIT_VAL_C_VAL(11)1019371
BinFILTER_C_VAL_BIT_VAL_C_VAL(10)011041
BinFILTER_C_VAL_BIT_VAL_C_VAL(10)1018061
BinFILTER_C_VAL_BIT_VAL_C_VAL(9)011131
BinFILTER_C_VAL_BIT_VAL_C_VAL(9)1018791
BinFILTER_C_VAL_BIT_VAL_C_VAL(8)01961
BinFILTER_C_VAL_BIT_VAL_C_VAL(8)1018301
BinFILTER_C_VAL_BIT_VAL_C_VAL(7)01911
BinFILTER_C_VAL_BIT_VAL_C_VAL(7)1017611
BinFILTER_C_VAL_BIT_VAL_C_VAL(6)01901
BinFILTER_C_VAL_BIT_VAL_C_VAL(6)1019201
BinFILTER_C_VAL_BIT_VAL_C_VAL(5)01991
BinFILTER_C_VAL_BIT_VAL_C_VAL(5)1018971
BinFILTER_C_VAL_BIT_VAL_C_VAL(4)011001
BinFILTER_C_VAL_BIT_VAL_C_VAL(4)1018661
BinFILTER_C_VAL_BIT_VAL_C_VAL(3)01891
BinFILTER_C_VAL_BIT_VAL_C_VAL(3)1018231
BinFILTER_C_VAL_BIT_VAL_C_VAL(2)011071
BinFILTER_C_VAL_BIT_VAL_C_VAL(2)1018731
BinFILTER_C_VAL_BIT_VAL_C_VAL(1)011101
BinFILTER_C_VAL_BIT_VAL_C_VAL(1)1020041
BinFILTER_C_VAL_BIT_VAL_C_VAL(0)011101
BinFILTER_C_VAL_BIT_VAL_C_VAL(0)1018761
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)0121
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)1016031
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)0121
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)1016031
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)1016021
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)1016041
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)0111
BinFILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)0121
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)1016031
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)0121
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)1016031
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)0121
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)1016031
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)1016021
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)1016041
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)0111
BinFILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)1016041
BinFILTER_CONTROL_FANB0120521
BinFILTER_CONTROL_FANB104511
BinFILTER_CONTROL_FANE0120291
BinFILTER_CONTROL_FANE104281
BinFILTER_CONTROL_FAFB0120601
BinFILTER_CONTROL_FAFB104591
BinFILTER_CONTROL_FAFE0120291
BinFILTER_CONTROL_FAFE104281
BinFILTER_CONTROL_FBNB011061
BinFILTER_CONTROL_FBNB1017071
BinFILTER_CONTROL_FBNE011051
BinFILTER_CONTROL_FBNE1017061
BinFILTER_CONTROL_FBFB011071
BinFILTER_CONTROL_FBFB1017081
BinFILTER_CONTROL_FBFE011051
BinFILTER_CONTROL_FBFE1017061
BinFILTER_CONTROL_FCNB011061
BinFILTER_CONTROL_FCNB1017071
BinFILTER_CONTROL_FCNE011051
BinFILTER_CONTROL_FCNE1017061
BinFILTER_CONTROL_FCFB011071
BinFILTER_CONTROL_FCFB1017081
BinFILTER_CONTROL_FCFE011051
BinFILTER_CONTROL_FCFE1017061
BinFILTER_CONTROL_FRNB0161
BinFILTER_CONTROL_FRNB1016071
BinFILTER_CONTROL_FRNE0151
BinFILTER_CONTROL_FRNE1016061
BinFILTER_CONTROL_FRFB0161
BinFILTER_CONTROL_FRFB1016071
BinFILTER_CONTROL_FRFE0151
BinFILTER_CONTROL_FRFE1016061
BinRX_SETTINGS_RTSOP0151
BinRX_SETTINGS_RTSOP1016061
BinRX_DATA_READ01510131
BinRX_DATA_READ10526141
BinTX_COMMAND_TXCE013541
BinTX_COMMAND_TXCE10252911
BinTX_COMMAND_TXCR01216021
BinTX_COMMAND_TXCR10252911
BinTX_COMMAND_TXCA0117341
BinTX_COMMAND_TXCA10252911
BinTX_COMMAND_TXB10165541
BinTX_COMMAND_TXB11081511
BinTX_COMMAND_TXB20155851
BinTX_COMMAND_TXB21071861
BinTX_COMMAND_TXB3013191
BinTX_COMMAND_TXB31019201
BinTX_COMMAND_TXB4013481
BinTX_COMMAND_TXB41019491
BinTX_COMMAND_TXB501841
BinTX_COMMAND_TXB51016851
BinTX_COMMAND_TXB601641
BinTX_COMMAND_TXB61016651
BinTX_COMMAND_TXB701761
BinTX_COMMAND_TXB71016771
BinTX_COMMAND_TXB801681
BinTX_COMMAND_TXB81016691
BinTX_PRIORITY_TXT1P(2)011111
BinTX_PRIORITY_TXT1P(2)1017121
BinTX_PRIORITY_TXT1P(1)011131
BinTX_PRIORITY_TXT1P(1)1017141
BinTX_PRIORITY_TXT1P(0)0117211
BinTX_PRIORITY_TXT1P(0)101201
BinTX_PRIORITY_TXT2P(2)01931
BinTX_PRIORITY_TXT2P(2)1016941
BinTX_PRIORITY_TXT2P(1)011211
BinTX_PRIORITY_TXT2P(1)1017221
BinTX_PRIORITY_TXT2P(0)011191
BinTX_PRIORITY_TXT2P(0)1017201
BinTX_PRIORITY_TXT3P(2)01841
BinTX_PRIORITY_TXT3P(2)1016851
BinTX_PRIORITY_TXT3P(1)01921
BinTX_PRIORITY_TXT3P(1)1016931
BinTX_PRIORITY_TXT3P(0)011021
BinTX_PRIORITY_TXT3P(0)1017031
BinTX_PRIORITY_TXT4P(2)01851
BinTX_PRIORITY_TXT4P(2)1016861
BinTX_PRIORITY_TXT4P(1)011001
BinTX_PRIORITY_TXT4P(1)1017011
BinTX_PRIORITY_TXT4P(0)01871
BinTX_PRIORITY_TXT4P(0)1016881
BinTX_PRIORITY_TXT5P(2)01271
BinTX_PRIORITY_TXT5P(2)1016281
BinTX_PRIORITY_TXT5P(1)01291
BinTX_PRIORITY_TXT5P(1)1016301
BinTX_PRIORITY_TXT5P(0)01221
BinTX_PRIORITY_TXT5P(0)1016231
BinTX_PRIORITY_TXT6P(2)01171
BinTX_PRIORITY_TXT6P(2)1016181
BinTX_PRIORITY_TXT6P(1)01191
BinTX_PRIORITY_TXT6P(1)1016201
BinTX_PRIORITY_TXT6P(0)01231
BinTX_PRIORITY_TXT6P(0)1016241
BinTX_PRIORITY_TXT7P(2)01231
BinTX_PRIORITY_TXT7P(2)1016241
BinTX_PRIORITY_TXT7P(1)01221
BinTX_PRIORITY_TXT7P(1)1016231
BinTX_PRIORITY_TXT7P(0)01301
BinTX_PRIORITY_TXT7P(0)1016311
BinTX_PRIORITY_TXT8P(2)01251
BinTX_PRIORITY_TXT8P(2)1016261
BinTX_PRIORITY_TXT8P(1)01251
BinTX_PRIORITY_TXT8P(1)1016261
BinTX_PRIORITY_TXT8P(0)01201
BinTX_PRIORITY_TXT8P(0)1016211
BinSSP_CFG_SSP_OFFSET(7)01251
BinSSP_CFG_SSP_OFFSET(7)1016261
BinSSP_CFG_SSP_OFFSET(6)01271
BinSSP_CFG_SSP_OFFSET(6)1016281
BinSSP_CFG_SSP_OFFSET(5)01461
BinSSP_CFG_SSP_OFFSET(5)1016471
BinSSP_CFG_SSP_OFFSET(4)01531
BinSSP_CFG_SSP_OFFSET(4)1016541
BinSSP_CFG_SSP_OFFSET(3)0143031
BinSSP_CFG_SSP_OFFSET(3)1027141
BinSSP_CFG_SSP_OFFSET(2)015271
BinSSP_CFG_SSP_OFFSET(2)1021281
BinSSP_CFG_SSP_OFFSET(1)0129001
BinSSP_CFG_SSP_OFFSET(1)1013111
BinSSP_CFG_SSP_OFFSET(0)0123971
BinSSP_CFG_SSP_OFFSET(0)1039981
BinSSP_CFG_SSP_SRC(1)01451
BinSSP_CFG_SSP_SRC(1)1016461
BinSSP_CFG_SSP_SRC(0)018141
BinSSP_CFG_SSP_SRC(0)1024031

Signal:

 WRITE_EN
ElementFromToCountThreshold
Bin(3)011264111
Bin(3)101871061
Bin(2)011264311
Bin(2)101870861
Bin(1)011478351
Bin(1)101656821
Bin(0)011478351
Bin(0)101656821

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 122:

 write = '1' and cs = '1' 
 <---LHS--->     <-RHS--> 

LHSRHSCountThreshold
BinFalseTrue391701861
BinTrueFalse10970811
BinTrueTrue1559581

"=" expression on line 122:

 write = '1' 
Evaluated toCountThreshold
BinFalse937999771
BinTrue12530391

"=" expression on line 122:

 cs = '1' 
Evaluated toCountThreshold
BinFalse557268721
BinTrue393261441

"=" expression on line 3339:

 rst_n = '0' 
Evaluated toCountThreshold
BinFalse619289151
BinTrue179461

"and" expression on line 3342:

 cs = '1' and read = '1' 
 <-LHS-->     <--RHS---> 

LHSRHSCountThreshold
BinFalseTrue8497511
BinTrueFalse1559581
BinTrueTrue195070381

"=" expression on line 3342:

 cs = '1' 
Evaluated toCountThreshold
BinFalse112960251
BinTrue196629961

"=" expression on line 3342:

 read = '1' 
Evaluated toCountThreshold
BinFalse106022321
BinTrue203567891

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 3364 to 3365:

3364:    -- psl device_id_read_access_cov : cover 
3365:    -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 15
Threshold: 1

PSL cover point on lines 3367 to 3368:

3367:    -- psl version_read_access_cov : cover 
3368:    -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 15
Threshold: 1

PSL cover point on lines 3370 to 3371:

3370:    -- psl mode_write_access_cov : cover 
3371:    -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 31276
Threshold: 1

PSL cover point on lines 3373 to 3374:

3373:    -- psl mode_read_access_cov : cover 
3374:    -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 33511
Threshold: 1

PSL cover point on lines 3376 to 3377:

3376:    -- psl settings_write_access_cov : cover 
3377:    -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 34200
Threshold: 1

PSL cover point on lines 3379 to 3380:

3379:    -- psl settings_read_access_cov : cover 
3380:    -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 38870
Threshold: 1

PSL cover point on lines 3382 to 3383:

3382:    -- psl status_read_access_cov : cover 
3383:    -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 9047813
Threshold: 1

PSL cover point on lines 3385 to 3386:

3385:    -- psl command_write_access_cov : cover 
3386:    -- {((cs='1') and (write='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 1463
Threshold: 1

PSL cover point on lines 3388 to 3389:

3388:    -- psl int_stat_write_access_cov : cover 
3389:    -- {((cs='1') and (write='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 147
Threshold: 1

PSL cover point on lines 3391 to 3392:

3391:    -- psl int_stat_read_access_cov : cover 
3392:    -- {((cs='1') and (read='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 2007
Threshold: 1

PSL cover point on lines 3394 to 3395:

3394:    -- psl int_ena_set_write_access_cov : cover 
3395:    -- {((cs='1') and (write='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 542
Threshold: 1

PSL cover point on lines 3397 to 3398:

3397:    -- psl int_ena_set_read_access_cov : cover 
3398:    -- {((cs='1') and (read='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 90
Threshold: 1

PSL cover point on lines 3400 to 3401:

3400:    -- psl int_ena_clr_write_access_cov : cover 
3401:    -- {((cs='1') and (write='1') and (reg_sel(6)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 542
Threshold: 1

PSL cover point on lines 3403 to 3404:

3403:    -- psl int_mask_set_write_access_cov : cover 
3404:    -- {((cs='1') and (write='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 475
Threshold: 1

PSL cover point on lines 3406 to 3407:

3406:    -- psl int_mask_set_read_access_cov : cover 
3407:    -- {((cs='1') and (read='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 90
Threshold: 1

PSL cover point on lines 3409 to 3410:

3409:    -- psl int_mask_clr_write_access_cov : cover 
3410:    -- {((cs='1') and (write='1') and (reg_sel(8)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 475
Threshold: 1

PSL cover point on lines 3412 to 3413:

3412:    -- psl btr_write_access_cov : cover 
3413:    -- {((cs='1') and (write='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 6312
Threshold: 1

PSL cover point on lines 3415 to 3416:

3415:    -- psl btr_read_access_cov : cover 
3416:    -- {((cs='1') and (read='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 309
Threshold: 1

PSL cover point on lines 3418 to 3419:

3418:    -- psl btr_fd_write_access_cov : cover 
3419:    -- {((cs='1') and (write='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 6372
Threshold: 1

PSL cover point on lines 3421 to 3422:

3421:    -- psl btr_fd_read_access_cov : cover 
3422:    -- {((cs='1') and (read='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 339
Threshold: 1

PSL cover point on lines 3424 to 3425:

3424:    -- psl ewl_write_access_cov : cover 
3425:    -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(0)='1')))}; 

Count: 210
Threshold: 1

PSL cover point on lines 3427 to 3428:

3427:    -- psl ewl_read_access_cov : cover 
3428:    -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(0)='1')))}; 

Count: 13851
Threshold: 1

PSL cover point on lines 3430 to 3431:

3430:    -- psl erp_write_access_cov : cover 
3431:    -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(1)='1')))}; 

Count: 210
Threshold: 1

PSL cover point on lines 3433 to 3434:

3433:    -- psl erp_read_access_cov : cover 
3434:    -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(1)='1')))}; 

Count: 13851
Threshold: 1

PSL cover point on lines 3436 to 3437:

3436:    -- psl fault_state_read_access_cov : cover 
3437:    -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 111484
Threshold: 1

PSL cover point on lines 3439 to 3440:

3439:    -- psl rec_read_access_cov : cover 
3440:    -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 13095
Threshold: 1

PSL cover point on lines 3442 to 3443:

3442:    -- psl tec_read_access_cov : cover 
3443:    -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 13095
Threshold: 1

PSL cover point on lines 3445 to 3446:

3445:    -- psl err_norm_read_access_cov : cover 
3446:    -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 1221
Threshold: 1

PSL cover point on lines 3448 to 3449:

3448:    -- psl err_fd_read_access_cov : cover 
3449:    -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 1221
Threshold: 1

PSL cover point on lines 3451 to 3452:

3451:    -- psl ctr_pres_write_access_cov : cover 
3452:    -- {((cs='1') and (write='1') and (reg_sel(14)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 44143
Threshold: 1

PSL cover point on lines 3454 to 3455:

3454:    -- psl filter_a_mask_write_access_cov : cover 
3455:    -- {((cs='1') and (write='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 4064
Threshold: 1

PSL cover point on lines 3457 to 3458:

3457:    -- psl filter_a_mask_read_access_cov : cover 
3458:    -- {((cs='1') and (read='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 18
Threshold: 1

PSL cover point on lines 3460 to 3461:

3460:    -- psl filter_a_val_write_access_cov : cover 
3461:    -- {((cs='1') and (write='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 4064
Threshold: 1

PSL cover point on lines 3463 to 3464:

3463:    -- psl filter_a_val_read_access_cov : cover 
3464:    -- {((cs='1') and (read='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 18
Threshold: 1

PSL cover point on lines 3466 to 3467:

3466:    -- psl filter_b_mask_write_access_cov : cover 
3467:    -- {((cs='1') and (write='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 2823
Threshold: 1

PSL cover point on lines 3469 to 3470:

3469:    -- psl filter_b_mask_read_access_cov : cover 
3470:    -- {((cs='1') and (read='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12
Threshold: 1

PSL cover point on lines 3472 to 3473:

3472:    -- psl filter_b_val_write_access_cov : cover 
3473:    -- {((cs='1') and (write='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 2823
Threshold: 1

PSL cover point on lines 3475 to 3476:

3475:    -- psl filter_b_val_read_access_cov : cover 
3476:    -- {((cs='1') and (read='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12
Threshold: 1

PSL cover point on lines 3478 to 3479:

3478:    -- psl filter_c_mask_write_access_cov : cover 
3479:    -- {((cs='1') and (write='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 2823
Threshold: 1

PSL cover point on lines 3481 to 3482:

3481:    -- psl filter_c_mask_read_access_cov : cover 
3482:    -- {((cs='1') and (read='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12
Threshold: 1

PSL cover point on lines 3484 to 3485:

3484:    -- psl filter_c_val_write_access_cov : cover 
3485:    -- {((cs='1') and (write='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 2823
Threshold: 1

PSL cover point on lines 3487 to 3488:

3487:    -- psl filter_c_val_read_access_cov : cover 
3488:    -- {((cs='1') and (read='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12
Threshold: 1

PSL cover point on lines 3490 to 3491:

3490:    -- psl filter_ran_low_write_access_cov : cover 
3491:    -- {((cs='1') and (write='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 58
Threshold: 1

PSL cover point on lines 3493 to 3494:

3493:    -- psl filter_ran_low_read_access_cov : cover 
3494:    -- {((cs='1') and (read='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12
Threshold: 1

PSL cover point on lines 3496 to 3497:

3496:    -- psl filter_ran_high_write_access_cov : cover 
3497:    -- {((cs='1') and (write='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 58
Threshold: 1

PSL cover point on lines 3499 to 3500:

3499:    -- psl filter_ran_high_read_access_cov : cover 
3500:    -- {((cs='1') and (read='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12
Threshold: 1

PSL cover point on lines 3502 to 3503:

3502:    -- psl filter_control_write_access_cov : cover 
3503:    -- {((cs='1') and (write='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 9764
Threshold: 1

PSL cover point on lines 3505 to 3506:

3505:    -- psl filter_control_read_access_cov : cover 
3506:    -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 9774
Threshold: 1

PSL cover point on lines 3508 to 3509:

3508:    -- psl filter_status_read_access_cov : cover 
3509:    -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 10284
Threshold: 1

PSL cover point on lines 3511 to 3512:

3511:    -- psl rx_mem_info_read_access_cov : cover 
3512:    -- {((cs='1') and (read='1') and (reg_sel(24)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12418
Threshold: 1

PSL cover point on lines 3514 to 3515:

3514:    -- psl rx_pointers_read_access_cov : cover 
3515:    -- {((cs='1') and (read='1') and (reg_sel(25)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 12418
Threshold: 1

PSL cover point on lines 3517 to 3518:

3517:    -- psl rx_status_read_access_cov : cover 
3518:    -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 13183
Threshold: 1

PSL cover point on lines 3520 to 3521:

3520:    -- psl rx_settings_write_access_cov : cover 
3521:    -- {((cs='1') and (write='1') and (reg_sel(26)='1') and ((be(2)='1')))}; 

Count: 20
Threshold: 1

PSL cover point on lines 3523 to 3524:

3523:    -- psl rx_settings_read_access_cov : cover 
3524:    -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(2)='1')))}; 

Count: 13193
Threshold: 1

PSL cover point on lines 3526 to 3527:

3526:    -- psl rx_data_read_access_cov : cover 
3527:    -- {((cs='1') and (read='1') and (reg_sel(27)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 51013
Threshold: 1

PSL cover point on lines 3529 to 3530:

3529:    -- psl tx_status_read_access_cov : cover 
3530:    -- {((cs='1') and (read='1') and (reg_sel(28)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 8204
Threshold: 1

PSL cover point on lines 3532 to 3533:

3532:    -- psl tx_command_write_access_cov : cover 
3533:    -- {((cs='1') and (write='1') and (reg_sel(29)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 23690
Threshold: 1

PSL cover point on lines 3535 to 3536:

3535:    -- psl txtb_info_read_access_cov : cover 
3536:    -- {((cs='1') and (read='1') and (reg_sel(29)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 4512
Threshold: 1

PSL cover point on lines 3538 to 3539:

3538:    -- psl tx_priority_write_access_cov : cover 
3539:    -- {((cs='1') and (write='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 2028
Threshold: 1

PSL cover point on lines 3541 to 3542:

3541:    -- psl tx_priority_read_access_cov : cover 
3542:    -- {((cs='1') and (read='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 2038
Threshold: 1

PSL cover point on lines 3544 to 3545:

3544:    -- psl err_capt_read_access_cov : cover 
3545:    -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(0)='1')))}; 

Count: 230
Threshold: 1

PSL cover point on lines 3547 to 3548:

3547:    -- psl retr_ctr_read_access_cov : cover 
3548:    -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(1)='1')))}; 

Count: 90
Threshold: 1

PSL cover point on lines 3550 to 3551:

3550:    -- psl alc_read_access_cov : cover 
3551:    -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(2)='1')))}; 

Count: 207
Threshold: 1

PSL cover point on lines 3553 to 3554:

3553:    -- psl ts_info_read_access_cov : cover 
3554:    -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(3)='1')))}; 

Count: 10
Threshold: 1

PSL cover point on lines 3556 to 3557:

3556:    -- psl trv_delay_read_access_cov : cover 
3557:    -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(0)='1') or (be(1)='1')))}; 

Count: 40
Threshold: 1

PSL cover point on lines 3559 to 3560:

3559:    -- psl ssp_cfg_write_access_cov : cover 
3560:    -- {((cs='1') and (write='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 3384
Threshold: 1

PSL cover point on lines 3562 to 3563:

3562:    -- psl ssp_cfg_read_access_cov : cover 
3563:    -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))}; 

Count: 65
Threshold: 1

PSL cover point on lines 3565 to 3566:

3565:    -- psl rx_fr_ctr_read_access_cov : cover 
3566:    -- {((cs='1') and (read='1') and (reg_sel(33)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 1122
Threshold: 1

PSL cover point on lines 3568 to 3569:

3568:    -- psl tx_fr_ctr_read_access_cov : cover 
3569:    -- {((cs='1') and (read='1') and (reg_sel(34)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 1122
Threshold: 1

PSL cover point on lines 3571 to 3572:

3571:    -- psl debug_register_read_access_cov : cover 
3572:    -- {((cs='1') and (read='1') and (reg_sel(35)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 10164430
Threshold: 1

PSL cover point on lines 3574 to 3575:

3574:    -- psl yolo_reg_read_access_cov : cover 
3575:    -- {((cs='1') and (read='1') and (reg_sel(36)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 45
Threshold: 1

PSL cover point on lines 3577 to 3578:

3577:    -- psl timestamp_low_read_access_cov : cover 
3578:    -- {((cs='1') and (read='1') and (reg_sel(37)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 3935
Threshold: 1

PSL cover point on lines 3580 to 3581:

3580:    -- psl timestamp_high_read_access_cov : cover 
3581:    -- {((cs='1') and (read='1') and (reg_sel(38)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 

Count: 3935
Threshold: 1