NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_ERR_DETECTOR

File:  /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_ERR_DETECTOR 100.0 % (78/78) 100.0 % (72/72) 100.0 % (388/388) 100.0 % (123/123) N.A. 100.0 % (13/13) 100.0 % (674/674)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 259:

253:    err_frm_req_i <= '1' when (bit_err = '1') else 
254:                     '1' when (stuff_err = '1') else 
...
258:                     '1' when (tran_frame_parity_error = '1') else 
259:                     '0'; 
Count: 259052
Threshold: 1

Signal assignment statement on line 253:

253:    err_frm_req_i <= '1' when (bit_err = '1') else 
Count: 10230
Threshold: 1

Signal assignment statement on line 254:

254:                     '1' when (stuff_err = '1') else 
Count: 15693
Threshold: 1

Signal assignment statement on line 255:

255:                     '1' when (form_err = '1' or ack_err = '1') else 
Count: 97413
Threshold: 1

Signal assignment statement on line 256:

256:                     '1' when (crc_err = '1') else 
Count: 863
Threshold: 1

Signal assignment statement on line 257:

257:                     '1' when (bit_err_arb = '1') else 
Count: 1547
Threshold: 1

Signal assignment statement on line 258:

258:                     '1' when (tran_frame_parity_error = '1') else 
Count: 699
Threshold: 1

Signal assignment statement on line 259:

259:                     '0'; 
Count: 132607
Threshold: 1

If statement on lines 262 to 264:

262:    form_err_i <= '1' when (form_err = '1') else 
263:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
264:                  '0'; 
Count: 251333
Threshold: 1

Signal assignment statement on line 262:

262:    form_err_i <= '1' when (form_err = '1') else 
Count: 89135
Threshold: 1

Signal assignment statement on line 263:

263:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Count: 409
Threshold: 1

Signal assignment statement on line 264:

264:                  '0'; 
Count: 161789
Threshold: 1

If statement on lines 268 to 272:

268:        if (rst_n = '0') then 
269:            err_frm_req <= '0'; 
270:        elsif (rising_edge(clk_sys)) then 
271:            err_frm_req <= err_frm_req_i; 
272:        end if; 
Count: 1096781321
Threshold: 1

Signal assignment statement on line 269:

269:            err_frm_req <= '0'; 
Count: 2422674
Threshold: 1

Signal assignment statement on line 271:

271:            err_frm_req <= err_frm_req_i; 
Count: 547174334
Threshold: 1

Sequential statement on lines 278 to 286:

278:    with dst_ctr select dst_ctr_grey <= 
279:        "001" when "001", 
...
285:        "100" when "111", 
286:        "000" when others; 
Count: 999446
Threshold: 1

Signal assignment statement on line 279:

279:        "001" when "001", 
Count: 148811
Threshold: 1

Signal assignment statement on line 280:

280:        "011" when "010", 
Count: 137787
Threshold: 1

Signal assignment statement on line 281:

281:        "010" when "011", 
Count: 126687
Threshold: 1

Signal assignment statement on line 282:

282:        "110" when "100", 
Count: 117167
Threshold: 1

Signal assignment statement on line 283:

283:        "111" when "101", 
Count: 110705
Threshold: 1

Signal assignment statement on line 284:

284:        "101" when "110", 
Count: 105457
Threshold: 1

Signal assignment statement on line 285:

285:        "100" when "111", 
Count: 100830
Threshold: 1

Signal assignment statement on line 286:

286:        "000" when others; 
Count: 152002
Threshold: 1

Signal assignment statement on line 288:

288:    dst_parity <= dst_ctr_grey(0) xor dst_ctr_grey(1) xor dst_ctr_grey(2); 
Count: 999446
Threshold: 1

If statement on lines 294 to 297:

294:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
295:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
296:                             else 
297:                         '0'; 
Count: 101216
Threshold: 1

Signal assignment statement on line 294:

294:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
Count: 53128
Threshold: 1

Signal assignment statement on line 297:

297:                         '0'; 
Count: 48088
Threshold: 1

Signal assignment statement on line 300:

300:    rx_crc_15 <= rx_crc(14 downto 0); 
Count: 3831168
Threshold: 1

Signal assignment statement on line 301:

301:    rx_crc_17 <= rx_crc(16 downto 0); 
Count: 4175142
Threshold: 1

Signal assignment statement on line 302:

302:    rx_crc_21 <= rx_crc(20 downto 0); 
Count: 4859041
Threshold: 1

If statement on lines 305 to 307:

305:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
306:                     else 
307:                 '0'; 
Count: 9664914
Threshold: 1

Signal assignment statement on line 305:

305:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
Count: 75140
Threshold: 1

Signal assignment statement on line 307:

307:                 '0'; 
Count: 9589774
Threshold: 1

If statement on lines 310 to 312:

310:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
311:                     else 
312:                 '0'; 
Count: 11145671
Threshold: 1

Signal assignment statement on line 310:

310:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
Count: 19392
Threshold: 1

Signal assignment statement on line 312:

312:                 '0'; 
Count: 11126279
Threshold: 1

If statement on lines 315 to 317:

315:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
316:                     else 
317:                 '0'; 
Count: 11829587
Threshold: 1

Signal assignment statement on line 315:

315:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
Count: 11943
Threshold: 1

Signal assignment statement on line 317:

317:                 '0'; 
Count: 11817644
Threshold: 1

If statement on lines 320 to 322:

320:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
321:                          else 
322:                      '0'; 
Count: 1997254
Threshold: 1

Signal assignment statement on line 320:

320:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
Count: 162920
Threshold: 1

Signal assignment statement on line 322:

322:                      '0'; 
Count: 1834334
Threshold: 1

If statement on lines 325 to 330:

325:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
326:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
327:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
328:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
329:                       else 
330:                   '1'; 
Count: 668246
Threshold: 1

Signal assignment statement on line 325:

325:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
Count: 538113
Threshold: 1

Signal assignment statement on line 330:

330:                   '1'; 
Count: 130133
Threshold: 1

If statement on lines 332 to 334:

332:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
333:                   crc_match_c when (crc_check = '1') else 
334:                   crc_match_q; 
Count: 439172
Threshold: 1

Signal assignment statement on line 332:

332:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
Count: 85610
Threshold: 1

Signal assignment statement on line 333:

333:                   crc_match_c when (crc_check = '1') else 
Count: 87205
Threshold: 1

Signal assignment statement on line 334:

334:                   crc_match_q; 
Count: 266357
Threshold: 1

If statement on lines 338 to 342:

338:        if (rst_n = '0') then 
339:            crc_match_q <= '0'; 
340:        elsif (rising_edge(clk_sys)) then 
341:            crc_match_q <= crc_match_d; 
342:        end if; 
Count: 1096781321
Threshold: 1

Signal assignment statement on line 339:

339:            crc_match_q <= '0'; 
Count: 2422674
Threshold: 1

Signal assignment statement on line 341:

341:            crc_match_q <= crc_match_d; 
Count: 547174334
Threshold: 1

If statement on lines 355 to 360:

355:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
356:                              else 
357:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
358:                                    is_transmitter = '1' and rx_data = DOMINANT) 
359:                              else 
360:                          '0'; 
Count: 3015817
Threshold: 1

Signal assignment statement on line 355:

355:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Count: 432
Threshold: 1

Signal assignment statement on line 357:

357:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
Count: 368
Threshold: 1

Signal assignment statement on line 360:

360:                          '0'; 
Count: 3015017
Threshold: 1

Signal assignment statement on line 364:

364:    err_detected <= err_frm_req_i; 
Count: 255608
Threshold: 1

If statement on lines 369 to 376:

369:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
370:                           ERC_BIT_ERR when (bit_err = '1') else 
...
375:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
376:                           err_capt_err_type_q; 
Count: 266835
Threshold: 1

Signal assignment statement on line 369:

369:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
Count: 91751
Threshold: 1

Signal assignment statement on line 370:

370:                           ERC_BIT_ERR when (bit_err = '1') else 
Count: 10775
Threshold: 1

Signal assignment statement on line 371:

371:                           ERC_BIT_ERR when (bit_err_arb = '1') else 
Count: 1805
Threshold: 1

Signal assignment statement on line 372:

372:                           ERC_CRC_ERR when (crc_err = '1') else 
Count: 1641
Threshold: 1

Signal assignment statement on line 373:

373:                           ERC_ACK_ERR when (ack_err = '1') else 
Count: 8543
Threshold: 1

Signal assignment statement on line 374:

374:                           ERC_STUF_ERR when (stuff_err = '1') else 
Count: 16448
Threshold: 1

Signal assignment statement on line 375:

375:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
Count: 744
Threshold: 1

Signal assignment statement on line 376:

376:                           err_capt_err_type_q; 
Count: 135128
Threshold: 1

If statement on lines 383 to 393:

383:        if (rst_n = '0') then 
384:            err_capt_err_type_q <= ERR_TYPE_RSTVAL; 
...
392:            end if; 
393:        end if; 
Count: 1096781321
Threshold: 1

Signal assignment statement on line 384:

384:            err_capt_err_type_q <= ERR_TYPE_RSTVAL; 
Count: 2422674
Threshold: 1

Signal assignment statement on line 385:

385:            err_capt_err_pos_q <= ERR_POS_RSTVAL; 
Count: 2422674
Threshold: 1

Signal assignment statement on line 386:

386:            err_capt_err_erp <= ERR_ERP_RSTVAL; 
Count: 2422674
Threshold: 1

If statement on lines 388 to 392:

388:            if (err_frm_req_i = '1') then 
389:                err_capt_err_type_q <= err_capt_err_type_d; 
390:                err_capt_err_pos_q <= err_pos; 
391:                err_capt_err_erp <= is_err_passive; 
392:            end if; 
Count: 547174334
Threshold: 1

Signal assignment statement on line 389:

389:                err_capt_err_type_q <= err_capt_err_type_d; 
Count: 31526
Threshold: 1

Signal assignment statement on line 390:

390:                err_capt_err_pos_q <= err_pos; 
Count: 31526
Threshold: 1

Signal assignment statement on line 391:

391:                err_capt_err_erp <= is_err_passive; 
Count: 31526
Threshold: 1

Signal assignment statement on line 397:

397:    err_capt_err_type <= err_capt_err_type_q; 
Count: 7061
Threshold: 1

Signal assignment statement on line 398:

398:    err_capt_err_pos <= err_capt_err_pos_q; 
Count: 12035
Threshold: 1

Signal assignment statement on line 399:

399:    crc_match <= crc_match_q; 
Count: 58806
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

253:    err_frm_req_i <= '1' when (bit_err = '1') else 
Evaluated toCountThreshold
BinTrue102301
BinFalse2488221

"if" / "when" / "else" condition on line 254:

254:                     '1' when (stuff_err = '1') else 
Evaluated toCountThreshold
BinTrue156931
BinFalse2331291

"if" / "when" / "else" condition on line 255:

255:                     '1' when (form_err = '1' or ack_err = '1') else 
Evaluated toCountThreshold
BinTrue974131
BinFalse1357161

"if" / "when" / "else" condition on line 256:

256:                     '1' when (crc_err = '1') else 
Evaluated toCountThreshold
BinTrue8631
BinFalse1348531

"if" / "when" / "else" condition on line 257:

257:                     '1' when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinTrue15471
BinFalse1333061

"if" / "when" / "else" condition on line 258:

258:                     '1' when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinTrue6991
BinFalse1326071

"if" / "when" / "else" condition on line 262:

262:    form_err_i <= '1' when (form_err = '1') else 
Evaluated toCountThreshold
BinTrue891351
BinFalse1621981

"if" / "when" / "else" condition on line 263:

263:                  '1' when (stuff_err = '1' and fixed_stuff = '1') else 
Evaluated toCountThreshold
BinTrue4091
BinFalse1617891

"if" / "when" / "else" condition on line 268:

268:        if (rst_n = '0') then 
Evaluated toCountThreshold
BinTrue24226741
BinFalse10943586471

"if" / "when" / "else" condition on line 270:

270:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471743341
BinFalse5471843131

"case" / "with" / "select" choice on line 279:

279:        "001" when "001", 
Choice ofCountThreshold
Bin"001"1488111

"case" / "with" / "select" choice on line 280:

280:        "011" when "010", 
Choice ofCountThreshold
Bin"010"1377871

"case" / "with" / "select" choice on line 281:

281:        "010" when "011", 
Choice ofCountThreshold
Bin"011"1266871

"case" / "with" / "select" choice on line 282:

282:        "110" when "100", 
Choice ofCountThreshold
Bin"100"1171671

"case" / "with" / "select" choice on line 283:

283:        "111" when "101", 
Choice ofCountThreshold
Bin"101"1107051

"case" / "with" / "select" choice on line 284:

284:        "101" when "110", 
Choice ofCountThreshold
Bin"110"1054571

"case" / "with" / "select" choice on line 285:

285:        "100" when "111", 
Choice ofCountThreshold
Bin"111"1008301

"case" / "with" / "select" choice on line 286:

286:        "000" when others; 
Choice ofCountThreshold
Binothers1520021

"if" / "when" / "else" condition on lines 294 to 295:

294:    stuff_count_check <= '1' when (mr_settings_nisofd = ISO_FD) and 
295:                                  (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
Evaluated toCountThreshold
BinTrue531281
BinFalse480881

"if" / "when" / "else" condition on line 305:

305:    crc_15_ok <= '1' when (rx_crc_15 = crc_15) 
Evaluated toCountThreshold
BinTrue751401
BinFalse95897741

"if" / "when" / "else" condition on line 310:

310:    crc_17_ok <= '1' when (rx_crc_17 = crc_17) 
Evaluated toCountThreshold
BinTrue193921
BinFalse111262791

"if" / "when" / "else" condition on line 315:

315:    crc_21_ok <= '1' when (rx_crc_21 = crc_21) 
Evaluated toCountThreshold
BinTrue119431
BinFalse118176441

"if" / "when" / "else" condition on line 320:

320:    stuff_count_ok <= '1' when (rx_stuff_count = dst_ctr_grey & dst_parity) 
Evaluated toCountThreshold
BinTrue1629201
BinFalse18343341

"if" / "when" / "else" condition on lines 325 to 328:

325:    crc_match_c <= '0' when (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or 
326:                            (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or 
327:                            (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or 
328:                            (stuff_count_ok = '0' and stuff_count_check = '1') 
Evaluated toCountThreshold
BinTrue5381131
BinFalse1301331

"if" / "when" / "else" condition on line 332:

332:    crc_match_d <= '0' when (crc_clear_match_flag = '1') else 
Evaluated toCountThreshold
BinTrue856101
BinFalse3535621

"if" / "when" / "else" condition on line 333:

333:                   crc_match_c when (crc_check = '1') else 
Evaluated toCountThreshold
BinTrue872051
BinFalse2663571

"if" / "when" / "else" condition on line 338:

338:        if (rst_n = '0') then 
Evaluated toCountThreshold
BinTrue24226741
BinFalse10943586471

"if" / "when" / "else" condition on line 340:

340:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471743341
BinFalse5471843131

"if" / "when" / "else" condition on line 355:

355:    err_ctrs_unchanged <= '1' when (ack_err = '1' and is_err_passive = '1') 
Evaluated toCountThreshold
BinTrue4321
BinFalse30153851

"if" / "when" / "else" condition on lines 357 to 358:

357:                          '1' when (stuff_err = '1' and is_arbitration = '1' and 
358:                                    is_transmitter = '1' and rx_data = DOMINANT) 
Evaluated toCountThreshold
BinTrue3681
BinFalse30150171

"if" / "when" / "else" condition on line 369:

369:    err_capt_err_type_d <= ERC_FRM_ERR when (form_err_i = '1') else 
Evaluated toCountThreshold
BinTrue917511
BinFalse1750841

"if" / "when" / "else" condition on line 370:

370:                           ERC_BIT_ERR when (bit_err = '1') else 
Evaluated toCountThreshold
BinTrue107751
BinFalse1643091

"if" / "when" / "else" condition on line 371:

371:                           ERC_BIT_ERR when (bit_err_arb = '1') else 
Evaluated toCountThreshold
BinTrue18051
BinFalse1625041

"if" / "when" / "else" condition on line 372:

372:                           ERC_CRC_ERR when (crc_err = '1') else 
Evaluated toCountThreshold
BinTrue16411
BinFalse1608631

"if" / "when" / "else" condition on line 373:

373:                           ERC_ACK_ERR when (ack_err = '1') else 
Evaluated toCountThreshold
BinTrue85431
BinFalse1523201

"if" / "when" / "else" condition on line 374:

374:                           ERC_STUF_ERR when (stuff_err = '1') else 
Evaluated toCountThreshold
BinTrue164481
BinFalse1358721

"if" / "when" / "else" condition on line 375:

375:                           ERC_PRT_ERR when (tran_frame_parity_error = '1') else 
Evaluated toCountThreshold
BinTrue7441
BinFalse1351281

"if" / "when" / "else" condition on line 383:

383:        if (rst_n = '0') then 
Evaluated toCountThreshold
BinTrue24226741
BinFalse10943586471

"if" / "when" / "else" condition on line 387:

387:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471743341
BinFalse5471843131

"if" / "when" / "else" condition on line 388:

388:            if (err_frm_req_i = '1') then 
Evaluated toCountThreshold
BinTrue315261
BinFalse5471428081

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RST_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 TX_DATA
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_DATA
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 BIT_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 BIT_ERR_ARB
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 STUFF_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 FORM_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 ACK_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 CRC_ERR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_CRC
ElementFromToCountThresholdExcluded due to
Bin(20)0101Exclude file
Bin(20)1001Exclude file
Bin(19)0101Exclude file
Bin(19)1001Exclude file
Bin(18)0101Exclude file
Bin(18)1001Exclude file
Bin(17)0101Exclude file
Bin(17)1001Exclude file
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_15
ElementFromToCountThresholdExcluded due to
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_17
ElementFromToCountThresholdExcluded due to
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_21
ElementFromToCountThresholdExcluded due to
Bin(20)0101Exclude file
Bin(20)1001Exclude file
Bin(19)0101Exclude file
Bin(19)1001Exclude file
Bin(18)0101Exclude file
Bin(18)1001Exclude file
Bin(17)0101Exclude file
Bin(17)1001Exclude file
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 RX_STUFF_COUNT
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 DST_CTR
ElementFromToCountThresholdExcluded due to
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 FIXED_STUFF
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 ERR_POS
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 CRC_CHECK
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 CRC_CLEAR_MATCH_FLAG
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 CRC_SRC
ElementFromToCountThresholdExcluded due to
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 IS_ARBITRATION
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 IS_TRANSMITTER
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 IS_ERR_PASSIVE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 TRAN_FRAME_PARITY_ERROR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 MR_SETTINGS_NISOFD
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Port:

 ERR_CAPT_ERR_TYPE
ElementFromToCountThreshold
Bin(2)018001
Bin(2)1023991
Bin(1)0112631
Bin(1)1028611
Bin(0)013331
Bin(0)1019331

Port:

 ERR_CAPT_ERR_POS
ElementFromToCountThreshold
Bin(3)0141881
Bin(3)1025951
Bin(2)0144271
Bin(2)1028281
Bin(1)0136271
Bin(1)1020311
Bin(0)0130491
Bin(0)1014491

Port:

 ERR_CAPT_ERR_ERP
FromToCountThreshold
Bin012951
Bin1018961

Port:

 ERR_FRM_REQ
FromToCountThreshold
Bin01315261
Bin10331271

Port:

 ERR_DETECTED
FromToCountThreshold
Bin011262031
Bin101278041

Port:

 CRC_MATCH
FromToCountThreshold
Bin01278021
Bin10294031

Port:

 ERR_CTRS_UNCHANGED
FromToCountThreshold
Bin018001
Bin1024011

Signal:

 ERR_FRM_REQ_I
FromToCountThreshold
Bin011262031
Bin101278041

Signal:

 ERR_CAPT_ERR_TYPE_D
ElementFromToCountThreshold
Bin(2)01144061
Bin(2)10160051
Bin(1)01838731
Bin(1)10854711
Bin(0)01115231
Bin(0)10131231

Signal:

 ERR_CAPT_ERR_TYPE_Q
ElementFromToCountThreshold
Bin(2)018001
Bin(2)1023991
Bin(1)0112631
Bin(1)1028611
Bin(0)013331
Bin(0)1019331

Signal:

 ERR_CAPT_ERR_POS_Q
ElementFromToCountThreshold
Bin(3)0141881
Bin(3)1025951
Bin(2)0144271
Bin(2)1028281
Bin(1)0136271
Bin(1)1020311
Bin(0)0130491
Bin(0)1014491

Signal:

 FORM_ERR_I
FromToCountThreshold
Bin01895441
Bin10911451

Signal:

 CRC_MATCH_C
FromToCountThreshold
Bin01741471
Bin10725541

Signal:

 CRC_MATCH_D
FromToCountThreshold
Bin01278271
Bin10294281

Signal:

 CRC_MATCH_Q
FromToCountThreshold
Bin01278021
Bin10294031

Signal:

 DST_CTR_GREY
ElementFromToCountThreshold
Bin(2)014341591
Bin(2)105636861
Bin(1)014923461
Bin(1)105054991
Bin(0)015027601
Bin(0)104950851

Signal:

 DST_PARITY
FromToCountThreshold
Bin014870331
Bin104886291

Signal:

 STUFF_COUNT_CHECK
FromToCountThreshold
Bin01430061
Bin10446021

Signal:

 CRC_15_OK
FromToCountThreshold
Bin01751401
Bin10735501

Signal:

 CRC_17_OK
FromToCountThreshold
Bin01193921
Bin10177991

Signal:

 CRC_21_OK
FromToCountThreshold
Bin01119431
Bin10103531

Signal:

 STUFF_COUNT_OK
FromToCountThreshold
Bin011622091
Bin101606151

Signal:

 RX_CRC_15
ElementFromToCountThreshold
Bin(14)014069741
Bin(14)104085711
Bin(13)014170881
Bin(13)104186861
Bin(12)014274261
Bin(12)104290241
Bin(11)014397391
Bin(11)104413341
Bin(10)014525211
Bin(10)104541151
Bin(9)014622271
Bin(9)104638241
Bin(8)014748221
Bin(8)104764181
Bin(7)015202771
Bin(7)105218741
Bin(6)015334351
Bin(6)105350301
Bin(5)015425981
Bin(5)105441931
Bin(4)015540731
Bin(4)105556661
Bin(3)015657901
Bin(3)105673851
Bin(2)015773331
Bin(2)105789281
Bin(1)015866881
Bin(1)105882801
Bin(0)015958531
Bin(0)105974451

Signal:

 RX_CRC_17
ElementFromToCountThreshold
Bin(16)013516171
Bin(16)103532141
Bin(15)013932201
Bin(15)103948171
Bin(14)014069741
Bin(14)104085711
Bin(13)014170881
Bin(13)104186861
Bin(12)014274261
Bin(12)104290241
Bin(11)014397391
Bin(11)104413341
Bin(10)014525211
Bin(10)104541151
Bin(9)014622271
Bin(9)104638241
Bin(8)014748221
Bin(8)104764181
Bin(7)015202771
Bin(7)105218741
Bin(6)015334351
Bin(6)105350301
Bin(5)015425981
Bin(5)105441931
Bin(4)015540731
Bin(4)105556661
Bin(3)015657901
Bin(3)105673851
Bin(2)015773331
Bin(2)105789281
Bin(1)015866881
Bin(1)105882801
Bin(0)015958531
Bin(0)105974451

Signal:

 RX_CRC_21
ElementFromToCountThreshold
Bin(20)013169161
Bin(20)103185131
Bin(19)013302771
Bin(19)103318731
Bin(18)013376041
Bin(18)103392011
Bin(17)013436251
Bin(17)103452231
Bin(16)013516171
Bin(16)103532141
Bin(15)013932201
Bin(15)103948171
Bin(14)014069741
Bin(14)104085711
Bin(13)014170881
Bin(13)104186861
Bin(12)014274261
Bin(12)104290241
Bin(11)014397391
Bin(11)104413341
Bin(10)014525211
Bin(10)104541151
Bin(9)014622271
Bin(9)104638241
Bin(8)014748221
Bin(8)104764181
Bin(7)015202771
Bin(7)105218741
Bin(6)015334351
Bin(6)105350301
Bin(5)015425981
Bin(5)105441931
Bin(4)015540731
Bin(4)105556661
Bin(3)015657901
Bin(3)105673851
Bin(2)015773331
Bin(2)105789281
Bin(1)015866881
Bin(1)105882801
Bin(0)015958531
Bin(0)105974451

Uncovered expressions:

Excluded expressions:

"and" expression on lines 294 to 295:

 (mr_settings_nisofd = ISO_FD) and (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
  <-----------LHS----------->       <--------------------RHS--------------------->  
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"or" expression on line 295:

 crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC 
 <--------LHS-------->    <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"or" expression on lines 325 to 327:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or (crc_21_ok = '0' and crc_src = C_CRC21_SRC) 
 <------------------------------------------LHS------------------------------------------->     <------------------RHS------------------>  
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"or" expression on lines 325 to 326:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) 
  <------------------LHS------------------>      <------------------RHS------------------>  
LHSRHSCountThresholdExcluded due to
BinTrueFalse01Unreachable

"and" expression on line 325:

 crc_15_ok = '0' and crc_src = C_CRC15_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"and" expression on line 326:

 crc_17_ok = '0' and crc_src = C_CRC17_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

"and" expression on line 327:

 crc_21_ok = '0' and crc_src = C_CRC21_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThresholdExcluded due to
BinFalseTrue01Unreachable

Covered expressions:

"=" expression on line 253:

 bit_err = '1' 
Evaluated toCountThreshold
BinFalse2488221
BinTrue102301

"=" expression on line 254:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse2331291
BinTrue156931

"or" expression on line 255:

 form_err = '1' or ack_err = '1' 
 <----LHS----->    <----RHS----> 
LHSRHSCountThreshold
BinFalseFalse1357161
BinFalseTrue82781
BinTrueFalse891351

"=" expression on line 255:

 form_err = '1' 
Evaluated toCountThreshold
BinFalse1439941
BinTrue891351

"=" expression on line 255:

 ack_err = '1' 
Evaluated toCountThreshold
BinFalse2248511
BinTrue82781

"=" expression on line 256:

 crc_err = '1' 
Evaluated toCountThreshold
BinFalse1348531
BinTrue8631

"=" expression on line 257:

 bit_err_arb = '1' 
Evaluated toCountThreshold
BinFalse1333061
BinTrue15471

"=" expression on line 258:

 tran_frame_parity_error = '1' 
Evaluated toCountThreshold
BinFalse1326071
BinTrue6991

"=" expression on line 262:

 form_err = '1' 
Evaluated toCountThreshold
BinFalse1621981
BinTrue891351

"and" expression on line 263:

 stuff_err = '1' and fixed_stuff = '1' 
 <-----LHS----->     <------RHS------> 
LHSRHSCountThreshold
BinFalseTrue130271
BinTrueFalse200981
BinTrueTrue4091

"=" expression on line 263:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse1416911
BinTrue205071

"=" expression on line 263:

 fixed_stuff = '1' 
Evaluated toCountThreshold
BinFalse1487621
BinTrue134361

"=" expression on line 268:

 rst_n = '0' 
Evaluated toCountThreshold
BinFalse10943586471
BinTrue24226741

"xor" expression on line 288:

 dst_ctr_grey(0) xor dst_ctr_grey(1) xor dst_ctr_grey(2) 
 <---------------LHS--------------->     <-----RHS-----> 
LHSRHSCountThreshold
Bin'0''0'2881881
Bin'0''1'2115351
Bin'1''0'2754981
Bin'1''1'2226241

"xor" expression on line 288:

 dst_ctr_grey(0) xor dst_ctr_grey(1) 
 <-----LHS----->     <-----RHS-----> 
LHSRHSCountThreshold
Bin'0''0'2512311
Bin'0''1'2438541
Bin'1''0'2542681
Bin'1''1'2484921

"and" expression on lines 294 to 295:

 (mr_settings_nisofd = ISO_FD) and (crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC) 
  <-----------LHS----------->       <--------------------RHS--------------------->  
LHSRHSCountThreshold
BinTrueFalse447321
BinTrueTrue531281

"=" expression on line 294:

 mr_settings_nisofd = ISO_FD 
Evaluated toCountThreshold
BinFalse33561
BinTrue978601

"or" expression on line 295:

 crc_src = C_CRC17_SRC or crc_src = C_CRC21_SRC 
 <--------LHS-------->    <--------RHS--------> 
LHSRHSCountThreshold
BinFalseFalse447321
BinFalseTrue248221

"or" expression on lines 325 to 328:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or (crc_21_ok = '0' and crc_src = C_CRC21_SRC) or (stuff_count_ok = '0' and stuff_count_check = '1') 
 <------------------------------------------------------------------LHS------------------------------------------------------------------>     <---------------------RHS---------------------->  
LHSRHSCountThreshold
BinFalseFalse1301331
BinFalseTrue137621
BinTrueFalse3498231

"or" expression on lines 325 to 327:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) or (crc_21_ok = '0' and crc_src = C_CRC21_SRC) 
 <------------------------------------------LHS------------------------------------------->     <------------------RHS------------------>  
LHSRHSCountThreshold
BinFalseFalse1438951
BinFalseTrue2607061

"or" expression on lines 325 to 326:

 (crc_15_ok = '0' and crc_src = C_CRC15_SRC) or (crc_17_ok = '0' and crc_src = C_CRC17_SRC) 
  <------------------LHS------------------>      <------------------RHS------------------>  
LHSRHSCountThreshold
BinFalseFalse4046011
BinFalseTrue1090351

"and" expression on line 325:

 crc_15_ok = '0' and crc_src = C_CRC15_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThreshold
BinTrueFalse3500161
BinTrueTrue1546101

"=" expression on line 325:

 crc_15_ok = '0' 
Evaluated toCountThreshold
BinFalse1636201
BinTrue5046261

"and" expression on line 326:

 crc_17_ok = '0' and crc_src = C_CRC17_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThreshold
BinTrueFalse3817611
BinTrueTrue1090351

"=" expression on line 326:

 crc_17_ok = '0' 
Evaluated toCountThreshold
BinFalse228401
BinTrue4907961

"and" expression on line 327:

 crc_21_ok = '0' and crc_src = C_CRC21_SRC 
 <-----LHS----->     <--------RHS--------> 
LHSRHSCountThreshold
BinTrueFalse1285081
BinTrueTrue2607061

"=" expression on line 327:

 crc_21_ok = '0' 
Evaluated toCountThreshold
BinFalse153871
BinTrue3892141

"and" expression on line 328:

 stuff_count_ok = '0' and stuff_count_check = '1' 
 <-------LHS-------->     <---------RHS---------> 
LHSRHSCountThreshold
BinFalseTrue1924681
BinTrueFalse1587451
BinTrueTrue1882901

"=" expression on line 328:

 stuff_count_ok = '0' 
Evaluated toCountThreshold
BinFalse3212111
BinTrue3470351

"=" expression on line 328:

 stuff_count_check = '1' 
Evaluated toCountThreshold
BinFalse2874881
BinTrue3807581

"=" expression on line 332:

 crc_clear_match_flag = '1' 
Evaluated toCountThreshold
BinFalse3535621
BinTrue856101

"=" expression on line 333:

 crc_check = '1' 
Evaluated toCountThreshold
BinFalse2663571
BinTrue872051

"=" expression on line 338:

 rst_n = '0' 
Evaluated toCountThreshold
BinFalse10943586471
BinTrue24226741

"and" expression on line 355:

 ack_err = '1' and is_err_passive = '1' 
 <----LHS---->     <-------RHS--------> 
LHSRHSCountThreshold
BinFalseTrue7398711
BinTrueFalse78461
BinTrueTrue4321

"=" expression on line 355:

 ack_err = '1' 
Evaluated toCountThreshold
BinFalse30075391
BinTrue82781

"=" expression on line 355:

 is_err_passive = '1' 
Evaluated toCountThreshold
BinFalse22755141
BinTrue7403031

"and" expression on lines 357 to 358:

 stuff_err = '1' and is_arbitration = '1' and is_transmitter = '1' and rx_data = DOMINANT 
 <------------------------------LHS------------------------------>     <------RHS-------> 
LHSRHSCountThreshold
BinFalseTrue15265141
BinTrueFalse3101
BinTrueTrue3681

"and" expression on lines 357 to 358:

 stuff_err = '1' and is_arbitration = '1' and is_transmitter = '1' 
 <-----------------LHS------------------>     <-------RHS--------> 
LHSRHSCountThreshold
BinFalseTrue13447051
BinTrueFalse24951
BinTrueTrue6781

"and" expression on line 357:

 stuff_err = '1' and is_arbitration = '1' 
 <-----LHS----->     <-------RHS--------> 
LHSRHSCountThreshold
BinFalseTrue6158331
BinTrueFalse173341
BinTrueTrue31731

"=" expression on line 357:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse29948781
BinTrue205071

"=" expression on line 357:

 is_arbitration = '1' 
Evaluated toCountThreshold
BinFalse23963791
BinTrue6190061

"=" expression on line 358:

 is_transmitter = '1' 
Evaluated toCountThreshold
BinFalse16700021
BinTrue13453831

"=" expression on line 358:

 rx_data = DOMINANT 
Evaluated toCountThreshold
BinFalse14885031
BinTrue15268821

"=" expression on line 369:

 form_err_i = '1' 
Evaluated toCountThreshold
BinFalse1750841
BinTrue917511

"=" expression on line 370:

 bit_err = '1' 
Evaluated toCountThreshold
BinFalse1643091
BinTrue107751

"=" expression on line 371:

 bit_err_arb = '1' 
Evaluated toCountThreshold
BinFalse1625041
BinTrue18051

"=" expression on line 372:

 crc_err = '1' 
Evaluated toCountThreshold
BinFalse1608631
BinTrue16411

"=" expression on line 373:

 ack_err = '1' 
Evaluated toCountThreshold
BinFalse1523201
BinTrue85431

"=" expression on line 374:

 stuff_err = '1' 
Evaluated toCountThreshold
BinFalse1358721
BinTrue164481

"=" expression on line 375:

 tran_frame_parity_error = '1' 
Evaluated toCountThreshold
BinFalse1351281
BinTrue7441

"=" expression on line 383:

 rst_n = '0' 
Evaluated toCountThreshold
BinFalse10943586471
BinTrue24226741

"=" expression on line 388:

 err_frm_req_i = '1' 
Evaluated toCountThreshold
BinFalse5471428081
BinTrue315261

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 407 to 408:

407:    -- psl err_detect_bit_err_cov : cover 
408:    --  {bit_err = '1'}; 
Count: 10109
Threshold: 1

PSL cover point on lines 410 to 411:

410:    -- psl err_detect_bit_err_arb_cov : cover 
411:    --  {bit_err_arb = '1'}; 
Count: 1547
Threshold: 1

PSL cover point on lines 413 to 414:

413:    -- psl err_detect_stuff_err_cov : cover 
414:    --  {stuff_err = '1'}; 
Count: 20507
Threshold: 1

PSL cover point on lines 416 to 417:

416:    -- psl err_detect_form_err_cov : cover 
417:    --  {form_err = '1'}; 
Count: 2755
Threshold: 1

PSL cover point on lines 419 to 420:

419:    -- psl err_detect_ack_err_cov : cover 
420:    --  {ack_err = '1'}; 
Count: 1326
Threshold: 1

PSL cover point on lines 422 to 423:

422:    -- psl err_detect_crc_err_cov : cover 
423:    --  {crc_err = '1'}; 
Count: 809
Threshold: 1

PSL cover point on lines 425 to 426:

425:    -- psl err_detect_parity_err_cov : cover 
426:    --  {tran_frame_parity_error = '1'}; 
Count: 158
Threshold: 1

PSL cover point on lines 428 to 429:

428:    -- psl err_capt_q_form_err_cov : cover 
429:    --  {err_capt_err_type_q = ERC_FRM_ERR}; 
Count: 37366037
Threshold: 1

PSL cover point on lines 431 to 432:

431:    -- psl err_capt_q_bit_err_cov : cover 
432:    --  {err_capt_err_type_q = ERC_BIT_ERR}; 
Count: 335189009
Threshold: 1

PSL cover point on lines 434 to 435:

434:    -- psl err_capt_q_crc_err_cov : cover 
435:    --  {err_capt_err_type_q = ERC_CRC_ERR}; 
Count: 748280
Threshold: 1

PSL cover point on lines 437 to 438:

437:    -- psl err_capt_q_ack_err_cov : cover 
438:    --  {err_capt_err_type_q = ERC_ACK_ERR}; 
Count: 4396253
Threshold: 1

PSL cover point on lines 440 to 441:

440:    -- psl err_capt_q_stuff_err_cov : cover 
441:    --  {err_capt_err_type_q = ERC_STUF_ERR}; 
Count: 169941504
Threshold: 1

PSL cover point on lines 443 to 444:

443:    -- psl err_capt_q_prt_err_cov : cover 
444:    --  {err_capt_err_type_q = ERC_PRT_ERR}; 
Count: 738302
Threshold: 1