NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_COUNTERS_DBT	100.0 % (23/23)	100.0 % (20/20)	100.0 % (108/108)	100.0 % (29/29)	N.A.	N.A.	100.0 % (180/180)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_COUNTERS_DBT

100.0 % (23/23)

100.0 % (20/20)

100.0 % (108/108)

100.0 % (29/29)

N.A.

100.0 % (180/180)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

155:    tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp)) 
156:                              else 
157:                          '0';

Count: 80910697
Threshold: 1

Signal assignment statement on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))
Count: 35305112
Threshold: 1

Signal assignment statement on line 157:

157: '0';
Count: 45605585
Threshold: 1

If statement on lines 165 to 168:

165:    tq_counter_d <= 
166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
167:                                   else 
168:        std_logic_vector(unsigned(tq_counter_q) + 1);

Count: 197303253
Threshold: 1

Signal assignment statement on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')
Count: 115148178
Threshold: 1

Signal assignment statement on line 168:

168: std_logic_vector(unsigned(tq_counter_q) + 1);
Count: 82155075
Threshold: 1

If statement on lines 172 to 178:

172:        if (rst_n = '0') then 
173:            tq_counter_q <= std_logic_vector(C_TQ_RST); 
...
177:            end if; 
178:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 173:

173: tq_counter_q <= std_logic_vector(C_TQ_RST);
Count: 2422674
Threshold: 1

If statement on lines 175 to 177:

175:            if (ctrs_en = '1') then 
176:                tq_counter_q <= tq_counter_d; 
177:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 176:

176: tq_counter_q <= tq_counter_d;
Count: 138844624
Threshold: 1

Signal assignment statement on line 184:

184: tq_edge_i <= tq_counter_expired;
Count: 70613415
Threshold: 1

If statement on lines 189 to 190:

189:    segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else 
190:                      std_logic_vector(unsigned(segm_counter_q) + 1);

Count: 139087503
Threshold: 1

Signal assignment statement on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else
Count: 32934111
Threshold: 1

Signal assignment statement on line 190:

190: std_logic_vector(unsigned(segm_counter_q) + 1);
Count: 106153392
Threshold: 1

If statement on lines 192 to 194:

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
193:                           else 
194:                       '0';

Count: 116538378
Threshold: 1

Signal assignment statement on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')
Count: 68238479
Threshold: 1

Signal assignment statement on line 194:

194: '0';
Count: 48299899
Threshold: 1

If statement on lines 198 to 204:

198:        if (rst_n = '0') then 
199:            segm_counter_q <= (others => '0'); 
...
203:            end if; 
204:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 199:

199: segm_counter_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 201 to 203:

201:            if (segm_counter_ce = '1') then 
202:                segm_counter_q <= segm_counter_d; 
203:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 202:

202: segm_counter_q <= segm_counter_d;
Count: 106141995
Threshold: 1

Signal assignment statement on line 210:

210: segm_counter <= segm_counter_q;
Count: 93297906
Threshold: 1

Signal assignment statement on line 211:

211: tq_edge <= tq_edge_i;
Count: 70613415
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))

	Evaluated to	Count	Threshold
Bin	True	35305112	1
Bin	False	45605585	1

"if" / "when" / "else" condition on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	True	115148178	1
Bin	False	82155075	1

"if" / "when" / "else" condition on line 172:

172: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 174:

174: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 175:

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	138844624	1
Bin	False	408329710	1

"if" / "when" / "else" condition on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	32934111	1
Bin	False	106153392	1

"if" / "when" / "else" condition on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	True	68238479	1
Bin	False	48299899	1

"if" / "when" / "else" condition on line 198:

198: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 200:

200: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 201:

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	106141995	1
Bin	False	441032339	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BRP

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TQ_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BT_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	35305112	1
Bin	1	0	35306702	1

Port:

SEGM_COUNTER

	Element	From	To	Count	Threshold
Bin	(6)	0	1	142320	1
Bin	(6)	1	0	143921	1
Bin	(5)	0	1	248387	1
Bin	(5)	1	0	249988	1
Bin	(4)	0	1	798552	1
Bin	(4)	1	0	800153	1
Bin	(3)	0	1	4518748	1
Bin	(3)	1	0	4520349	1
Bin	(2)	0	1	12010808	1
Bin	(2)	1	0	12012409	1
Bin	(1)	0	1	22910154	1
Bin	(1)	1	0	22911755	1
Bin	(0)	0	1	42613854	1
Bin	(0)	1	0	42615454	1

Signal:

TQ_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	21715	1
Bin	(7)	1	0	23316	1
Bin	(6)	0	1	43430	1
Bin	(6)	1	0	45031	1
Bin	(5)	0	1	86860	1
Bin	(5)	1	0	88461	1
Bin	(4)	0	1	173735	1
Bin	(4)	1	0	175336	1
Bin	(3)	0	1	359173	1
Bin	(3)	1	0	360774	1
Bin	(2)	0	1	5118154	1
Bin	(2)	1	0	5119755	1
Bin	(1)	0	1	37897300	1
Bin	(1)	1	0	37895710	1
Bin	(0)	0	1	43696683	1
Bin	(0)	1	0	43698273	1

Signal:

TQ_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	21715	1
Bin	(7)	1	0	23316	1
Bin	(6)	0	1	43430	1
Bin	(6)	1	0	45031	1
Bin	(5)	0	1	86860	1
Bin	(5)	1	0	88461	1
Bin	(4)	0	1	173735	1
Bin	(4)	1	0	175336	1
Bin	(3)	0	1	357352	1
Bin	(3)	1	0	358953	1
Bin	(2)	0	1	1050788	1
Bin	(2)	1	0	1052389	1
Bin	(1)	0	1	36693723	1
Bin	(1)	1	0	36695323	1
Bin	(0)	0	1	38429203	1
Bin	(0)	1	0	38427603	1

Signal:

TQ_COUNTER_EXPIRED

	From	To	Count	Threshold
Bin	0	1	35305112	1
Bin	1	0	35306702	1

Signal:

TQ_EDGE_I

	From	To	Count	Threshold
Bin	0	1	35305112	1
Bin	1	0	35306702	1

Signal:

SEGM_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(6)	0	1	167587	1
Bin	(6)	1	0	169188	1
Bin	(5)	0	1	254912	1
Bin	(5)	1	0	256513	1
Bin	(4)	0	1	805739	1
Bin	(4)	1	0	807340	1
Bin	(3)	0	1	4536178	1
Bin	(3)	1	0	4537779	1
Bin	(2)	0	1	12044038	1
Bin	(2)	1	0	12045639	1
Bin	(1)	0	1	24795673	1
Bin	(1)	1	0	24797274	1
Bin	(0)	0	1	63536334	1
Bin	(0)	1	0	63534735	1

Signal:

SEGM_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(6)	0	1	142320	1
Bin	(6)	1	0	143921	1
Bin	(5)	0	1	248387	1
Bin	(5)	1	0	249988	1
Bin	(4)	0	1	798552	1
Bin	(4)	1	0	800153	1
Bin	(3)	0	1	4518748	1
Bin	(3)	1	0	4520349	1
Bin	(2)	0	1	12010808	1
Bin	(2)	1	0	12012409	1
Bin	(1)	0	1	22910154	1
Bin	(1)	1	0	22911755	1
Bin	(0)	0	1	42613854	1
Bin	(0)	1	0	42615454	1

Signal:

SEGM_COUNTER_CE

	From	To	Count	Threshold
Bin	0	1	48259936	1
Bin	1	0	48261535	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

 tq_counter_expired = '1' or tq_reset = '1' 
 <---------LHS---------->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	82155075	1
Bin	False	True	4444472	1
Bin	True	False	85863130	1

"=" expression on line 166:

tq_counter_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	86599547	1
Bin	True	110703706	1

"=" expression on line 166:

tq_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	168018205	1
Bin	True	29285048	1

"=" expression on line 172:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 175:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	408329710	1
Bin	True	138844624	1

"=" expression on line 189:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	106153392	1
Bin	True	32934111	1

"or" expression on line 192:

 (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
  <----LHS----->      <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	48299899	1
Bin	False	True	42149660	1
Bin	True	False	16099553	1

"=" expression on line 192:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	90449559	1
Bin	True	26088819	1

"and" expression on line 192:

 tq_edge_i = '1' and ctrs_en = '1' 
 <-----LHS----->     <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	38516166	1
Bin	True	False	23382083	1
Bin	True	True	52138926	1

"=" expression on line 192:

tq_edge_i = '1'

	Evaluated to	Count	Threshold
Bin	False	41017369	1
Bin	True	75521009	1

"=" expression on line 192:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	25883286	1
Bin	True	90655092	1

"=" expression on line 198:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 201:

segm_counter_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	441032339	1
Bin	True	106141995	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_COUNTERS_DBT

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

Signal assignment statement on line 155:

Signal assignment statement on line 157:

If statement on lines 165 to 168:

Signal assignment statement on line 166:

Signal assignment statement on line 168:

If statement on lines 172 to 178:

Signal assignment statement on line 173:

If statement on lines 175 to 177:

Signal assignment statement on line 176:

Signal assignment statement on line 184:

If statement on lines 189 to 190:

Signal assignment statement on line 189:

Signal assignment statement on line 190:

If statement on lines 192 to 194:

Signal assignment statement on line 192:

Signal assignment statement on line 194:

If statement on lines 198 to 204:

Signal assignment statement on line 199:

If statement on lines 201 to 203:

Signal assignment statement on line 202:

Signal assignment statement on line 210:

Signal assignment statement on line 211:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 172:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 175:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on line 192:

"if" / "when" / "else" condition on line 198:

"if" / "when" / "else" condition on line 200:

"if" / "when" / "else" condition on line 201:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 172:

"=" expression on line 175:

"=" expression on line 189:

"or" expression on line 192:

"=" expression on line 192:

"and" expression on line 192:

"=" expression on line 192:

"=" expression on line 192:

"=" expression on line 198:

"=" expression on line 201:

Uncovered FSM states:

Excluded FSM states: