NVC code coverage report

Signal assignment statement on line 183:

183:    req_input(1) <= exit_segm_req_nbt; 
Count: 33038226
Threshold: 1

---

Signal assignment statement on line 184:

184:    req_input(2) <= exit_segm_req_dbt; 
Count: 20068130
Threshold: 1

---

Signal assignment statement on line 191:

191:    segm_end_req_capt_clr(1) <= segment_end_i; 
Count: 45724148
Threshold: 1

---

Signal assignment statement on line 192:

192:    segm_end_req_capt_clr(2) <= segment_end_i; 
Count: 45724148
Threshold: 1

---

If statement on lines 229 to 231:

229:    segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') 
230:                                            else 
231:                               req_input(1) or segm_end_req_capt_q(1); 
Count: 64174526
Threshold: 1

---

Signal assignment statement on line 229:

229:    segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') 
Count: 28756082
Threshold: 1

---

Signal assignment statement on line 231:

231:                               req_input(1) or segm_end_req_capt_q(1); 
Count: 35418444
Threshold: 1

---

If statement on lines 233 to 235:

233:    segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') 
234:                                            else 
235:                               req_input(2) or segm_end_req_capt_q(2); 
Count: 49660052
Threshold: 1

---

Signal assignment statement on line 233:

233:    segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') 
Count: 24839969
Threshold: 1

---

Signal assignment statement on line 235:

235:                               req_input(2) or segm_end_req_capt_q(2); 
Count: 24820083
Threshold: 1

---

If statement on lines 240 to 242:

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 
241:                         else 
242:                     '0'; 
Count: 198587784
Threshold: 1

---

Signal assignment statement on line 240:

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 
Count: 77261816
Threshold: 1

---

Signal assignment statement on line 242:

242:                     '0'; 
Count: 121325968
Threshold: 1

---

If statement on lines 244 to 247:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE)) 
246:                         else 
247:                     '0'; 
Count: 70670334
Threshold: 1

---

Signal assignment statement on line 244:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
Count: 34403342
Threshold: 1

---

Signal assignment statement on line 247:

247:                     '0'; 
Count: 36266992
Threshold: 1

---

If statement on lines 253 to 256:

253:    segm_end_nbt_valid <= 
254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 
255:            else 
256:        '0'; 
Count: 187561141
Threshold: 1

---

Signal assignment statement on line 254:

254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 
Count: 13061229
Threshold: 1

---

Signal assignment statement on line 256:

256:        '0'; 
Count: 174499912
Threshold: 1

---

If statement on lines 258 to 261:

258:    segm_end_dbt_valid <= 
259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 
260:            else 
261:        '0'; 
Count: 88869047
Threshold: 1

---

Signal assignment statement on line 259:

259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 
Count: 9790799
Threshold: 1

---

Signal assignment statement on line 261:

261:        '0'; 
Count: 79078248
Threshold: 1

---

If statement on lines 263 to 266:

263:    segm_end_nbt_dbt_valid <= 
264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 
265:            else 
266:        '0'; 
Count: 45707256
Threshold: 1

---

Signal assignment statement on line 264:

264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 
Count: 22852028
Threshold: 1

---

Signal assignment statement on line 266:

266:        '0'; 
Count: 22855228
Threshold: 1

---

If statement on lines 271 to 273:

271:    tseg1_end_req_valid <= 
272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 
273:        '0'; 
Count: 68564676
Threshold: 1

---

Signal assignment statement on line 272:

272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 
Count: 22851615
Threshold: 1

---

Signal assignment statement on line 273:

273:        '0'; 
Count: 45713061
Threshold: 1

---

If statement on lines 275 to 278:

275:    tseg2_end_req_valid <= 
276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 
277:            else 
278:        '0'; 
Count: 68553648
Threshold: 1

---

Signal assignment statement on line 276:

276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 
Count: 22839112
Threshold: 1

---

Signal assignment statement on line 278:

278:        '0'; 
Count: 45714536
Threshold: 1

---

If statement on lines 284 to 286:

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 
285:                          else 
286:                      '0'; 
Count: 154636650
Threshold: 1

---

Signal assignment statement on line 284:

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 
Count: 54910
Threshold: 1

---

Signal assignment statement on line 286:

286:                      '0'; 
Count: 154581740
Threshold: 1

---

If statement on lines 297 to 301:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or 
299:                               (h_sync_valid_i = '1' and is_tseg2 = '1')) 
300:                         else 
301:                     '0'; 
Count: 91500594
Threshold: 1

---

Signal assignment statement on line 297:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
Count: 68541811
Threshold: 1

---

Signal assignment statement on line 301:

301:                     '0'; 
Count: 22958783
Threshold: 1

---

If statement on lines 309 to 311:

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 
310:                          else 
311:                      '0'; 
Count: 45823896
Threshold: 1

---

Signal assignment statement on line 309:

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 
Count: 22926697
Threshold: 1

---

Signal assignment statement on line 311:

311:                      '0'; 
Count: 22897199
Threshold: 1

---

Signal assignment statement on line 313:

313:    bt_ctr_clear    <= bt_ctr_clear_i; 
Count: 45791198
Threshold: 1

---

Signal assignment statement on line 314:

314:    segm_end        <= segment_end_i; 
Count: 45724148
Threshold: 1

---

Signal assignment statement on line 315:

315:    h_sync_valid    <= h_sync_valid_i; 
Count: 113022
Threshold: 1

"if" / "when" / "else" condition on line 229:

229:    segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') 

	Evaluated to	Count	Threshold
Bin	True	28756082	1
Bin	False	35418444	1

---

"if" / "when" / "else" condition on line 233:

233:    segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') 

	Evaluated to	Count	Threshold
Bin	True	24839969	1
Bin	False	24820083	1

---

"if" / "when" / "else" condition on line 240:

240:    nbt_tq_active <= '1' when (sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1') 

	Evaluated to	Count	Threshold
Bin	True	77261816	1
Bin	False	121325968	1

---

"if" / "when" / "else" condition on lines 244 to 245:

244:    dbt_tq_active <= '1' when (tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or 
245:                                                      sp_control = SECONDARY_SAMPLE)) 

	Evaluated to	Count	Threshold
Bin	True	34403342	1
Bin	False	36266992	1

---

"if" / "when" / "else" condition on line 254:

254:        '1' when (segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1') 

	Evaluated to	Count	Threshold
Bin	True	13061229	1
Bin	False	174499912	1

---

"if" / "when" / "else" condition on line 259:

259:        '1' when (segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1') 

	Evaluated to	Count	Threshold
Bin	True	9790799	1
Bin	False	79078248	1

---

"if" / "when" / "else" condition on line 264:

264:        '1' when (segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1') 

	Evaluated to	Count	Threshold
Bin	True	22852028	1
Bin	False	22855228	1

---

"if" / "when" / "else" condition on line 272:

272:        '1' when (is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1') else 

	Evaluated to	Count	Threshold
Bin	True	22851615	1
Bin	False	45713061	1

---

"if" / "when" / "else" condition on line 276:

276:        '1' when (is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1') 

	Evaluated to	Count	Threshold
Bin	True	22839112	1
Bin	False	45714536	1

---

"if" / "when" / "else" condition on line 284:

284:    h_sync_valid_i <= '1' when ((h_sync_edge_valid = '1') and (nbt_tq_active = '1')) 

	Evaluated to	Count	Threshold
Bin	True	54910	1
Bin	False	154581740	1

---

"if" / "when" / "else" condition on lines 297 to 299:

297:    segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or 
298:                               tseg2_end_req_valid = '1' or 
299:                               (h_sync_valid_i = '1' and is_tseg2 = '1')) 

	Evaluated to	Count	Threshold
Bin	True	68541811	1
Bin	False	22958783	1

---

"if" / "when" / "else" condition on line 309:

309:    bt_ctr_clear_i <= '1' when (segment_end_i = '1' or h_sync_valid_i = '1') 

	Evaluated to	Count	Threshold
Bin	True	22926697	1
Bin	False	22897199	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SP_CONTROL

	Element	From	To	Count	Threshold	Excluded due to
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 H_SYNC_EDGE_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 EXIT_SEGM_REQ_NBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 EXIT_SEGM_REQ_DBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TQ_EDGE_NBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TQ_EDGE_DBT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

 SEGM_END

	From	To	Count	Threshold
Bin	0	1	22860474	1
Bin	1	0	22862073	1

---

Port:

 H_SYNC_VALID

	From	To	Count	Threshold
Bin	0	1	54910	1
Bin	1	0	56511	1

---

Port:

 BT_CTR_CLEAR

	From	To	Count	Threshold
Bin	0	1	22893999	1
Bin	1	0	22895598	1

---

Signal:

 REQ_INPUT

	Element	From	To	Count	Threshold
Bin	(2)	0	1	13711028	1
Bin	(2)	1	0	35754288	1
Bin	(1)	0	1	16600679	1
Bin	(1)	1	0	32864637	1

---

Signal:

 SEGM_END_REQ_CAPT_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	10254002	1
Bin	(2)	1	0	35770035	1
Bin	(1)	0	1	13208845	1
Bin	(1)	1	0	32815192	1

---

Signal:

 SEGM_END_REQ_CAPT_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	3457888	1
Bin	(2)	1	0	11402479	1
Bin	(1)	0	1	4185952	1
Bin	(1)	1	0	10674415	1

---

Signal:

 SEGM_END_REQ_CAPT_CE

	Element	From	To	Count	Threshold
Bin	(2)	0	1	32803525	1
Bin	(2)	1	0	35765469	1
Bin	(1)	0	1	35758368	1
Bin	(1)	1	0	32810626	1

---

Signal:

 SEGM_END_REQ_CAPT_CLR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	22860474	1
Bin	(2)	1	0	22862073	1
Bin	(1)	0	1	22860474	1
Bin	(1)	1	0	22862073	1

---

Signal:

 SEGM_END_REQ_CAPT_DQ

	Element	From	To	Count	Threshold
Bin	(2)	0	1	13710764	1
Bin	(2)	1	0	35750254	1
Bin	(1)	0	1	16600242	1
Bin	(1)	1	0	32860776	1

---

Signal:

 SEGM_END_NBT_VALID

	From	To	Count	Threshold
Bin	0	1	13061229	1
Bin	1	0	13062828	1

---

Signal:

 SEGM_END_DBT_VALID

	From	To	Count	Threshold
Bin	0	1	9790799	1
Bin	1	0	9792400	1

---

Signal:

 SEGM_END_NBT_DBT_VALID

	From	To	Count	Threshold
Bin	0	1	22852028	1
Bin	1	0	22853627	1

---

Signal:

 TSEG1_END_REQ_VALID

	From	To	Count	Threshold
Bin	0	1	22851615	1
Bin	1	0	22853216	1

---

Signal:

 TSEG2_END_REQ_VALID

	From	To	Count	Threshold
Bin	0	1	22839112	1
Bin	1	0	22840711	1

---

Signal:

 H_SYNC_VALID_I

	From	To	Count	Threshold
Bin	0	1	54910	1
Bin	1	0	56511	1

---

Signal:

 SEGMENT_END_I

	From	To	Count	Threshold
Bin	0	1	22860474	1
Bin	1	0	22862073	1

---

Signal:

 NBT_TQ_ACTIVE

	From	To	Count	Threshold
Bin	0	1	77261816	1
Bin	1	0	77263412	1

---

Signal:

 DBT_TQ_ACTIVE

	From	To	Count	Threshold
Bin	0	1	34401982	1
Bin	1	0	34403583	1

---

Signal:

 BT_CTR_CLEAR_I

	From	To	Count	Threshold
Bin	0	1	22893999	1
Bin	1	0	22895598	1

"and" expression on lines 244 to 245:

 tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
 <------LHS------>      <--------------------------RHS-------------------------->  

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

---

"or" expression on lines 244 to 245:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------> 

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"=" expression on line 229:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	35418444	1
Bin	True	28756082	1

---

"or" expression on line 231:

 req_input(1) or segm_end_req_capt_q(1) 
 <---LHS---->    <--------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	14791964	1
Bin	'0'	'1'	1155	1
Bin	'1'	'0'	18558298	1

---

"=" expression on line 233:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	24820083	1
Bin	True	24839969	1

---

"or" expression on line 235:

 req_input(2) or segm_end_req_capt_q(2) 
 <---LHS---->    <--------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	11428015	1
Bin	'0'	'1'	1725	1
Bin	'1'	'0'	11702098	1

---

"and" expression on line 240:

 sp_control = NOMINAL_SAMPLE and tq_edge_nbt = '1' 
 <-----------LHS----------->     <------RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22030520	1
Bin	True	False	77262762	1
Bin	True	True	77261816	1

---

"=" expression on line 240:

 tq_edge_nbt = '1' 

	Evaluated to	Count	Threshold
Bin	False	99295448	1
Bin	True	99292336	1

---

"and" expression on lines 244 to 245:

 tq_edge_dbt = '1' and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
 <------LHS------>      <--------------------------RHS-------------------------->  

	LHS	RHS	Count	Threshold
Bin	True	False	946491	1
Bin	True	True	34403342	1

---

"=" expression on line 244:

 tq_edge_dbt = '1' 

	Evaluated to	Count	Threshold
Bin	False	35320501	1
Bin	True	35349833	1

---

"or" expression on lines 244 to 245:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	946491	1
Bin	False	True	1046266	1

---

"and" expression on line 254:

 segm_end_req_capt_dq(1) = '1' and nbt_tq_active = '1' 
 <------------LHS------------>     <-------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	True	82215846	1
Bin	True	False	11562326	1
Bin	True	True	13061229	1

---

"=" expression on line 254:

 segm_end_req_capt_dq(1) = '1' 

	Evaluated to	Count	Threshold
Bin	False	162937586	1
Bin	True	24623555	1

---

"=" expression on line 254:

 nbt_tq_active = '1' 

	Evaluated to	Count	Threshold
Bin	False	92284066	1
Bin	True	95277075	1

---

"and" expression on line 259:

 segm_end_req_capt_dq(2) = '1' and dbt_tq_active = '1' 
 <------------LHS------------>     <-------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	True	37866503	1
Bin	True	False	6564292	1
Bin	True	True	9790799	1

---

"=" expression on line 259:

 segm_end_req_capt_dq(2) = '1' 

	Evaluated to	Count	Threshold
Bin	False	72513956	1
Bin	True	16355091	1

---

"=" expression on line 259:

 dbt_tq_active = '1' 

	Evaluated to	Count	Threshold
Bin	False	41211745	1
Bin	True	47657302	1

---

"or" expression on line 264:

 segm_end_nbt_valid = '1' or segm_end_dbt_valid = '1' 
 <---------LHS---------->    <---------RHS----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	22855228	1
Bin	False	True	9790799	1
Bin	True	False	13061229	1

---

"=" expression on line 264:

 segm_end_nbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	32646027	1
Bin	True	13061229	1

---

"=" expression on line 264:

 segm_end_dbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	35916457	1
Bin	True	9790799	1

---

"and" expression on line 272:

 is_tseg1 = '1' and segm_end_nbt_dbt_valid = '1' 
 <----LHS----->     <-----------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22839431	1
Bin	True	False	11442112	1
Bin	True	True	22851615	1

---

"=" expression on line 272:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34270949	1
Bin	True	34293727	1

---

"=" expression on line 272:

 segm_end_nbt_dbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	22873630	1
Bin	True	45691046	1

---

"and" expression on line 276:

 is_tseg2 = '1' and segm_end_nbt_dbt_valid = '1' 
 <----LHS----->     <-----------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22852029	1
Bin	True	False	11423194	1
Bin	True	True	22839112	1

---

"=" expression on line 276:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34291342	1
Bin	True	34262306	1

---

"=" expression on line 276:

 segm_end_nbt_dbt_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	22862507	1
Bin	True	45691141	1

---

"and" expression on line 284:

 (h_sync_edge_valid = '1') and (nbt_tq_active = '1') 
  <---------LHS--------->       <-------RHS------->  

	LHS	RHS	Count	Threshold
Bin	False	True	77312057	1
Bin	True	False	4670	1
Bin	True	True	54910	1

---

"=" expression on line 284:

 h_sync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	154577070	1
Bin	True	59580	1

---

"=" expression on line 284:

 nbt_tq_active = '1' 

	Evaluated to	Count	Threshold
Bin	False	77269683	1
Bin	True	77366967	1

---

"or" expression on lines 297 to 299:

 (tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or tseg2_end_req_valid = '1' or (h_sync_valid_i = '1' and is_tseg2 = '1') 
 <--------------------------------------LHS-------------------------------------->     <-----------------RHS----------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	22958783	1
Bin	False	True	7585	1
Bin	True	False	68531687	1

---

"or" expression on lines 297 to 298:

 (tseg1_end_req_valid = '1' and h_sync_valid_i = '0') or tseg2_end_req_valid = '1' 
  <----------------------LHS----------------------->     <----------RHS----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	22966368	1
Bin	False	True	34256888	1
Bin	True	False	34277338	1

---

"and" expression on line 297:

 tseg1_end_req_valid = '1' and h_sync_valid_i = '0' 
 <----------LHS---------->     <-------RHS--------> 

	LHS	RHS	Count	Threshold
Bin	False	True	57146626	1
Bin	True	False	13507	1
Bin	True	True	34277338	1

---

"=" expression on line 297:

 tseg1_end_req_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	57209749	1
Bin	True	34290845	1

---

"=" expression on line 297:

 h_sync_valid_i = '0' 

	Evaluated to	Count	Threshold
Bin	False	76630	1
Bin	True	91423964	1

---

"=" expression on line 298:

 tseg2_end_req_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	57243706	1
Bin	True	34256888	1

---

"and" expression on line 299:

 h_sync_valid_i = '1' and is_tseg2 = '1' 
 <-------LHS-------->     <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	45684834	1
Bin	True	False	64905	1
Bin	True	True	10124	1

---

"=" expression on line 299:

 h_sync_valid_i = '1' 

	Evaluated to	Count	Threshold
Bin	False	91425565	1
Bin	True	75029	1

---

"=" expression on line 299:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	45805636	1
Bin	True	45694958	1

---

"or" expression on line 309:

 segment_end_i = '1' or h_sync_valid_i = '1' 
 <-------LHS------->    <-------RHS--------> 

	LHS	RHS	Count	Threshold
Bin	False	False	22897199	1
Bin	False	True	51066	1
Bin	True	False	22855110	1

---

"=" expression on line 309:

 segment_end_i = '1' 

	Evaluated to	Count	Threshold
Bin	False	22948265	1
Bin	True	22875631	1

---

"=" expression on line 309:

 h_sync_valid_i = '1' 

	Evaluated to	Count	Threshold
Bin	False	45752309	1
Bin	True	71587	1