NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_FSM

File:  /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_FSM 100.0 % (29/29) 100.0 % (26/26) 100.0 % (18/18) 100.0 % (18/18) 100.0 % (6/6) N.A. 100.0 % (97/97)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 143:

143:        next_state <= current_state; 
Count: 68597886
Threshold: 1

If statement on lines 145 to 160:

145:        if (mr_settings_ena = CTU_CAN_DISABLED) then 
146:            next_state <= s_bt_reset; 
...
159:            end case; 
160:        end if; 
Count: 68597886
Threshold: 1

Signal assignment statement on line 146:

146:            next_state <= s_bt_reset; 
Count: 12192
Threshold: 1

Sequential statement on lines 148 to 159:

148:            case current_state is 
149:            when s_bt_tseg1 => 
...
158:                next_state <= s_bt_tseg1; 
159:            end case; 
Count: 68585694
Threshold: 1

If statement on lines 150 to 152:

150:                if (segm_end = '1') then 
151:                    next_state <= s_bt_tseg2; 
152:                end if; 
Count: 34306188
Threshold: 1

Signal assignment statement on line 151:

151:                    next_state <= s_bt_tseg2; 
Count: 22860049
Threshold: 1

If statement on lines 154 to 156:

154:                if (segm_end = '1') then 
155:                    next_state <= s_bt_tseg1; 
156:                end if; 
Count: 34268191
Threshold: 1

Signal assignment statement on line 155:

155:                    next_state <= s_bt_tseg1; 
Count: 22845018
Threshold: 1

Signal assignment statement on line 158:

158:                next_state <= s_bt_tseg1; 
Count: 11315
Threshold: 1

Signal assignment statement on line 169:

169:        is_tseg1       <= '0'; 
Count: 68597886
Threshold: 1

Signal assignment statement on line 170:

170:        is_tseg2       <= '0'; 
Count: 68597886
Threshold: 1

Signal assignment statement on line 171:

171:        rx_trig_req    <= '0'; 
Count: 68597886
Threshold: 1

Signal assignment statement on line 172:

172:        tx_trig_req    <= '0'; 
Count: 68597886
Threshold: 1

Sequential statement on lines 174 to 192:

174:        case current_state is 
175:        when s_bt_reset => 
...
191: 
192:        end case; 
Count: 68597886
Threshold: 1

If statement on lines 176 to 178:

176:            if (mr_settings_ena = CTU_CAN_ENABLED) then 
177:                tx_trig_req <= '1'; 
178:            end if; 
Count: 20100
Threshold: 1

Signal assignment statement on line 177:

177:                tx_trig_req <= '1'; 
Count: 9714
Threshold: 1

Signal assignment statement on line 181:

181:            is_tseg1 <= '1'; 
Count: 34309024
Threshold: 1

If statement on lines 182 to 184:

182:            if (segm_end = '1') then 
183:                rx_trig_req <= '1'; 
184:            end if; 
Count: 34309024
Threshold: 1

Signal assignment statement on line 183:

183:                rx_trig_req <= '1'; 
Count: 22860161
Threshold: 1

Signal assignment statement on line 187:

187:            is_tseg2 <= '1'; 
Count: 34268762
Threshold: 1

If statement on lines 188 to 190:

188:            if (segm_end = '1') then 
189:                tx_trig_req <= '1'; 
190:            end if; 
Count: 34268762
Threshold: 1

Signal assignment statement on line 189:

189:                tx_trig_req <= '1'; 
Count: 22845073
Threshold: 1

If statement on lines 200 to 206:

200:        if (rst_n = '0') then 
201:            current_state <= s_bt_reset; 
...
205:            end if; 
206:        end if; 
Count: 1096781321
Threshold: 1

Signal assignment statement on line 201:

201:            current_state <= s_bt_reset; 
Count: 2422674
Threshold: 1

If statement on lines 203 to 205:

203:            if (bt_fsm_ce = '1') then 
204:                current_state <= next_state; 
205:            end if; 
Count: 547174334
Threshold: 1

Signal assignment statement on line 204:

204:                current_state <= next_state; 
Count: 22854352
Threshold: 1

If statement on lines 209 to 210:

209:    bt_fsm_ce <= '1' when (next_state /= current_state) else 
210:                 '0'; 
Count: 91441198
Threshold: 1

Signal assignment statement on line 209:

209:    bt_fsm_ce <= '1' when (next_state /= current_state) else 
Count: 45720786
Threshold: 1

Signal assignment statement on line 210:

210:                 '0'; 
Count: 45720412
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 145:

145:        if (mr_settings_ena = CTU_CAN_DISABLED) then 
Evaluated toCountThreshold
BinTrue121921
BinFalse685856941

"case" / "with" / "select" choice on line 149:

149:            when s_bt_tseg1 => 
Choice ofCountThreshold
Bins_bt_tseg1343061881

"if" / "when" / "else" condition on line 150:

150:                if (segm_end = '1') then 
Evaluated toCountThreshold
BinTrue228600491
BinFalse114461391

"case" / "with" / "select" choice on line 153:

153:            when s_bt_tseg2 => 
Choice ofCountThreshold
Bins_bt_tseg2342681911

"if" / "when" / "else" condition on line 154:

154:                if (segm_end = '1') then 
Evaluated toCountThreshold
BinTrue228450181
BinFalse114231731

"case" / "with" / "select" choice on line 157:

157:            when s_bt_reset => 
Choice ofCountThreshold
Bins_bt_reset113151

"case" / "with" / "select" choice on line 175:

175:        when s_bt_reset => 
Choice ofCountThreshold
Bins_bt_reset201001

"if" / "when" / "else" condition on line 176:

176:            if (mr_settings_ena = CTU_CAN_ENABLED) then 
Evaluated toCountThreshold
BinTrue97141
BinFalse103861

"case" / "with" / "select" choice on line 180:

180:        when s_bt_tseg1 => 
Choice ofCountThreshold
Bins_bt_tseg1343090241

"if" / "when" / "else" condition on line 182:

182:            if (segm_end = '1') then 
Evaluated toCountThreshold
BinTrue228601611
BinFalse114488631

"case" / "with" / "select" choice on line 186:

186:        when s_bt_tseg2 => 
Choice ofCountThreshold
Bins_bt_tseg2342687621

"if" / "when" / "else" condition on line 188:

188:            if (segm_end = '1') then 
Evaluated toCountThreshold
BinTrue228450731
BinFalse114236891

"if" / "when" / "else" condition on line 200:

200:        if (rst_n = '0') then 
Evaluated toCountThreshold
BinTrue24226741
BinFalse10943586471

"if" / "when" / "else" condition on line 202:

202:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471743341
BinFalse5471843131

"if" / "when" / "else" condition on line 203:

203:            if (bt_fsm_ce = '1') then 
Evaluated toCountThreshold
BinTrue228543521
BinFalse5243199821

"if" / "when" / "else" condition on line 209:

209:    bt_fsm_ce <= '1' when (next_state /= current_state) else 
Evaluated toCountThreshold
BinTrue457207861
BinFalse457204121

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RST_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 MR_SETTINGS_ENA
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 SEGM_END
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Port:

 IS_TSEG1
FromToCountThreshold
Bin01114295151
Bin10114295061

Port:

 IS_TSEG2
FromToCountThreshold
Bin01114231971
Bin10114247961

Port:

 RX_TRIG_REQ
FromToCountThreshold
Bin01228600611
Bin10228616621

Port:

 TX_TRIG_REQ
FromToCountThreshold
Bin01228543761
Bin10228559741

Signal:

 BT_FSM_CE
FromToCountThreshold
Bin01457188141
Bin10457204121

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 145:

 mr_settings_ena = CTU_CAN_DISABLED 
Evaluated toCountThreshold
BinFalse685856941
BinTrue121921

"=" expression on line 150:

 segm_end = '1' 
Evaluated toCountThreshold
BinFalse114461391
BinTrue228600491

"=" expression on line 154:

 segm_end = '1' 
Evaluated toCountThreshold
BinFalse114231731
BinTrue228450181

"=" expression on line 176:

 mr_settings_ena = CTU_CAN_ENABLED 
Evaluated toCountThreshold
BinFalse103861
BinTrue97141

"=" expression on line 182:

 segm_end = '1' 
Evaluated toCountThreshold
BinFalse114488631
BinTrue228601611

"=" expression on line 188:

 segm_end = '1' 
Evaluated toCountThreshold
BinFalse114236891
BinTrue228450731

"=" expression on line 200:

 rst_n = '0' 
Evaluated toCountThreshold
BinFalse10943586471
BinTrue24226741

"=" expression on line 203:

 bt_fsm_ce = '1' 
Evaluated toCountThreshold
BinFalse5243199821
BinTrue228543521

"/=" expression on line 209:

 next_state /= current_state 
Evaluated toCountThreshold
BinFalse457204121
BinTrue457207861

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

"T_BIT_TIME" FSM on line 130:

130:    signal current_state    : t_bit_time; 
StateCountThreshold
BinS_BT_TSEG1114295151
BinS_BT_TSEG2114231971
BinS_BT_RESET80721

"T_BIT_TIME" FSM on line 131:

131:    signal next_state       : t_bit_time; 
StateCountThreshold
BinS_BT_TSEG1342907211
BinS_BT_TSEG2342832221
BinS_BT_RESET80721

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: