NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_BIT_ERR_DETECTOR	100.0 % (25/25)	100.0 % (24/24)	100.0 % (38/38)	100.0 % (56/56)	N.A.	N.A.	100.0 % (143/143)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_BIT_ERR_DETECTOR

100.0 % (25/25)

100.0 % (24/24)

100.0 % (38/38)

100.0 % (56/56)

N.A.

100.0 % (143/143)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 163 to 167:

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and 
165:                                       bit_err_enable = '1') 
166:                                 else 
167:                             '0';

Count: 3542364
Threshold: 1

Signal assignment statement on line 163:

163: bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and
Count: 106131
Threshold: 1

Signal assignment statement on line 167:

167: '0';
Count: 3436233
Threshold: 1

If statement on lines 174 to 176:

174:    bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else 
175:                          '1' when (bit_err_ssp_condition = '1') else 
176:          bit_err_ssp_capt_q;

Count: 45871970
Threshold: 1

Signal assignment statement on line 174:

174: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else
Count: 22927792
Threshold: 1

Signal assignment statement on line 175:

175: '1' when (bit_err_ssp_condition = '1') else
Count: 39603
Threshold: 1

Signal assignment statement on line 176:

176: bit_err_ssp_capt_q;
Count: 22904575
Threshold: 1

If statement on lines 180 to 184:

180:        if (rst_n = '0') then 
181:            bit_err_ssp_capt_q <= '0'; 
182:        elsif (rising_edge(clk_sys)) then 
183:            bit_err_ssp_capt_q <= bit_err_ssp_capt_d; 
184:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 181:

181: bit_err_ssp_capt_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 183:

183: bit_err_ssp_capt_q <= bit_err_ssp_capt_d;
Count: 547174334
Threshold: 1

If statement on lines 192 to 195:

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1')) 
194:                             else 
195:                         '0';

Count: 45928889
Threshold: 1

Signal assignment statement on line 192:

192: bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and
Count: 67777
Threshold: 1

Signal assignment statement on line 195:

195: '0';
Count: 45861112
Threshold: 1

If statement on lines 197 to 202:

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and 
200:                                    bit_err_enable = '1') 
201:                              else 
202:                          '0';

Count: 50007360
Threshold: 1

Signal assignment statement on line 197:

197: bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and
Count: 866133
Threshold: 1

Signal assignment statement on line 202:

202: '0';
Count: 49141227
Threshold: 1

If statement on lines 207 to 210:

207:    bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else 
208:                 '1' when (bit_err_ssp_valid = '1') else 
209:                 '1' when (bit_err_norm_valid = '1') else 
210:                 '0';

Count: 1885527
Threshold: 1

Signal assignment statement on line 207:

207: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else
Count: 8072
Threshold: 1

Signal assignment statement on line 208:

208: '1' when (bit_err_ssp_valid = '1') else
Count: 67752
Threshold: 1

Signal assignment statement on line 209:

209: '1' when (bit_err_norm_valid = '1') else
Count: 866133
Threshold: 1

Signal assignment statement on line 210:

210: '0';
Count: 943570
Threshold: 1

If statement on lines 217 to 221:

217:        if (rst_n = '0') then 
218:            bit_err_q <= '0'; 
219:        elsif (rising_edge(clk_sys)) then 
220:            bit_err_q <= bit_err_d; 
221:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 218:

218: bit_err_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 220:

220: bit_err_q <= bit_err_d;
Count: 547174334
Threshold: 1

Signal assignment statement on line 225:

225: bit_err <= bit_err_q;
Count: 23420
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 163 to 165:

163:    bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and 
164:                                       sample_sec = '1' and 
165:                                       bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	106131	1
Bin	False	3436233	1

"if" / "when" / "else" condition on line 174:

174: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	22927792	1
Bin	False	22944178	1

"if" / "when" / "else" condition on line 175:

175: '1' when (bit_err_ssp_condition = '1') else

	Evaluated to	Count	Threshold
Bin	True	39603	1
Bin	False	22904575	1

"if" / "when" / "else" condition on line 180:

180: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 182:

182: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on lines 192 to 193:

192:    bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and 
193:                                   (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1'))

	Evaluated to	Count	Threshold
Bin	True	67777	1
Bin	False	45861112	1

"if" / "when" / "else" condition on lines 197 to 200:

197:    bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and 
198:                                    data_rx_synced /= data_tx and 
199:                                    rx_trigger = '1' and 
200:                                    bit_err_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	866133	1
Bin	False	49141227	1

"if" / "when" / "else" condition on line 207:

207: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else

	Evaluated to	Count	Threshold
Bin	True	8072	1
Bin	False	1877455	1

"if" / "when" / "else" condition on line 208:

208: '1' when (bit_err_ssp_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	67752	1
Bin	False	1809703	1

"if" / "when" / "else" condition on line 209:

209: '1' when (bit_err_norm_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	866133	1
Bin	False	943570	1

"if" / "when" / "else" condition on line 217:

217: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 219:

219: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SAMPLE_SEC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX_DELAYED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_RX_SYNCED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

BIT_ERR

	From	To	Count	Threshold
Bin	0	1	10109	1
Bin	1	0	11710	1

Signal:

BIT_ERR_D

	From	To	Count	Threshold
Bin	0	1	933885	1
Bin	1	0	935486	1

Signal:

BIT_ERR_Q

	From	To	Count	Threshold
Bin	0	1	10109	1
Bin	1	0	11710	1

Signal:

BIT_ERR_SSP_CAPT_D

	From	To	Count	Threshold
Bin	0	1	39150	1
Bin	1	0	40751	1

Signal:

BIT_ERR_SSP_CAPT_Q

	From	To	Count	Threshold
Bin	0	1	589	1
Bin	1	0	2190	1

Signal:

BIT_ERR_SSP_VALID

	From	To	Count	Threshold
Bin	0	1	67752	1
Bin	1	0	69353	1

Signal:

BIT_ERR_SSP_CONDITION

	From	To	Count	Threshold
Bin	0	1	106131	1
Bin	1	0	107732	1

Signal:

BIT_ERR_NORM_VALID

	From	To	Count	Threshold
Bin	0	1	866133	1
Bin	1	0	867734	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on lines 163 to 165:

 data_tx_delayed /= data_rx_synced and sample_sec = '1' and bit_err_enable = '1' 
 <------------------------LHS------------------------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	1509623	1
Bin	True	False	938	1
Bin	True	True	106131	1

"and" expression on lines 163 to 164:

 data_tx_delayed /= data_rx_synced and sample_sec = '1' 
 <--------------LHS-------------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	194929	1
Bin	True	False	1587179	1
Bin	True	True	107069	1

"/=" expression on line 163:

data_tx_delayed /= data_rx_synced

	Evaluated to	Count	Threshold
Bin	False	1848116	1
Bin	True	1694248	1

"=" expression on line 164:

sample_sec = '1'

	Evaluated to	Count	Threshold
Bin	False	3240366	1
Bin	True	301998	1

"=" expression on line 165:

bit_err_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	1926610	1
Bin	True	1615754	1

"=" expression on line 174:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	22944178	1
Bin	True	22927792	1

"=" expression on line 175:

bit_err_ssp_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	22904575	1
Bin	True	39603	1

"=" expression on line 180:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"and" expression on lines 192 to 193:

 sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1') 
 <----------------------LHS----------------------->      <-------------------------RHS------------------------->

	LHS	RHS	Count	Threshold
Bin	False	True	40379	1
Bin	True	False	388843	1
Bin	True	True	67777	1

"and" expression on line 192:

 sp_control = SECONDARY_SAMPLE and rx_trigger = '1' 
 <------------LHS------------>     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	22471172	1
Bin	True	False	470308	1
Bin	True	True	456620	1

"=" expression on line 192:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	23001097	1
Bin	True	22927792	1

"or" expression on line 193:

 bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1' 
 <---------LHS---------->    <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	45820733	1
Bin	False	True	106176	1
Bin	True	False	1366	1

"=" expression on line 193:

bit_err_ssp_capt_q = '1'

	Evaluated to	Count	Threshold
Bin	False	45926909	1
Bin	True	1980	1

"=" expression on line 193:

bit_err_ssp_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	45822099	1
Bin	True	106790	1

"and" expression on lines 197 to 200:

 sp_control /= SECONDARY_SAMPLE and data_rx_synced /= data_tx and rx_trigger = '1' and bit_err_enable = '1' 
 <--------------------------------------LHS-------------------------------------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	10817212	1
Bin	True	False	5244330	1
Bin	True	True	866133	1

"and" expression on lines 197 to 199:

 sp_control /= SECONDARY_SAMPLE and data_rx_synced /= data_tx and rx_trigger = '1' 
 <---------------------------LHS---------------------------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	18024726	1
Bin	True	False	6915180	1
Bin	True	True	6110463	1

"and" expression on lines 197 to 198:

 sp_control /= SECONDARY_SAMPLE and data_rx_synced /= data_tx 
 <------------LHS------------->     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	231061	1
Bin	True	False	35977156	1
Bin	True	True	13025643	1

"/=" expression on line 198:

data_rx_synced /= data_tx

	Evaluated to	Count	Threshold
Bin	False	36750656	1
Bin	True	13256704	1

"=" expression on line 199:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	25872171	1
Bin	True	24135189	1

"=" expression on line 200:

bit_err_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	38324015	1
Bin	True	11683345	1

"=" expression on line 207:

mr_settings_ena = CTU_CAN_DISABLED

	Evaluated to	Count	Threshold
Bin	False	1877455	1
Bin	True	8072	1

"=" expression on line 208:

bit_err_ssp_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	1809703	1
Bin	True	67752	1

"=" expression on line 209:

bit_err_norm_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	943570	1
Bin	True	866133	1

"=" expression on line 217:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_BIT_ERR_DETECTOR

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 163 to 167:

Signal assignment statement on line 163:

Signal assignment statement on line 167:

If statement on lines 174 to 176:

Signal assignment statement on line 174:

Signal assignment statement on line 175:

Signal assignment statement on line 176:

If statement on lines 180 to 184:

Signal assignment statement on line 181:

Signal assignment statement on line 183:

If statement on lines 192 to 195:

Signal assignment statement on line 192:

Signal assignment statement on line 195:

If statement on lines 197 to 202:

Signal assignment statement on line 197:

Signal assignment statement on line 202:

If statement on lines 207 to 210:

Signal assignment statement on line 207:

Signal assignment statement on line 208:

Signal assignment statement on line 209:

Signal assignment statement on line 210:

If statement on lines 217 to 221:

Signal assignment statement on line 218:

Signal assignment statement on line 220:

Signal assignment statement on line 225:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 163 to 165:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 175:

"if" / "when" / "else" condition on line 180:

"if" / "when" / "else" condition on line 182:

"if" / "when" / "else" condition on lines 192 to 193:

"if" / "when" / "else" condition on lines 197 to 200:

"if" / "when" / "else" condition on line 207:

"if" / "when" / "else" condition on line 208:

"if" / "when" / "else" condition on line 209:

"if" / "when" / "else" condition on line 217:

"if" / "when" / "else" condition on line 219:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on lines 163 to 165:

"and" expression on lines 163 to 164:

"/=" expression on line 163:

"=" expression on line 164:

"=" expression on line 165:

"=" expression on line 174:

"=" expression on line 175:

"=" expression on line 180: