NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_RST_REG	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
I_RXB_FSM	100.0 % (69/69)	100.0 % (50/50)	100.0 % (48/48)	100.0 % (29/29)	100.0 % (24/24)	100.0 % (3/3)	100.0 % (223/223)
I_RXB_POINTERS	100.0 % (59/59)	100.0 % (60/60)	100.0 % (468/468)	100.0 % (55/55)	N.A.	N.A.	100.0 % (642/642)
I_CLK_GATE_RXB_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
I_RXB_RAM	100.0 % (49/49)	100.0 % (30/30)	100.0 % (271288/271288)	100.0 % (25/25)	N.A.	N.A.	100.0 % (271392/271392)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_RXB_TOP	100.0 % (146/146)	100.0 % (126/126)	100.0 % (1276/1276)	100.0 % (166/166)	N.A.	N.A.	100.0 % (1714/1714)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 436 to 438:

436:    rx_buf_rst_n_d <= '0' when (mr_command_rrb = '1' or rst_n = '0') 
437:                          else 
438:                      '1';

Count: 22744
Threshold: 1

Signal assignment statement on line 436:

436: rx_buf_rst_n_d <= '0' when (mr_command_rrb = '1' or rst_n = '0')
Count: 8532
Threshold: 1

Signal assignment statement on line 438:

438: '1';
Count: 14212
Threshold: 1

Sequential statement on lines 517 to 523:

517:    with data_selector select rxb_port_a_data_in <= 
518:        "0000" & frame_form_w            when "00001", 
...
522:        timestamp_capture(63 downto 32)  when "10000", 
523:        (others => '0')                  when others;

Count: 6449647
Threshold: 1

Signal assignment statement on line 518:

518: "0000" & frame_form_w when "00001",
Count: 27015
Threshold: 1

Signal assignment statement on line 519:

519: "000" & rec_ident when "00010",
Count: 27006
Threshold: 1

Signal assignment statement on line 520:

520: store_data_word when "00100",
Count: 2997320
Threshold: 1

Signal assignment statement on line 521:

521: timestamp_capture(31 downto 0) when "01000",
Count: 13327
Threshold: 1

Signal assignment statement on line 522:

522: timestamp_capture(63 downto 32) when "10000",
Count: 13327
Threshold: 1

Signal assignment statement on line 523:

523: (others => '0') when others;
Count: 3371652
Threshold: 1

If statement on lines 528 to 530:

528:    read_attempt <= mr_rx_data_read when (mr_mode_rxbam = RXBAM_ENABLED) 
529:                                    else 
530:                    mr_command_rxrpmv;

Count: 162650
Threshold: 1

Signal assignment statement on line 528:

528: read_attempt <= mr_rx_data_read when (mr_mode_rxbam = RXBAM_ENABLED)
Count: 157358
Threshold: 1

Signal assignment statement on line 530:

530: mr_command_rxrpmv;
Count: 5292
Threshold: 1

If statement on lines 532 to 534:

532:    read_increment <= '1' when (read_attempt = '1' and rx_empty_i = '0') 
533:                          else 
534:                      '0';

Count: 173998
Threshold: 1

Signal assignment statement on line 532:

532: read_increment <= '1' when (read_attempt = '1' and rx_empty_i = '0')
Count: 50920
Threshold: 1

Signal assignment statement on line 534:

534: '0';
Count: 123078
Threshold: 1

If statement on lines 540 to 543:

540:    write_raw_OK <= '1' when (write_raw_intent = '1' and overrun_condition = '0' and 
541:                              data_overrun_i = '0') 
542:                        else 
543:                    '0';

Count: 230589
Threshold: 1

Signal assignment statement on line 540:

540: write_raw_OK <= '1' when (write_raw_intent = '1' and overrun_condition = '0' and
Count: 112334
Threshold: 1

Signal assignment statement on line 543:

543: '0';
Count: 118255
Threshold: 1

If statement on lines 552 to 554:

552:    is_free_word <= '0' when (read_pointer = write_pointer_raw and frame_count > 0) 
553:                        else 
554:                    '1';

Count: 285299
Threshold: 1

Signal assignment statement on line 552:

552: is_free_word <= '0' when (read_pointer = write_pointer_raw and frame_count > 0)
Count: 47
Threshold: 1

Signal assignment statement on line 554:

554: '1';
Count: 285252
Threshold: 1

If statement on lines 563 to 565:

563:    overrun_condition <= '1' when (write_raw_intent = '1' and is_free_word = '0') 
564:                             else 
565:                         '0';

Count: 227957
Threshold: 1

Signal assignment statement on line 563:

563: overrun_condition <= '1' when (write_raw_intent = '1' and is_free_word = '0')
Count: 45
Threshold: 1

Signal assignment statement on line 565:

565: '0';
Count: 227912
Threshold: 1

If statement on lines 573 to 575:

573:    rxb_port_b_data_out <= rxb_port_b_data_out_i when (rx_empty_i = '0') 
574:                                                 else 
575:                                 (others => '0');

Count: 125439
Threshold: 1

Signal assignment statement on line 573:

573: rxb_port_b_data_out <= rxb_port_b_data_out_i when (rx_empty_i = '0')
Count: 50170
Threshold: 1

Signal assignment statement on line 575:

575: (others => '0');
Count: 75269
Threshold: 1

Sequential statement on lines 581 to 597:

581:    with rec_dlc select rwcnt_com <= 
582:        3 when "0000", --Zero bits 
...
596:        15 when "1110", --48 bytes 
597:        19 when others; --64 bytes

Count: 80123
Threshold: 1

Signal assignment statement on line 582:

582: 3 when "0000", --Zero bits
Count: 40058
Threshold: 1

Signal assignment statement on line 583:

583: 4 when "0001", --1 byte
Count: 8658
Threshold: 1

Signal assignment statement on line 584:

584: 4 when "0010", --2 bytes
Count: 2822
Threshold: 1

Signal assignment statement on line 585:

585: 4 when "0011", --3 bytes
Count: 1255
Threshold: 1

Signal assignment statement on line 586:

586: 4 when "0100", --4 bytes
Count: 1816
Threshold: 1

Signal assignment statement on line 587:

587: 5 when "0101", --5 bytes
Count: 1101
Threshold: 1

Signal assignment statement on line 588:

588: 5 when "0110", --6 bytes
Count: 1515
Threshold: 1

Signal assignment statement on line 589:

589: 5 when "0111", --7 bytes
Count: 1166
Threshold: 1

Signal assignment statement on line 590:

590: 5 when "1000", --8 bytes
Count: 3104
Threshold: 1

Signal assignment statement on line 591:

591: 6 when "1001", --12 bytes
Count: 435
Threshold: 1

Signal assignment statement on line 592:

592: 7 when "1010", --16 bytes
Count: 566
Threshold: 1

Signal assignment statement on line 593:

593: 8 when "1011", --20 bytes
Count: 352
Threshold: 1

Signal assignment statement on line 594:

594: 9 when "1100", --24 bytes
Count: 1099
Threshold: 1

Signal assignment statement on line 595:

595: 11 when "1101", --32 bytes
Count: 723
Threshold: 1

Signal assignment statement on line 596:

596: 15 when "1110", --48 bytes
Count: 581
Threshold: 1

Signal assignment statement on line 597:

597: 19 when others; --64 bytes
Count: 14872
Threshold: 1

Signal assignment statement on line 603:

603: frame_form_w(DLC_H downto DLC_L) <= rec_dlc;
Count: 80123
Threshold: 1

Signal assignment statement on line 604:

604: frame_form_w(ERF_IND) <= rec_erf;
Count: 3878
Threshold: 1

Signal assignment statement on line 605:

605: frame_form_w(RTR_IND) <= rec_is_rtr;
Count: 50472
Threshold: 1

Signal assignment statement on line 606:

606: frame_form_w(IDE_IND) <= rec_ident_type;
Count: 40792
Threshold: 1

Signal assignment statement on line 607:

607: frame_form_w(FDF_IND) <= rec_frame_type;
Count: 60094
Threshold: 1

Signal assignment statement on line 608:

608: frame_form_w(LBPF_IND) <= rec_lbpf;
Count: 3562
Threshold: 1

Signal assignment statement on line 609:

609: frame_form_w(BRS_IND) <= rec_brs;
Count: 43294
Threshold: 1

Signal assignment statement on line 610:

610: frame_form_w(ESI_RSV_IND) <= rec_esi;
Count: 8363
Threshold: 1

Signal assignment statement on line 611:

611: frame_form_w(IVLD_IND) <= rec_ivld;
Count: 105553
Threshold: 1

If statement on lines 619 to 622:

619:    frame_form_w(RWCNT_H downto RWCNT_L)  <= 
620:        "00011" when (rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED) else 
621:        "00101" when ((rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1')) else 
622:         std_logic_vector(to_unsigned(rwcnt_com, (RWCNT_H - RWCNT_L + 1)));

Count: 203118
Threshold: 1

Signal assignment statement on line 620:

620: "00011" when (rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED) else
Count: 26263
Threshold: 1

Signal assignment statement on line 621:

621: "00101" when ((rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1')) else
Count: 6019
Threshold: 1

Signal assignment statement on line 622:

622: std_logic_vector(to_unsigned(rwcnt_com, (RWCNT_H - RWCNT_L + 1)));
Count: 170836
Threshold: 1

If statement on lines 625 to 627:

625:    frame_form_w(ERF_POS_H downto ERF_POS_L) <= err_capt_err_pos when (rec_erf = '1') 
626:                                                                 else 
627:                                                (others => '0');

Count: 14312
Threshold: 1

Signal assignment statement on line 625:

625: frame_form_w(ERF_POS_H downto ERF_POS_L) <= err_capt_err_pos when (rec_erf = '1')
Count: 338
Threshold: 1

Signal assignment statement on line 627:

627: (others => '0');
Count: 13974
Threshold: 1

If statement on lines 629 to 631:

629:    frame_form_w(ERF_TYPE_H downto ERF_TYPE_L) <= err_capt_err_type when (rec_erf = '1') 
630:                                                                    else 
631:                                                  (others => '0');

Count: 9338
Threshold: 1

Signal assignment statement on line 629:

629: frame_form_w(ERF_TYPE_H downto ERF_TYPE_L) <= err_capt_err_type when (rec_erf = '1')
Count: 338
Threshold: 1

Signal assignment statement on line 631:

631:                                                  (others => '0');

Count: 9000
Threshold: 1

If statement on lines 633 to 635:

633:    frame_form_w(ERF_ERP_IND) <= err_capt_err_erp when (rec_erf = '1') 
634:                                                  else 
635:                                              '0';

Count: 6069
Threshold: 1

Signal assignment statement on line 633:

633: frame_form_w(ERF_ERP_IND) <= err_capt_err_erp when (rec_erf = '1')
Count: 338
Threshold: 1

Signal assignment statement on line 635:

635: '0';
Count: 5731
Threshold: 1

If statement on lines 638 to 640:

638:    frame_form_w(LBTBI_H downto LBTBI_L) <= curr_txtb_index when (rec_lbpf = LBPF_LOOPBACK) 
639:                                                            else 
640:                                            (others => '0');

Count: 17449
Threshold: 1

Signal assignment statement on line 638:

638: frame_form_w(LBTBI_H downto LBTBI_L) <= curr_txtb_index when (rec_lbpf = LBPF_LOOPBACK)
Count: 350
Threshold: 1

Signal assignment statement on line 640:

640: (others => '0');
Count: 17099
Threshold: 1

If statement on lines 648 to 654:

648:    timestamp_capture_ce <= '1' when (mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1') 
649:                                else 
...
653:                                else 
654:                            '0';

Count: 256339
Threshold: 1

Signal assignment statement on line 648:

648: timestamp_capture_ce <= '1' when (mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1')
Count: 12979
Threshold: 1

Signal assignment statement on line 650:

650:                            '1' when (mr_rx_settings_rtsop = RTS_BEG and sof_pulse = '1')

Count: 15
Threshold: 1

Signal assignment statement on line 652:

652:                            '1' when (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1')

Count: 338
Threshold: 1

Signal assignment statement on line 654:

654: '0';
Count: 243007
Threshold: 1

If statement on lines 658 to 664:

658:        if (rst_n = '0') then 
659:            timestamp_capture <= (others => '0'); 
...
663:            end if; 
664:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 659:

659: timestamp_capture <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 661 to 663:

661:            if (timestamp_capture_ce = '1') then 
662:                timestamp_capture   <= timestamp; 
663:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 662:

662: timestamp_capture <= timestamp;
Count: 13327
Threshold: 1

If statement on lines 679 to 681:

679:    read_counter_d <= read_counter_q - 1 when (read_counter_q > "00000") 
680:                                         else 
681:                      unsigned(rxb_port_b_data_out_i(RWCNT_H downto RWCNT_L));

Count: 155756
Threshold: 1

Signal assignment statement on line 679:

679: read_counter_d <= read_counter_q - 1 when (read_counter_q > "00000")
Count: 78111
Threshold: 1

Signal assignment statement on line 681:

681: unsigned(rxb_port_b_data_out_i(RWCNT_H downto RWCNT_L));
Count: 77645
Threshold: 1

If statement on lines 685 to 693:

685:        if (rx_buf_rst_n_q_scan = '0') then 
686:            read_counter_q <= (others => '0'); 
...
692:            end if; 
693:        end if;

Count: 1096782032
Threshold: 1

Signal assignment statement on line 686:

686: read_counter_q <= (others => '0');
Count: 2436708
Threshold: 1

If statement on lines 690 to 692:

690:            if (read_increment = '1') then 
691:                read_counter_q <= read_counter_d; 
692:            end if;

Count: 547167495
Threshold: 1

Signal assignment statement on line 691:

691: read_counter_q <= read_counter_d;
Count: 50920
Threshold: 1

If statement on lines 704 to 719:

704:        if (rx_buf_rst_n_q_scan = '0') then 
705:            frame_count <= (others => '0'); 
...
718: 
719:        end if;

Count: 1096782032
Threshold: 1

Signal assignment statement on line 705:

705: frame_count <= (others => '0');
Count: 2436708
Threshold: 1

If statement on lines 709 to 717:

709:            if ((read_increment = '1') and (read_counter_q = "00001")) then 
710:                if (commit_rx_frame = '0') then 
...
716:                frame_count <= frame_count + 1; 
717:            end if;

Count: 547167495
Threshold: 1

If statement on lines 710 to 712:

710:                if (commit_rx_frame = '0') then 
711:                    frame_count <= frame_count - 1; 
712:                end if;

Count: 9258
Threshold: 1

Signal assignment statement on line 711:

711: frame_count <= frame_count - 1;
Count: 9251
Threshold: 1

Signal assignment statement on line 716:

716: frame_count <= frame_count + 1;
Count: 13276
Threshold: 1

If statement on lines 729 to 746:

729:        if (rx_buf_rst_n_q_scan = '0') then 
730:            commit_rx_frame       <= '0'; 
...
745: 
746:        end if;

Count: 1096782032
Threshold: 1

Signal assignment statement on line 730:

730: commit_rx_frame <= '0';
Count: 2436708
Threshold: 1

Signal assignment statement on line 731:

731: commit_overrun_abort <= '0';
Count: 2436708
Threshold: 1

If statement on lines 735 to 744:

735:            if (commit_intent = '1') then 
736:                if (data_overrun_i = '0') then 
...
743:                commit_overrun_abort <= '0'; 
744:            end if;

Count: 547167495
Threshold: 1

If statement on lines 736 to 740:

736:                if (data_overrun_i = '0') then 
737:                    commit_rx_frame <= '1'; 
738:                else 
739:                    commit_overrun_abort <= '1'; 
740:                end if;

Count: 13327
Threshold: 1

Signal assignment statement on line 737:

737: commit_rx_frame <= '1';
Count: 13283
Threshold: 1

Signal assignment statement on line 739:

739: commit_overrun_abort <= '1';
Count: 44
Threshold: 1

Signal assignment statement on line 742:

742: commit_rx_frame <= '0';
Count: 547154168
Threshold: 1

Signal assignment statement on line 743:

743: commit_overrun_abort <= '0';
Count: 547154168
Threshold: 1

If statement on lines 757 to 770:

757:        if (rx_buf_rst_n_q_scan = '0') then 
758:            data_overrun_flg <= '0'; 
...
769: 
770:        end if;

Count: 1096782032
Threshold: 1

Signal assignment statement on line 758:

758: data_overrun_flg <= '0';
Count: 2436708
Threshold: 1

If statement on lines 762 to 768:

762:            if (mr_command_cdo = '1') then 
763:                data_overrun_flg <= '0'; 
...
767:                data_overrun_flg <= data_overrun_flg; 
768:            end if;

Count: 547167495
Threshold: 1

Signal assignment statement on line 763:

763: data_overrun_flg <= '0';
Count: 20
Threshold: 1

Signal assignment statement on line 765:

765: data_overrun_flg <= '1';
Count: 145
Threshold: 1

Signal assignment statement on line 767:

767: data_overrun_flg <= data_overrun_flg;
Count: 547167330
Threshold: 1

If statement on lines 789 to 799:

789:        if (rst_n = '0') then 
790:            data_overrun_i <= '0'; 
...
798:            end if; 
799:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 790:

790: data_overrun_i <= '0';
Count: 2422674
Threshold: 1

If statement on lines 792 to 798:

792:            if (overrun_condition = '1' or mr_command_rrb = '1') then 
793:                data_overrun_i <= '1'; 
...
797:                data_overrun_i <= data_overrun_i; 
798:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 793:

793: data_overrun_i <= '1';
Count: 605
Threshold: 1

Signal assignment statement on line 795:

795: data_overrun_i <= '0';
Count: 439297453
Threshold: 1

Signal assignment statement on line 797:

797: data_overrun_i <= data_overrun_i;
Count: 107876276
Threshold: 1

If statement on lines 808 to 812:

808:    rx_buf_ram_clk_en <= '1' when (rxb_port_a_write = '1' or read_attempt = '1') 
809:                             else 
810:                         '1' when (mr_tst_control_tmaena = '1') 
811:                             else 
812:                         '0';

Count: 411152
Threshold: 1

Signal assignment statement on line 808:

808: rx_buf_ram_clk_en <= '1' when (rxb_port_a_write = '1' or read_attempt = '1')
Count: 176515
Threshold: 1

Signal assignment statement on line 810:

810: '1' when (mr_tst_control_tmaena = '1')
Count: 648
Threshold: 1

Signal assignment statement on line 812:

812: '0';
Count: 233989
Threshold: 1

If statement on lines 864 to 867:

864:    rxb_port_a_write  <= '1' when (write_raw_OK = '1' or 
865:                                  (select_ts_wptr = '1' and data_overrun_i = '0')) 
866:                             else 
867:                         '0';

Count: 256443
Threshold: 1

Signal assignment statement on line 864:

864: rxb_port_a_write <= '1' when (write_raw_OK = '1' or
Count: 125279
Threshold: 1

Signal assignment statement on line 867:

867: '0';
Count: 131164
Threshold: 1

If statement on lines 873 to 875:

873:    rxb_port_a_address   <= write_pointer_ts when (select_ts_wptr = '1') 
874:                                             else 
875:                           write_pointer_raw;

Count: 250733
Threshold: 1

Signal assignment statement on line 873:

873: rxb_port_a_address <= write_pointer_ts when (select_ts_wptr = '1')
Count: 25978
Threshold: 1

Signal assignment statement on line 875:

875: write_pointer_raw;
Count: 224755
Threshold: 1

If statement on lines 882 to 884:

882:    rxb_port_b_address <= read_pointer_inc_1 when (read_increment = '1') 
883:                                             else 
884:                                read_pointer;

Count: 206393
Threshold: 1

Signal assignment statement on line 882:

882: rxb_port_b_address <= read_pointer_inc_1 when (read_increment = '1')
Count: 145838
Threshold: 1

Signal assignment statement on line 884:

884: read_pointer;
Count: 60555
Threshold: 1

If statement on lines 890 to 892:

890:    rx_mof <= '0' when (read_counter_q = "00000") 
891:                  else 
892:              '1';

Count: 54122
Threshold: 1

Signal assignment statement on line 890:

890: rx_mof <= '0' when (read_counter_q = "00000")
Count: 10859
Threshold: 1

Signal assignment statement on line 892:

892: '1';
Count: 43263
Threshold: 1

If statement on lines 901 to 910:

901:        if (rst_n = '0') then 
902:            rx_parity_error <= '0'; 
...
909:            end if; 
910:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 902:

902: rx_parity_error <= '0';
Count: 2422674
Threshold: 1

If statement on lines 904 to 909:

904:            if (mr_rx_data_read = '1' and rx_parity_mismatch_comb = '1' and mr_settings_pchke = '1') 
905:            then 
906:                rx_parity_error <= '1'; 
907:            elsif (mr_command_crxpe = '1') then 
908:                rx_parity_error <= '0'; 
909:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 906:

906: rx_parity_error <= '1';
Count: 13
Threshold: 1

Signal assignment statement on line 908:

908: rx_parity_error <= '0';
Count: 40
Threshold: 1

Signal assignment statement on line 917:

917: rx_read_pointer <= read_pointer;
Count: 54937
Threshold: 1

Signal assignment statement on line 918:

918: rx_write_pointer <= write_pointer;
Count: 17651
Threshold: 1

Signal assignment statement on line 919:

919: rx_data_overrun <= data_overrun_flg;
Count: 3264
Threshold: 1

If statement on lines 921 to 923:

921:    rx_empty_i       <= '1' when (frame_count = 0) 
922:                            else 
923:                        '0';

Count: 26156
Threshold: 1

Signal assignment statement on line 921:

921: rx_empty_i <= '1' when (frame_count = 0)
Count: 8950
Threshold: 1

Signal assignment statement on line 923:

923: '0';
Count: 17206
Threshold: 1

If statement on lines 925 to 927:

925:    rx_full          <= '1' when (rx_mem_free_i = C_RX_BUF_MEM_FREE_ZEROES) 
926:                            else 
927:                        '0';

Count: 67808
Threshold: 1

Signal assignment statement on line 925:

925: rx_full <= '1' when (rx_mem_free_i = C_RX_BUF_MEM_FREE_ZEROES)
Count: 20
Threshold: 1

Signal assignment statement on line 927:

927: '0';
Count: 67788
Threshold: 1

Signal assignment statement on line 929:

929: rx_frame_count <= std_logic_vector(frame_count);
Count: 26156
Threshold: 1

Signal assignment statement on line 930:

930: rx_mem_free <= rx_mem_free_i;
Count: 67808
Threshold: 1

Signal assignment statement on line 931:

931: rx_empty <= rx_empty_i;
Count: 19503
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 436:

436: rx_buf_rst_n_d <= '0' when (mr_command_rrb = '1' or rst_n = '0')

	Evaluated to	Count	Threshold
Bin	True	8532	1
Bin	False	14212	1

"case" / "with" / "select" choice on line 518:

518: "0000" & frame_form_w when "00001",

	Choice of	Count	Threshold
Bin	`"00001"`	27015	1

"case" / "with" / "select" choice on line 519:

519: "000" & rec_ident when "00010",

	Choice of	Count	Threshold
Bin	`"00010"`	27006	1

"case" / "with" / "select" choice on line 520:

520: store_data_word when "00100",

	Choice of	Count	Threshold
Bin	`"00100"`	2997320	1

"case" / "with" / "select" choice on line 521:

521: timestamp_capture(31 downto 0) when "01000",

	Choice of	Count	Threshold
Bin	`"01000"`	13327	1

"case" / "with" / "select" choice on line 522:

522: timestamp_capture(63 downto 32) when "10000",

	Choice of	Count	Threshold
Bin	`"10000"`	13327	1

"case" / "with" / "select" choice on line 523:

523: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	3371652	1

"if" / "when" / "else" condition on line 528:

528: read_attempt <= mr_rx_data_read when (mr_mode_rxbam = RXBAM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	157358	1
Bin	False	5292	1

"if" / "when" / "else" condition on line 532:

532: read_increment <= '1' when (read_attempt = '1' and rx_empty_i = '0')

	Evaluated to	Count	Threshold
Bin	True	50920	1
Bin	False	123078	1

"if" / "when" / "else" condition on lines 540 to 541:

540:    write_raw_OK <= '1' when (write_raw_intent = '1' and overrun_condition = '0' and 
541:                              data_overrun_i = '0')

	Evaluated to	Count	Threshold
Bin	True	112334	1
Bin	False	118255	1

"if" / "when" / "else" condition on line 552:

552: is_free_word <= '0' when (read_pointer = write_pointer_raw and frame_count > 0)

	Evaluated to	Count	Threshold
Bin	True	47	1
Bin	False	285252	1

"if" / "when" / "else" condition on line 563:

563: overrun_condition <= '1' when (write_raw_intent = '1' and is_free_word = '0')

	Evaluated to	Count	Threshold
Bin	True	45	1
Bin	False	227912	1

"if" / "when" / "else" condition on line 573:

573: rxb_port_b_data_out <= rxb_port_b_data_out_i when (rx_empty_i = '0')

	Evaluated to	Count	Threshold
Bin	True	50170	1
Bin	False	75269	1

"case" / "with" / "select" choice on line 582:

582: 3 when "0000", --Zero bits

	Choice of	Count	Threshold
Bin	`"0000"`	40058	1

"case" / "with" / "select" choice on line 583:

583: 4 when "0001", --1 byte

	Choice of	Count	Threshold
Bin	`"0001"`	8658	1

"case" / "with" / "select" choice on line 584:

584: 4 when "0010", --2 bytes

	Choice of	Count	Threshold
Bin	`"0010"`	2822	1

"case" / "with" / "select" choice on line 585:

585: 4 when "0011", --3 bytes

	Choice of	Count	Threshold
Bin	`"0011"`	1255	1

"case" / "with" / "select" choice on line 586:

586: 4 when "0100", --4 bytes

	Choice of	Count	Threshold
Bin	`"0100"`	1816	1

"case" / "with" / "select" choice on line 587:

587: 5 when "0101", --5 bytes

	Choice of	Count	Threshold
Bin	`"0101"`	1101	1

"case" / "with" / "select" choice on line 588:

588: 5 when "0110", --6 bytes

	Choice of	Count	Threshold
Bin	`"0110"`	1515	1

"case" / "with" / "select" choice on line 589:

589: 5 when "0111", --7 bytes

	Choice of	Count	Threshold
Bin	`"0111"`	1166	1

"case" / "with" / "select" choice on line 590:

590: 5 when "1000", --8 bytes

	Choice of	Count	Threshold
Bin	`"1000"`	3104	1

"case" / "with" / "select" choice on line 591:

591: 6 when "1001", --12 bytes

	Choice of	Count	Threshold
Bin	`"1001"`	435	1

"case" / "with" / "select" choice on line 592:

592: 7 when "1010", --16 bytes

	Choice of	Count	Threshold
Bin	`"1010"`	566	1

"case" / "with" / "select" choice on line 593:

593: 8 when "1011", --20 bytes

	Choice of	Count	Threshold
Bin	`"1011"`	352	1

"case" / "with" / "select" choice on line 594:

594: 9 when "1100", --24 bytes

	Choice of	Count	Threshold
Bin	`"1100"`	1099	1

"case" / "with" / "select" choice on line 595:

595: 11 when "1101", --32 bytes

	Choice of	Count	Threshold
Bin	`"1101"`	723	1

"case" / "with" / "select" choice on line 596:

596: 15 when "1110", --48 bytes

	Choice of	Count	Threshold
Bin	`"1110"`	581	1

"case" / "with" / "select" choice on line 597:

597: 19 when others; --64 bytes

	Choice of	Count	Threshold
Bin	`others`	14872	1

"if" / "when" / "else" condition on line 620:

620: "00011" when (rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED) else

	Evaluated to	Count	Threshold
Bin	True	26263	1
Bin	False	176855	1

"if" / "when" / "else" condition on line 621:

621: "00101" when ((rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1')) else

	Evaluated to	Count	Threshold
Bin	True	6019	1
Bin	False	170836	1

"if" / "when" / "else" condition on line 625:

625: frame_form_w(ERF_POS_H downto ERF_POS_L) <= err_capt_err_pos when (rec_erf = '1')

	Evaluated to	Count	Threshold
Bin	True	338	1
Bin	False	13974	1

"if" / "when" / "else" condition on line 629:

629: frame_form_w(ERF_TYPE_H downto ERF_TYPE_L) <= err_capt_err_type when (rec_erf = '1')

	Evaluated to	Count	Threshold
Bin	True	338	1
Bin	False	9000	1

"if" / "when" / "else" condition on line 633:

633: frame_form_w(ERF_ERP_IND) <= err_capt_err_erp when (rec_erf = '1')

	Evaluated to	Count	Threshold
Bin	True	338	1
Bin	False	5731	1

"if" / "when" / "else" condition on line 638:

638: frame_form_w(LBTBI_H downto LBTBI_L) <= curr_txtb_index when (rec_lbpf = LBPF_LOOPBACK)

	Evaluated to	Count	Threshold
Bin	True	350	1
Bin	False	17099	1

"if" / "when" / "else" condition on line 648:

648: timestamp_capture_ce <= '1' when (mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1')

	Evaluated to	Count	Threshold
Bin	True	12979	1
Bin	False	243360	1

"if" / "when" / "else" condition on line 650:

650:                            '1' when (mr_rx_settings_rtsop = RTS_BEG and sof_pulse = '1')

	Evaluated to	Count	Threshold
Bin	True	15	1
Bin	False	243345	1

"if" / "when" / "else" condition on line 652:

652:                            '1' when (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1')

	Evaluated to	Count	Threshold
Bin	True	338	1
Bin	False	243007	1

"if" / "when" / "else" condition on line 658:

658: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 660:

660: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 661:

661: if (timestamp_capture_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	13327	1
Bin	False	547161007	1

"if" / "when" / "else" condition on line 679:

679: read_counter_d <= read_counter_q - 1 when (read_counter_q > "00000")

	Evaluated to	Count	Threshold
Bin	True	78111	1
Bin	False	77645	1

"if" / "when" / "else" condition on line 685:

685: if (rx_buf_rst_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2436708	1
Bin	False	1094345324	1

"if" / "when" / "else" condition on line 687:

687: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547167495	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 690:

690: if (read_increment = '1') then

	Evaluated to	Count	Threshold
Bin	True	50920	1
Bin	False	547116575	1

"if" / "when" / "else" condition on line 704:

704: if (rx_buf_rst_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2436708	1
Bin	False	1094345324	1

"if" / "when" / "else" condition on line 706:

706: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547167495	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 709:

709: if ((read_increment = '1') and (read_counter_q = "00001")) then

	Evaluated to	Count	Threshold
Bin	True	9258	1
Bin	False	547158237	1

"if" / "when" / "else" condition on line 710:

710: if (commit_rx_frame = '0') then

	Evaluated to	Count	Threshold
Bin	True	9251	1
Bin	False	7	1

"if" / "when" / "else" condition on line 715:

715: elsif (commit_rx_frame = '1') then

	Evaluated to	Count	Threshold
Bin	True	13276	1
Bin	False	547144961	1

"if" / "when" / "else" condition on line 729:

729: if (rx_buf_rst_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2436708	1
Bin	False	1094345324	1

"if" / "when" / "else" condition on line 733:

733: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547167495	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 735:

735: if (commit_intent = '1') then

	Evaluated to	Count	Threshold
Bin	True	13327	1
Bin	False	547154168	1

"if" / "when" / "else" condition on line 736:

736: if (data_overrun_i = '0') then

	Evaluated to	Count	Threshold
Bin	True	13283	1
Bin	False	44	1

"if" / "when" / "else" condition on line 757:

757: if (rx_buf_rst_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2436708	1
Bin	False	1094345324	1

"if" / "when" / "else" condition on line 759:

759: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547167495	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 762:

762: if (mr_command_cdo = '1') then

	Evaluated to	Count	Threshold
Bin	True	20	1
Bin	False	547167475	1

"if" / "when" / "else" condition on line 764:

764: elsif (overrun_condition = '1') then

	Evaluated to	Count	Threshold
Bin	True	145	1
Bin	False	547167330	1

"if" / "when" / "else" condition on line 789:

789: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 791:

791: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 792:

792: if (overrun_condition = '1' or mr_command_rrb = '1') then

	Evaluated to	Count	Threshold
Bin	True	605	1
Bin	False	547173729	1

"if" / "when" / "else" condition on line 794:

794: elsif (reset_overrun_flag = '1') then

	Evaluated to	Count	Threshold
Bin	True	439297453	1
Bin	False	107876276	1

"if" / "when" / "else" condition on line 808:

808: rx_buf_ram_clk_en <= '1' when (rxb_port_a_write = '1' or read_attempt = '1')

	Evaluated to	Count	Threshold
Bin	True	176515	1
Bin	False	234637	1

"if" / "when" / "else" condition on line 810:

810: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	648	1
Bin	False	233989	1

"if" / "when" / "else" condition on lines 864 to 865:

864:    rxb_port_a_write  <= '1' when (write_raw_OK = '1' or 
865:                                  (select_ts_wptr = '1' and data_overrun_i = '0'))

	Evaluated to	Count	Threshold
Bin	True	125279	1
Bin	False	131164	1

"if" / "when" / "else" condition on line 873:

873: rxb_port_a_address <= write_pointer_ts when (select_ts_wptr = '1')

	Evaluated to	Count	Threshold
Bin	True	25978	1
Bin	False	224755	1

"if" / "when" / "else" condition on line 882:

882: rxb_port_b_address <= read_pointer_inc_1 when (read_increment = '1')

	Evaluated to	Count	Threshold
Bin	True	145838	1
Bin	False	60555	1

"if" / "when" / "else" condition on line 890:

890: rx_mof <= '0' when (read_counter_q = "00000")

	Evaluated to	Count	Threshold
Bin	True	10859	1
Bin	False	43263	1

"if" / "when" / "else" condition on line 901:

901: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 903:

903: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 904:

904:            if (mr_rx_data_read = '1' and rx_parity_mismatch_comb = '1' and mr_settings_pchke = '1')

	Evaluated to	Count	Threshold
Bin	True	13	1
Bin	False	547174321	1

"if" / "when" / "else" condition on line 907:

907: elsif (mr_command_crxpe = '1') then

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	547174281	1

"if" / "when" / "else" condition on line 921:

921: rx_empty_i <= '1' when (frame_count = 0)

	Evaluated to	Count	Threshold
Bin	True	8950	1
Bin	False	17206	1

"if" / "when" / "else" condition on line 925:

925: rx_full <= '1' when (rx_mem_free_i = C_RX_BUF_MEM_FREE_ZEROES)

	Evaluated to	Count	Threshold
Bin	True	20	1
Bin	False	67788	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_IDENT

	Element	From	To	Threshold	Excluded due to
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

REC_DLC

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

REC_IDENT_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_FRAME_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_LBPF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_IS_RTR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_BRS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_ESI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_IVLD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_METADATA_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_DATA_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_DATA_WORD

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

REC_VALID_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_ABORT_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SOF_PULSE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_CAPT_ERR_TYPE

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ERR_CAPT_ERR_POS

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ERR_CAPT_ERR_ERP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TIMESTAMP

	Element	From	To	Threshold	Excluded due to
Bin	(63)	0	1	1	Exclude file
Bin	(63)	1	0	1	Exclude file
Bin	(62)	0	1	1	Exclude file
Bin	(62)	1	0	1	Exclude file
Bin	(61)	0	1	1	Exclude file
Bin	(61)	1	0	1	Exclude file
Bin	(60)	0	1	1	Exclude file
Bin	(60)	1	0	1	Exclude file
Bin	(59)	0	1	1	Exclude file
Bin	(59)	1	0	1	Exclude file
Bin	(58)	0	1	1	Exclude file
Bin	(58)	1	0	1	Exclude file
Bin	(57)	0	1	1	Exclude file
Bin	(57)	1	0	1	Exclude file
Bin	(56)	0	1	1	Exclude file
Bin	(56)	1	0	1	Exclude file
Bin	(55)	0	1	1	Exclude file
Bin	(55)	1	0	1	Exclude file
Bin	(54)	0	1	1	Exclude file
Bin	(54)	1	0	1	Exclude file
Bin	(53)	0	1	1	Exclude file
Bin	(53)	1	0	1	Exclude file
Bin	(52)	0	1	1	Exclude file
Bin	(52)	1	0	1	Exclude file
Bin	(51)	0	1	1	Exclude file
Bin	(51)	1	0	1	Exclude file
Bin	(50)	0	1	1	Exclude file
Bin	(50)	1	0	1	Exclude file
Bin	(49)	0	1	1	Exclude file
Bin	(49)	1	0	1	Exclude file
Bin	(48)	0	1	1	Exclude file
Bin	(48)	1	0	1	Exclude file
Bin	(47)	0	1	1	Exclude file
Bin	(47)	1	0	1	Exclude file
Bin	(46)	0	1	1	Exclude file
Bin	(46)	1	0	1	Exclude file
Bin	(45)	0	1	1	Exclude file
Bin	(45)	1	0	1	Exclude file
Bin	(44)	0	1	1	Exclude file
Bin	(44)	1	0	1	Exclude file
Bin	(43)	0	1	1	Exclude file
Bin	(43)	1	0	1	Exclude file
Bin	(42)	0	1	1	Exclude file
Bin	(42)	1	0	1	Exclude file
Bin	(41)	0	1	1	Exclude file
Bin	(41)	1	0	1	Exclude file
Bin	(40)	0	1	1	Exclude file
Bin	(40)	1	0	1	Exclude file
Bin	(39)	0	1	1	Exclude file
Bin	(39)	1	0	1	Exclude file
Bin	(38)	0	1	1	Exclude file
Bin	(38)	1	0	1	Exclude file
Bin	(37)	0	1	1	Exclude file
Bin	(37)	1	0	1	Exclude file
Bin	(36)	0	1	1	Exclude file
Bin	(36)	1	0	1	Exclude file
Bin	(35)	0	1	1	Exclude file
Bin	(35)	1	0	1	Exclude file
Bin	(34)	0	1	1	Exclude file
Bin	(34)	1	0	1	Exclude file
Bin	(33)	0	1	1	Exclude file
Bin	(33)	1	0	1	Exclude file
Bin	(32)	0	1	1	Exclude file
Bin	(32)	1	0	1	Exclude file
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CURR_TXTB_INDEX

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_MODE_RXBAM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_CDO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_CRXPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_RRB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_RXRPMV

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_RX_DATA_READ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_RX_SETTINGS_RTSOP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ERFM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

RX_FULL

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1621	1

Port:

RX_EMPTY

	From	To	Count	Threshold
Bin	0	1	8950	1
Bin	1	0	8952	1

Port:

RX_FRAME_COUNT

	Element	From	To	Count	Threshold
Bin	(10)	0	1	4	1
Bin	(10)	1	0	169	1
Bin	(9)	0	1	5	1
Bin	(9)	1	0	170	1
Bin	(8)	0	1	10	1
Bin	(8)	1	0	175	1
Bin	(7)	0	1	21	1
Bin	(7)	1	0	186	1
Bin	(6)	0	1	43	1
Bin	(6)	1	0	208	1
Bin	(5)	0	1	98	1
Bin	(5)	1	0	758	1
Bin	(4)	0	1	195	1
Bin	(4)	1	0	855	1
Bin	(3)	0	1	403	1
Bin	(3)	1	0	2004	1
Bin	(2)	0	1	843	1
Bin	(2)	1	0	2444	1
Bin	(1)	0	1	2528	1
Bin	(1)	1	0	4129	1
Bin	(0)	0	1	11398	1
Bin	(0)	1	0	12997	1

Port:

RX_MEM_FREE

	Element	From	To	Count	Threshold
Bin	(12)	0	1	1206	1
Bin	(12)	1	0	1041	1
Bin	(11)	0	1	1043	1
Bin	(11)	1	0	1208	1
Bin	(10)	0	1	1050	1
Bin	(10)	1	0	1215	1
Bin	(9)	0	1	1064	1
Bin	(9)	1	0	1229	1
Bin	(8)	0	1	1092	1
Bin	(8)	1	0	1257	1
Bin	(7)	0	1	4484	1
Bin	(7)	1	0	4154	1
Bin	(6)	0	1	4111	1
Bin	(6)	1	0	4771	1
Bin	(5)	0	1	8775	1
Bin	(5)	1	0	8496	1
Bin	(4)	0	1	8358	1
Bin	(4)	1	0	9957	1
Bin	(3)	0	1	9825	1
Bin	(3)	1	0	11424	1
Bin	(2)	0	1	12159	1
Bin	(2)	1	0	13758	1
Bin	(1)	0	1	15624	1
Bin	(1)	1	0	17225	1
Bin	(0)	0	1	26860	1
Bin	(0)	1	0	28461	1

Port:

RX_READ_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	3	1
Bin	(11)	1	0	168	1
Bin	(10)	0	1	5	1
Bin	(10)	1	0	170	1
Bin	(9)	0	1	11	1
Bin	(9)	1	0	176	1
Bin	(8)	0	1	22	1
Bin	(8)	1	0	187	1
Bin	(7)	0	1	43	1
Bin	(7)	1	0	208	1
Bin	(6)	0	1	198	1
Bin	(6)	1	0	858	1
Bin	(5)	0	1	431	1
Bin	(5)	1	0	1091	1
Bin	(4)	0	1	1555	1
Bin	(4)	1	0	3156	1
Bin	(3)	0	1	3134	1
Bin	(3)	1	0	4735	1
Bin	(2)	0	1	6538	1
Bin	(2)	1	0	8139	1
Bin	(1)	0	1	12798	1
Bin	(1)	1	0	14399	1
Bin	(0)	0	1	25602	1
Bin	(0)	1	0	27203	1

Port:

RX_WRITE_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	6	1
Bin	(11)	1	0	171	1
Bin	(10)	0	1	11	1
Bin	(10)	1	0	176	1
Bin	(9)	0	1	23	1
Bin	(9)	1	0	188	1
Bin	(8)	0	1	46	1
Bin	(8)	1	0	211	1
Bin	(7)	0	1	91	1
Bin	(7)	1	0	256	1
Bin	(6)	0	1	304	1
Bin	(6)	1	0	964	1
Bin	(5)	0	1	663	1
Bin	(5)	1	0	1323	1
Bin	(4)	0	1	1946	1
Bin	(4)	1	0	3547	1
Bin	(3)	0	1	3727	1
Bin	(3)	1	0	5328	1
Bin	(2)	0	1	6176	1
Bin	(2)	1	0	7775	1
Bin	(1)	0	1	1742	1
Bin	(1)	1	0	3343	1
Bin	(0)	0	1	1540	1
Bin	(0)	1	0	3141	1

Port:

RX_DATA_OVERRUN

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	1632	1

Port:

RX_MOF

	From	To	Count	Threshold
Bin	0	1	10859	1
Bin	1	0	10859	1

Port:

RX_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	13	1
Bin	1	0	1614	1

Port:

RXB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	3128	1
Bin	(31)	1	0	6330	1
Bin	(30)	0	1	3405	1
Bin	(30)	1	0	6607	1
Bin	(29)	0	1	3235	1
Bin	(29)	1	0	6437	1
Bin	(28)	0	1	7281	1
Bin	(28)	1	0	10483	1
Bin	(27)	0	1	7210	1
Bin	(27)	1	0	10412	1
Bin	(26)	0	1	6752	1
Bin	(26)	1	0	9954	1
Bin	(25)	0	1	6614	1
Bin	(25)	1	0	9816	1
Bin	(24)	0	1	12777	1
Bin	(24)	1	0	15977	1
Bin	(23)	0	1	6836	1
Bin	(23)	1	0	10038	1
Bin	(22)	0	1	7147	1
Bin	(22)	1	0	10349	1
Bin	(21)	0	1	7197	1
Bin	(21)	1	0	10399	1
Bin	(20)	0	1	7293	1
Bin	(20)	1	0	10495	1
Bin	(19)	0	1	8608	1
Bin	(19)	1	0	11810	1
Bin	(18)	0	1	9052	1
Bin	(18)	1	0	12254	1
Bin	(17)	0	1	7834	1
Bin	(17)	1	0	11036	1
Bin	(16)	0	1	8071	1
Bin	(16)	1	0	11273	1
Bin	(15)	0	1	8310	1
Bin	(15)	1	0	11512	1
Bin	(14)	0	1	9553	1
Bin	(14)	1	0	12755	1
Bin	(13)	0	1	12231	1
Bin	(13)	1	0	15433	1
Bin	(12)	0	1	13751	1
Bin	(12)	1	0	16951	1
Bin	(11)	0	1	15302	1
Bin	(11)	1	0	18502	1
Bin	(10)	0	1	9846	1
Bin	(10)	1	0	13048	1
Bin	(9)	0	1	11261	1
Bin	(9)	1	0	14463	1
Bin	(8)	0	1	9793	1
Bin	(8)	1	0	12995	1
Bin	(7)	0	1	12942	1
Bin	(7)	1	0	16144	1
Bin	(6)	0	1	11665	1
Bin	(6)	1	0	14867	1
Bin	(5)	0	1	12281	1
Bin	(5)	1	0	15483	1
Bin	(4)	0	1	9731	1
Bin	(4)	1	0	12933	1
Bin	(3)	0	1	10763	1
Bin	(3)	1	0	13965	1
Bin	(2)	0	1	11082	1
Bin	(2)	1	0	14284	1
Bin	(1)	0	1	11748	1
Bin	(1)	1	0	14950	1
Bin	(0)	0	1	11917	1
Bin	(0)	1	0	15119	1

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	21399	1
Bin	(31)	1	0	18493	1
Bin	(30)	0	1	12499	1
Bin	(30)	1	0	18612	1
Bin	(29)	0	1	16902	1
Bin	(29)	1	0	13996	1
Bin	(28)	0	1	17082	1
Bin	(28)	1	0	23195	1
Bin	(27)	0	1	17015	1
Bin	(27)	1	0	14109	1
Bin	(26)	0	1	16993	1
Bin	(26)	1	0	23106	1
Bin	(25)	0	1	21615	1
Bin	(25)	1	0	18709	1
Bin	(24)	0	1	12394	1
Bin	(24)	1	0	18507	1
Bin	(23)	0	1	21421	1
Bin	(23)	1	0	18515	1
Bin	(22)	0	1	12559	1
Bin	(22)	1	0	18672	1
Bin	(21)	0	1	16960	1
Bin	(21)	1	0	14054	1
Bin	(20)	0	1	17078	1
Bin	(20)	1	0	23191	1
Bin	(19)	0	1	17010	1
Bin	(19)	1	0	14104	1
Bin	(18)	0	1	16966	1
Bin	(18)	1	0	23079	1
Bin	(17)	0	1	21592	1
Bin	(17)	1	0	18686	1
Bin	(16)	0	1	12366	1
Bin	(16)	1	0	18479	1
Bin	(15)	0	1	21426	1
Bin	(15)	1	0	18520	1
Bin	(14)	0	1	12538	1
Bin	(14)	1	0	18651	1
Bin	(13)	0	1	16985	1
Bin	(13)	1	0	14079	1
Bin	(12)	0	1	17133	1
Bin	(12)	1	0	23246	1
Bin	(11)	0	1	17035	1
Bin	(11)	1	0	14129	1
Bin	(10)	0	1	16976	1
Bin	(10)	1	0	23089	1
Bin	(9)	0	1	21642	1
Bin	(9)	1	0	18736	1
Bin	(8)	0	1	12374	1
Bin	(8)	1	0	18487	1
Bin	(7)	0	1	21491	1
Bin	(7)	1	0	18585	1
Bin	(6)	0	1	12603	1
Bin	(6)	1	0	18716	1
Bin	(5)	0	1	16973	1
Bin	(5)	1	0	14067	1
Bin	(4)	0	1	17089	1
Bin	(4)	1	0	23202	1
Bin	(3)	0	1	17026	1
Bin	(3)	1	0	14120	1
Bin	(2)	0	1	16994	1
Bin	(2)	1	0	23107	1
Bin	(1)	0	1	21633	1
Bin	(1)	1	0	18727	1
Bin	(0)	0	1	12422	1
Bin	(0)	1	0	18535	1

Signal:

READ_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	3	1
Bin	(11)	1	0	168	1
Bin	(10)	0	1	5	1
Bin	(10)	1	0	170	1
Bin	(9)	0	1	11	1
Bin	(9)	1	0	176	1
Bin	(8)	0	1	22	1
Bin	(8)	1	0	187	1
Bin	(7)	0	1	43	1
Bin	(7)	1	0	208	1
Bin	(6)	0	1	198	1
Bin	(6)	1	0	858	1
Bin	(5)	0	1	431	1
Bin	(5)	1	0	1091	1
Bin	(4)	0	1	1555	1
Bin	(4)	1	0	3156	1
Bin	(3)	0	1	3134	1
Bin	(3)	1	0	4735	1
Bin	(2)	0	1	6538	1
Bin	(2)	1	0	8139	1
Bin	(1)	0	1	12798	1
Bin	(1)	1	0	14399	1
Bin	(0)	0	1	25602	1
Bin	(0)	1	0	27203	1

Signal:

READ_POINTER_INC_1

	Element	From	To	Count	Threshold
Bin	(11)	0	1	3	1
Bin	(11)	1	0	168	1
Bin	(10)	0	1	5	1
Bin	(10)	1	0	170	1
Bin	(9)	0	1	11	1
Bin	(9)	1	0	176	1
Bin	(8)	0	1	22	1
Bin	(8)	1	0	187	1
Bin	(7)	0	1	43	1
Bin	(7)	1	0	208	1
Bin	(6)	0	1	198	1
Bin	(6)	1	0	858	1
Bin	(5)	0	1	436	1
Bin	(5)	1	0	1096	1
Bin	(4)	0	1	1564	1
Bin	(4)	1	0	3165	1
Bin	(3)	0	1	3157	1
Bin	(3)	1	0	4758	1
Bin	(2)	0	1	6576	1
Bin	(2)	1	0	8177	1
Bin	(1)	0	1	12996	1
Bin	(1)	1	0	14597	1
Bin	(0)	0	1	27203	1
Bin	(0)	1	0	25602	1

Signal:

WRITE_POINTER

	Element	From	To	Count	Threshold
Bin	(11)	0	1	6	1
Bin	(11)	1	0	171	1
Bin	(10)	0	1	11	1
Bin	(10)	1	0	176	1
Bin	(9)	0	1	23	1
Bin	(9)	1	0	188	1
Bin	(8)	0	1	46	1
Bin	(8)	1	0	211	1
Bin	(7)	0	1	91	1
Bin	(7)	1	0	256	1
Bin	(6)	0	1	304	1
Bin	(6)	1	0	964	1
Bin	(5)	0	1	663	1
Bin	(5)	1	0	1323	1
Bin	(4)	0	1	1946	1
Bin	(4)	1	0	3547	1
Bin	(3)	0	1	3727	1
Bin	(3)	1	0	5328	1
Bin	(2)	0	1	6176	1
Bin	(2)	1	0	7775	1
Bin	(1)	0	1	1742	1
Bin	(1)	1	0	3343	1
Bin	(0)	0	1	1540	1
Bin	(0)	1	0	3141	1

Signal:

WRITE_POINTER_RAW

	Element	From	To	Count	Threshold
Bin	(11)	0	1	7	1
Bin	(11)	1	0	172	1
Bin	(10)	0	1	12	1
Bin	(10)	1	0	177	1
Bin	(9)	0	1	25	1
Bin	(9)	1	0	190	1
Bin	(8)	0	1	49	1
Bin	(8)	1	0	214	1
Bin	(7)	0	1	96	1
Bin	(7)	1	0	261	1
Bin	(6)	0	1	344	1
Bin	(6)	1	0	1004	1
Bin	(5)	0	1	748	1
Bin	(5)	1	0	1408	1
Bin	(4)	0	1	4579	1
Bin	(4)	1	0	6180	1
Bin	(3)	0	1	11726	1
Bin	(3)	1	0	13327	1
Bin	(2)	0	1	26733	1
Bin	(2)	1	0	28332	1
Bin	(1)	0	1	49238	1
Bin	(1)	1	0	50839	1
Bin	(0)	0	1	98956	1
Bin	(0)	1	0	100557	1

Signal:

WRITE_POINTER_TS

	Element	From	To	Count	Threshold
Bin	(11)	0	1	6	1
Bin	(11)	1	0	171	1
Bin	(10)	0	1	11	1
Bin	(10)	1	0	176	1
Bin	(9)	0	1	23	1
Bin	(9)	1	0	188	1
Bin	(8)	0	1	46	1
Bin	(8)	1	0	211	1
Bin	(7)	0	1	91	1
Bin	(7)	1	0	256	1
Bin	(6)	0	1	296	1
Bin	(6)	1	0	956	1
Bin	(5)	0	1	637	1
Bin	(5)	1	0	1297	1
Bin	(4)	0	1	1862	1
Bin	(4)	1	0	3463	1
Bin	(3)	0	1	3581	1
Bin	(3)	1	0	5182	1
Bin	(2)	0	1	6156	1
Bin	(2)	1	0	7757	1
Bin	(1)	0	1	3648	1
Bin	(1)	1	0	5241	1
Bin	(0)	0	1	11716	1
Bin	(0)	1	0	13315	1

Signal:

RX_MEM_FREE_I

	Element	From	To	Count	Threshold
Bin	(12)	0	1	1206	1
Bin	(12)	1	0	1041	1
Bin	(11)	0	1	1043	1
Bin	(11)	1	0	1208	1
Bin	(10)	0	1	1050	1
Bin	(10)	1	0	1215	1
Bin	(9)	0	1	1064	1
Bin	(9)	1	0	1229	1
Bin	(8)	0	1	1092	1
Bin	(8)	1	0	1257	1
Bin	(7)	0	1	4484	1
Bin	(7)	1	0	4154	1
Bin	(6)	0	1	4111	1
Bin	(6)	1	0	4771	1
Bin	(5)	0	1	8775	1
Bin	(5)	1	0	8496	1
Bin	(4)	0	1	8358	1
Bin	(4)	1	0	9957	1
Bin	(3)	0	1	9825	1
Bin	(3)	1	0	11424	1
Bin	(2)	0	1	12159	1
Bin	(2)	1	0	13758	1
Bin	(1)	0	1	15624	1
Bin	(1)	1	0	17225	1
Bin	(0)	0	1	26860	1
Bin	(0)	1	0	28461	1

Signal:

DATA_OVERRUN_FLG

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	1632	1

Signal:

DATA_OVERRUN_I

	From	To	Count	Threshold
Bin	0	1	497	1
Bin	1	0	2098	1

Signal:

OVERRUN_CONDITION

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1646	1

Signal:

RX_EMPTY_I

	From	To	Count	Threshold
Bin	0	1	8950	1
Bin	1	0	8952	1

Signal:

IS_FREE_WORD

	From	To	Count	Threshold
Bin	0	1	1628	1
Bin	1	0	27	1

Signal:

FRAME_COUNT

	Element	From	To	Count	Threshold
Bin	(10)	0	1	4	1
Bin	(10)	1	0	169	1
Bin	(9)	0	1	5	1
Bin	(9)	1	0	170	1
Bin	(8)	0	1	10	1
Bin	(8)	1	0	175	1
Bin	(7)	0	1	21	1
Bin	(7)	1	0	186	1
Bin	(6)	0	1	43	1
Bin	(6)	1	0	208	1
Bin	(5)	0	1	98	1
Bin	(5)	1	0	758	1
Bin	(4)	0	1	195	1
Bin	(4)	1	0	855	1
Bin	(3)	0	1	403	1
Bin	(3)	1	0	2004	1
Bin	(2)	0	1	843	1
Bin	(2)	1	0	2444	1
Bin	(1)	0	1	2528	1
Bin	(1)	1	0	4129	1
Bin	(0)	0	1	11398	1
Bin	(0)	1	0	12997	1

Signal:

READ_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(4)	0	1	24447	1
Bin	(4)	1	0	21981	1
Bin	(3)	0	1	16142	1
Bin	(3)	1	0	22544	1
Bin	(2)	0	1	25077	1
Bin	(2)	1	0	20534	1
Bin	(1)	0	1	31252	1
Bin	(1)	1	0	36530	1
Bin	(0)	0	1	43901	1
Bin	(0)	1	0	39322	1

Signal:

READ_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(4)	0	1	286	1
Bin	(4)	1	0	1887	1
Bin	(3)	0	1	650	1
Bin	(3)	1	0	2251	1
Bin	(2)	0	1	5221	1
Bin	(2)	1	0	6822	1
Bin	(1)	0	1	11258	1
Bin	(1)	1	0	12859	1
Bin	(0)	0	1	24247	1
Bin	(0)	1	0	25848	1

Signal:

COMMIT_RX_FRAME

	From	To	Count	Threshold
Bin	0	1	13283	1
Bin	1	0	14884	1

Signal:

COMMIT_OVERRUN_ABORT

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1645	1

Signal:

READ_INCREMENT

	From	To	Count	Threshold
Bin	0	1	50920	1
Bin	1	0	52521	1

Signal:

WRITE_RAW_OK

	From	To	Count	Threshold
Bin	0	1	112334	1
Bin	1	0	113935	1

Signal:

WRITE_RAW_INTENT

	From	To	Count	Threshold
Bin	0	1	112351	1
Bin	1	0	113952	1

Signal:

SELECT_TS_WPTR

	From	To	Count	Threshold
Bin	0	1	12989	1
Bin	1	0	14590	1

Signal:

COMMIT_INTENT

	From	To	Count	Threshold
Bin	0	1	13327	1
Bin	1	0	14928	1

Signal:

DATA_SELECTOR

	Element	From	To	Count	Threshold
Bin	(4)	0	1	13327	1
Bin	(4)	1	0	14928	1
Bin	(3)	0	1	13327	1
Bin	(3)	1	0	14928	1
Bin	(2)	0	1	26330	1
Bin	(2)	1	0	27931	1
Bin	(1)	0	1	26668	1
Bin	(1)	1	0	28269	1
Bin	(0)	0	1	26672	1
Bin	(0)	1	0	28273	1

Signal:

STORE_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	26330	1
Bin	1	0	27931	1

Signal:

INC_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	12989	1
Bin	1	0	14590	1

Signal:

RESET_OVERRUN_FLAG

	From	To	Count	Threshold
Bin	0	1	28258	1
Bin	1	0	26657	1

Signal:

READ_ATTEMPT

	From	To	Count	Threshold
Bin	0	1	50950	1
Bin	1	0	52573	1

Signal:

REC_ERF

	From	To	Count	Threshold
Bin	0	1	338	1
Bin	1	0	1939	1

Signal:

FRAME_FORM_W

	Element	From	To	Count	Threshold
Bin	(27)	0	1	85	1
Bin	(27)	1	0	412696	1
Bin	(26)	0	1	548	1
Bin	(26)	1	0	416312	1
Bin	(25)	0	1	1415	1
Bin	(25)	1	0	417080	1
Bin	(24)	0	1	233447	1
Bin	(24)	1	0	180245	1
Bin	(23)	0	1	12	1
Bin	(23)	1	0	416912	1
Bin	(22)	0	1	128	1
Bin	(22)	1	0	418218	1
Bin	(21)	0	1	79	1
Bin	(21)	1	0	417440	1
Bin	(20)	0	1	34	1
Bin	(20)	1	0	418461	1
Bin	(19)	0	1	5	1
Bin	(19)	1	0	416168	1
Bin	(18)	0	1	217	1
Bin	(18)	1	0	417392	1
Bin	(17)	0	1	147	1
Bin	(17)	1	0	416863	1
Bin	(16)	0	1	278	1
Bin	(16)	1	0	417802	1
Bin	(15)	0	1	56280	1
Bin	(15)	1	0	120131	1
Bin	(14)	0	1	7504	1
Bin	(14)	1	0	21911	1
Bin	(13)	0	1	68734	1
Bin	(13)	1	0	153916	1
Bin	(12)	0	1	159590	1
Bin	(12)	1	0	69673	1
Bin	(11)	0	1	103655	1
Bin	(11)	1	0	44157	1
Bin	(10)	0	1	8534	1
Bin	(10)	1	0	403557	1
Bin	(9)	0	1	72986	1
Bin	(9)	1	0	339105	1
Bin	(8)	0	1	2639	1
Bin	(8)	1	0	411053	1
Bin	(7)	0	1	169089	1
Bin	(7)	1	0	239800	1
Bin	(6)	0	1	92350	1
Bin	(6)	1	0	319741	1
Bin	(5)	0	1	80268	1
Bin	(5)	1	0	335025	1
Bin	(4)	0	1	338	1
Bin	(4)	1	0	416556	1
Bin	(3)	0	1	68645	1
Bin	(3)	1	0	161227	1
Bin	(2)	0	1	74264	1
Bin	(2)	1	0	170491	1
Bin	(1)	0	1	74934	1
Bin	(1)	1	0	171867	1
Bin	(0)	0	1	90375	1
Bin	(0)	1	0	199463	1

Signal:

TIMESTAMP_CAPTURE

	Element	From	To	Count	Threshold
Bin	(63)	0	1	5	1
Bin	(63)	1	0	15633	1
Bin	(62)	0	1	59	1
Bin	(62)	1	0	15683	1
Bin	(61)	0	1	61	1
Bin	(61)	1	0	15685	1
Bin	(60)	0	1	59	1
Bin	(60)	1	0	15681	1
Bin	(59)	0	1	64	1
Bin	(59)	1	0	15686	1
Bin	(58)	0	1	74	1
Bin	(58)	1	0	15694	1
Bin	(57)	0	1	55	1
Bin	(57)	1	0	15679	1
Bin	(56)	0	1	70	1
Bin	(56)	1	0	15692	1
Bin	(55)	0	1	60	1
Bin	(55)	1	0	15682	1
Bin	(54)	0	1	51	1
Bin	(54)	1	0	15675	1
Bin	(53)	0	1	60	1
Bin	(53)	1	0	15686	1
Bin	(52)	0	1	58	1
Bin	(52)	1	0	15680	1
Bin	(51)	0	1	75	1
Bin	(51)	1	0	15695	1
Bin	(50)	0	1	59	1
Bin	(50)	1	0	15681	1
Bin	(49)	0	1	71	1
Bin	(49)	1	0	15693	1
Bin	(48)	0	1	70	1
Bin	(48)	1	0	15692	1
Bin	(47)	0	1	63	1
Bin	(47)	1	0	15687	1
Bin	(46)	0	1	67	1
Bin	(46)	1	0	15689	1
Bin	(45)	0	1	46	1
Bin	(45)	1	0	15674	1
Bin	(44)	0	1	60	1
Bin	(44)	1	0	15686	1
Bin	(43)	0	1	66	1
Bin	(43)	1	0	15690	1
Bin	(42)	0	1	65	1
Bin	(42)	1	0	15689	1
Bin	(41)	0	1	69	1
Bin	(41)	1	0	15691	1
Bin	(40)	0	1	63	1
Bin	(40)	1	0	15687	1
Bin	(39)	0	1	67	1
Bin	(39)	1	0	15693	1
Bin	(38)	0	1	66	1
Bin	(38)	1	0	15690	1
Bin	(37)	0	1	59	1
Bin	(37)	1	0	15681	1
Bin	(36)	0	1	58	1
Bin	(36)	1	0	15684	1
Bin	(35)	0	1	72	1
Bin	(35)	1	0	15692	1
Bin	(34)	0	1	64	1
Bin	(34)	1	0	15684	1
Bin	(33)	0	1	63	1
Bin	(33)	1	0	15683	1
Bin	(32)	0	1	60	1
Bin	(32)	1	0	15682	1
Bin	(31)	0	1	53	1
Bin	(31)	1	0	1654	1
Bin	(30)	0	1	56	1
Bin	(30)	1	0	1657	1
Bin	(29)	0	1	58	1
Bin	(29)	1	0	1659	1
Bin	(28)	0	1	53	1
Bin	(28)	1	0	1654	1
Bin	(27)	0	1	57	1
Bin	(27)	1	0	1658	1
Bin	(26)	0	1	63	1
Bin	(26)	1	0	1664	1
Bin	(25)	0	1	52	1
Bin	(25)	1	0	1653	1
Bin	(24)	0	1	64	1
Bin	(24)	1	0	1665	1
Bin	(23)	0	1	53	1
Bin	(23)	1	0	1654	1
Bin	(22)	0	1	50	1
Bin	(22)	1	0	1651	1
Bin	(21)	0	1	68	1
Bin	(21)	1	0	1669	1
Bin	(20)	0	1	71	1
Bin	(20)	1	0	1672	1
Bin	(19)	0	1	189	1
Bin	(19)	1	0	1790	1
Bin	(18)	0	1	240	1
Bin	(18)	1	0	1841	1
Bin	(17)	0	1	503	1
Bin	(17)	1	0	2104	1
Bin	(16)	0	1	850	1
Bin	(16)	1	0	2451	1
Bin	(15)	0	1	1009	1
Bin	(15)	1	0	2610	1
Bin	(14)	0	1	1410	1
Bin	(14)	1	0	3010	1
Bin	(13)	0	1	1716	1
Bin	(13)	1	0	3317	1
Bin	(12)	0	1	2224	1
Bin	(12)	1	0	3825	1
Bin	(11)	0	1	2883	1
Bin	(11)	1	0	4483	1
Bin	(10)	0	1	3668	1
Bin	(10)	1	0	5268	1
Bin	(9)	0	1	4626	1
Bin	(9)	1	0	6225	1
Bin	(8)	0	1	3070	1
Bin	(8)	1	0	4670	1
Bin	(7)	0	1	3894	1
Bin	(7)	1	0	5494	1
Bin	(6)	0	1	3759	1
Bin	(6)	1	0	5359	1
Bin	(5)	0	1	3316	1
Bin	(5)	1	0	4916	1
Bin	(4)	0	1	3584	1
Bin	(4)	1	0	5183	1
Bin	(3)	0	1	3054	1
Bin	(3)	1	0	4653	1
Bin	(2)	0	1	3833	1
Bin	(2)	1	0	5434	1
Bin	(1)	0	1	3174	1
Bin	(1)	1	0	4774	1
Bin	(0)	0	1	4956	1
Bin	(0)	1	0	6556	1

Signal:

TIMESTAMP_CAPTURE_CE

	From	To	Count	Threshold
Bin	0	1	13332	1
Bin	1	0	14933	1

Signal:

RXB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	125279	1
Bin	1	0	126880	1

Signal:

RXB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold
Bin	(11)	0	1	18	1
Bin	(11)	1	0	183	1
Bin	(10)	0	1	33	1
Bin	(10)	1	0	198	1
Bin	(9)	0	1	68	1
Bin	(9)	1	0	233	1
Bin	(8)	0	1	138	1
Bin	(8)	1	0	303	1
Bin	(7)	0	1	272	1
Bin	(7)	1	0	437	1
Bin	(6)	0	1	834	1
Bin	(6)	1	0	1494	1
Bin	(5)	0	1	1800	1
Bin	(5)	1	0	2460	1
Bin	(4)	0	1	7437	1
Bin	(4)	1	0	9038	1
Bin	(3)	0	1	17253	1
Bin	(3)	1	0	18854	1
Bin	(2)	0	1	37909	1
Bin	(2)	1	0	39508	1
Bin	(1)	0	1	60801	1
Bin	(1)	1	0	62402	1
Bin	(0)	0	1	111945	1
Bin	(0)	1	0	113546	1

Signal:

RXB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold
Bin	(31)	0	1	118633	1
Bin	(31)	1	0	120234	1
Bin	(30)	0	1	120259	1
Bin	(30)	1	0	121860	1
Bin	(29)	0	1	123335	1
Bin	(29)	1	0	124936	1
Bin	(28)	0	1	141710	1
Bin	(28)	1	0	143311	1
Bin	(27)	0	1	138405	1
Bin	(27)	1	0	140006	1
Bin	(26)	0	1	147626	1
Bin	(26)	1	0	149227	1
Bin	(25)	0	1	140224	1
Bin	(25)	1	0	141825	1
Bin	(24)	0	1	162870	1
Bin	(24)	1	0	164471	1
Bin	(23)	0	1	139442	1
Bin	(23)	1	0	141043	1
Bin	(22)	0	1	151074	1
Bin	(22)	1	0	152675	1
Bin	(21)	0	1	143735	1
Bin	(21)	1	0	145336	1
Bin	(20)	0	1	154110	1
Bin	(20)	1	0	155711	1
Bin	(19)	0	1	154601	1
Bin	(19)	1	0	156202	1
Bin	(18)	0	1	166930	1
Bin	(18)	1	0	168531	1
Bin	(17)	0	1	154379	1
Bin	(17)	1	0	155980	1
Bin	(16)	0	1	157651	1
Bin	(16)	1	0	159252	1
Bin	(15)	0	1	195166	1
Bin	(15)	1	0	196767	1
Bin	(14)	0	1	188980	1
Bin	(14)	1	0	190581	1
Bin	(13)	0	1	187057	1
Bin	(13)	1	0	188658	1
Bin	(12)	0	1	200345	1
Bin	(12)	1	0	201946	1
Bin	(11)	0	1	197296	1
Bin	(11)	1	0	198897	1
Bin	(10)	0	1	181043	1
Bin	(10)	1	0	182644	1
Bin	(9)	0	1	185507	1
Bin	(9)	1	0	187108	1
Bin	(8)	0	1	174805	1
Bin	(8)	1	0	176406	1
Bin	(7)	0	1	201286	1
Bin	(7)	1	0	202887	1
Bin	(6)	0	1	194132	1
Bin	(6)	1	0	195733	1
Bin	(5)	0	1	188521	1
Bin	(5)	1	0	190122	1
Bin	(4)	0	1	185375	1
Bin	(4)	1	0	186976	1
Bin	(3)	0	1	194767	1
Bin	(3)	1	0	196368	1
Bin	(2)	0	1	198029	1
Bin	(2)	1	0	199630	1
Bin	(1)	0	1	201564	1
Bin	(1)	1	0	203165	1
Bin	(0)	0	1	205565	1
Bin	(0)	1	0	207166	1

Signal:

RXB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold
Bin	(11)	0	1	7	1
Bin	(11)	1	0	172	1
Bin	(10)	0	1	14	1
Bin	(10)	1	0	179	1
Bin	(9)	0	1	31	1
Bin	(9)	1	0	196	1
Bin	(8)	0	1	64	1
Bin	(8)	1	0	229	1
Bin	(7)	0	1	127	1
Bin	(7)	1	0	292	1
Bin	(6)	0	1	520	1
Bin	(6)	1	0	1180	1
Bin	(5)	0	1	1156	1
Bin	(5)	1	0	1816	1
Bin	(4)	0	1	4125	1
Bin	(4)	1	0	5726	1
Bin	(3)	0	1	8569	1
Bin	(3)	1	0	10170	1
Bin	(2)	0	1	17972	1
Bin	(2)	1	0	19573	1
Bin	(1)	0	1	35812	1
Bin	(1)	1	0	37413	1
Bin	(0)	0	1	69600	1
Bin	(0)	1	0	71201	1

Signal:

RXB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	25127	1
Bin	(31)	1	0	23668	1
Bin	(30)	0	1	16750	1
Bin	(30)	1	0	24002	1
Bin	(29)	0	1	20741	1
Bin	(29)	1	0	19160	1
Bin	(28)	0	1	25091	1
Bin	(28)	1	0	34100	1
Bin	(27)	0	1	25192	1
Bin	(27)	1	0	24966	1
Bin	(26)	0	1	24518	1
Bin	(26)	1	0	33476	1
Bin	(25)	0	1	28939	1
Bin	(25)	1	0	28862	1
Bin	(24)	0	1	27276	1
Bin	(24)	1	0	29934	1
Bin	(23)	0	1	28977	1
Bin	(23)	1	0	28891	1
Bin	(22)	0	1	20515	1
Bin	(22)	1	0	29260	1
Bin	(21)	0	1	25083	1
Bin	(21)	1	0	24832	1
Bin	(20)	0	1	25360	1
Bin	(20)	1	0	34091	1
Bin	(19)	0	1	26658	1
Bin	(19)	1	0	26871	1
Bin	(18)	0	1	27021	1
Bin	(18)	1	0	36204	1
Bin	(17)	0	1	30504	1
Bin	(17)	1	0	29594	1
Bin	(16)	0	1	21581	1
Bin	(16)	1	0	29591	1
Bin	(15)	0	1	30594	1
Bin	(15)	1	0	28820	1
Bin	(14)	0	1	22942	1
Bin	(14)	1	0	30151	1
Bin	(13)	0	1	30179	1
Bin	(13)	1	0	25900	1
Bin	(12)	0	1	32619	1
Bin	(12)	1	0	37795	1
Bin	(11)	0	1	33856	1
Bin	(11)	1	0	29259	1
Bin	(10)	0	1	27274	1
Bin	(10)	1	0	33859	1
Bin	(9)	0	1	33278	1
Bin	(9)	1	0	30434	1
Bin	(8)	0	1	22595	1
Bin	(8)	1	0	29433	1
Bin	(7)	0	1	34617	1
Bin	(7)	1	0	31102	1
Bin	(6)	0	1	24596	1
Bin	(6)	1	0	30113	1
Bin	(5)	0	1	29638	1
Bin	(5)	1	0	27108	1
Bin	(4)	0	1	27224	1
Bin	(4)	1	0	33970	1
Bin	(3)	0	1	28271	1
Bin	(3)	1	0	25534	1
Bin	(2)	0	1	28423	1
Bin	(2)	1	0	34635	1
Bin	(1)	0	1	33739	1
Bin	(1)	1	0	30948	1
Bin	(0)	0	1	24894	1
Bin	(0)	1	0	30626	1

Signal:

RX_BUF_RST_N_D

	From	To	Count	Threshold
Bin	0	1	8544	1
Bin	1	0	8532	1

Signal:

RX_BUF_RST_N_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	8439	1
Bin	1	0	8428	1

Signal:

RX_BUF_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	176716	1
Bin	1	0	178317	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	13690855	1
Bin	1	0	13692456	1

Signal:

RX_PARITY_MISMATCH_COMB

	From	To	Count	Threshold
Bin	0	1	18725	1
Bin	1	0	19742	1

Uncovered expressions:

Excluded expressions:

"and" expression on line 552:

 read_pointer = write_pointer_raw and frame_count > 0 
 <-------------LHS-------------->     <-----RHS----->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"and" expression on line 621:

 (rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1') 
  <-----------LHS----------->       <-----RHS------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"and" expression on line 709:

 (read_increment = '1') and (read_counter_q = "00001") 
  <-------LHS-------->       <---------RHS---------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"or" expression on line 436:

 mr_command_rrb = '1' or rst_n = '0' 
 <-------LHS-------->    <---RHS--->

	LHS	RHS	Count	Threshold
Bin	False	False	14212	1
Bin	False	True	8072	1
Bin	True	False	460	1

"=" expression on line 436:

mr_command_rrb = '1'

	Evaluated to	Count	Threshold
Bin	False	22284	1
Bin	True	460	1

"=" expression on line 436:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	14672	1
Bin	True	8072	1

"=" expression on line 528:

mr_mode_rxbam = RXBAM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	5292	1
Bin	True	157358	1

"and" expression on line 532:

 read_attempt = '1' and rx_empty_i = '0' 
 <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	98549	1
Bin	True	False	6952	1
Bin	True	True	50920	1

"=" expression on line 532:

read_attempt = '1'

	Evaluated to	Count	Threshold
Bin	False	116126	1
Bin	True	57872	1

"=" expression on line 532:

rx_empty_i = '0'

	Evaluated to	Count	Threshold
Bin	False	24529	1
Bin	True	149469	1

"and" expression on lines 540 to 541:

 write_raw_intent = '1' and overrun_condition = '0' and data_overrun_i = '0' 
 <----------------------LHS----------------------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	114432	1
Bin	True	False	17	1
Bin	True	True	112334	1

"and" expression on line 540:

 write_raw_intent = '1' and overrun_condition = '0' 
 <--------LHS--------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	116510	1
Bin	True	False	82	1
Bin	True	True	112351	1

"=" expression on line 540:

write_raw_intent = '1'

	Evaluated to	Count	Threshold
Bin	False	118156	1
Bin	True	112433	1

"=" expression on line 540:

overrun_condition = '0'

	Evaluated to	Count	Threshold
Bin	False	1728	1
Bin	True	228861	1

"=" expression on line 541:

data_overrun_i = '0'

	Evaluated to	Count	Threshold
Bin	False	3823	1
Bin	True	226766	1

"and" expression on line 552:

 read_pointer = write_pointer_raw and frame_count > 0 
 <-------------LHS-------------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	True	False	25038	1
Bin	True	True	47	1

"and" expression on line 563:

 write_raw_intent = '1' and is_free_word = '0' 
 <--------LHS--------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	66	1
Bin	True	False	112312	1
Bin	True	True	45	1

"=" expression on line 563:

write_raw_intent = '1'

	Evaluated to	Count	Threshold
Bin	False	115600	1
Bin	True	112357	1

"=" expression on line 563:

is_free_word = '0'

	Evaluated to	Count	Threshold
Bin	False	227846	1
Bin	True	111	1

"=" expression on line 573:

rx_empty_i = '0'

	Evaluated to	Count	Threshold
Bin	False	75269	1
Bin	True	50170	1

"or" expression on line 620:

 rec_is_rtr = RTR_FRAME or rec_erf = ERFM_ENABLED 
 <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	176855	1
Bin	False	True	283	1
Bin	True	False	25925	1

"=" expression on line 620:

rec_is_rtr = RTR_FRAME

	Evaluated to	Count	Threshold
Bin	False	177138	1
Bin	True	25980	1

"=" expression on line 620:

rec_erf = ERFM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	202780	1
Bin	True	338	1

"and" expression on line 621:

 (rec_frame_type = NORMAL_CAN) and (rec_dlc(3) = '1') 
  <-----------LHS----------->       <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	True	False	76970	1
Bin	True	True	6019	1

"=" expression on line 621:

rec_frame_type = NORMAL_CAN

	Evaluated to	Count	Threshold
Bin	False	93866	1
Bin	True	82989	1

"=" expression on line 621:

rec_dlc(3) = '1'

	Evaluated to	Count	Threshold
Bin	False	76970	1
Bin	True	6019	1

"=" expression on line 625:

rec_erf = '1'

	Evaluated to	Count	Threshold
Bin	False	13974	1
Bin	True	338	1

"=" expression on line 629:

rec_erf = '1'

	Evaluated to	Count	Threshold
Bin	False	9000	1
Bin	True	338	1

"=" expression on line 633:

rec_erf = '1'

	Evaluated to	Count	Threshold
Bin	False	5731	1
Bin	True	338	1

"=" expression on line 638:

rec_lbpf = LBPF_LOOPBACK

	Evaluated to	Count	Threshold
Bin	False	17099	1
Bin	True	350	1

"and" expression on line 648:

 mr_rx_settings_rtsop = RTS_END and rec_valid_f = '1' 
 <------------LHS------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	10	1
Bin	True	False	240103	1
Bin	True	True	12979	1

"=" expression on line 648:

mr_rx_settings_rtsop = RTS_END

	Evaluated to	Count	Threshold
Bin	False	3257	1
Bin	True	253082	1

"=" expression on line 648:

rec_valid_f = '1'

	Evaluated to	Count	Threshold
Bin	False	243350	1
Bin	True	12989	1

"and" expression on line 650:

 mr_rx_settings_rtsop = RTS_BEG and sof_pulse = '1' 
 <------------LHS------------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	81084	1
Bin	True	False	40	1
Bin	True	True	15	1

"=" expression on line 650:

mr_rx_settings_rtsop = RTS_BEG

	Evaluated to	Count	Threshold
Bin	False	243305	1
Bin	True	55	1

"=" expression on line 650:

sof_pulse = '1'

	Evaluated to	Count	Threshold
Bin	False	162261	1
Bin	True	81099	1

"and" expression on line 652:

 mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1' 
 <-----------LHS----------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	31184	1
Bin	True	False	1603	1
Bin	True	True	338	1

"=" expression on line 652:

mr_mode_erfm = ERFM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	241404	1
Bin	True	1941	1

"=" expression on line 652:

rec_abort_f = '1'

	Evaluated to	Count	Threshold
Bin	False	211823	1
Bin	True	31522	1

"=" expression on line 658:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 661:

timestamp_capture_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	547161007	1
Bin	True	13327	1

"=" expression on line 685:

rx_buf_rst_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094345324	1
Bin	True	2436708	1

"=" expression on line 690:

read_increment = '1'

	Evaluated to	Count	Threshold
Bin	False	547116575	1
Bin	True	50920	1

"=" expression on line 704:

rx_buf_rst_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094345324	1
Bin	True	2436708	1

"and" expression on line 709:

 (read_increment = '1') and (read_counter_q = "00001") 
  <-------LHS-------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	True	False	41662	1
Bin	True	True	9258	1

"=" expression on line 709:

read_increment = '1'

	Evaluated to	Count	Threshold
Bin	False	547116575	1
Bin	True	50920	1

"=" expression on line 710:

commit_rx_frame = '0'

	Evaluated to	Count	Threshold
Bin	False	7	1
Bin	True	9251	1

"=" expression on line 715:

commit_rx_frame = '1'

	Evaluated to	Count	Threshold
Bin	False	547144961	1
Bin	True	13276	1

"=" expression on line 729:

rx_buf_rst_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094345324	1
Bin	True	2436708	1

"=" expression on line 735:

commit_intent = '1'

	Evaluated to	Count	Threshold
Bin	False	547154168	1
Bin	True	13327	1

"=" expression on line 736:

data_overrun_i = '0'

	Evaluated to	Count	Threshold
Bin	False	44	1
Bin	True	13283	1

"=" expression on line 757:

rx_buf_rst_n_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094345324	1
Bin	True	2436708	1

"=" expression on line 762:

mr_command_cdo = '1'

	Evaluated to	Count	Threshold
Bin	False	547167475	1
Bin	True	20	1

"=" expression on line 764:

overrun_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	547167330	1
Bin	True	145	1

"=" expression on line 789:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"or" expression on line 792:

 overrun_condition = '1' or mr_command_rrb = '1' 
 <---------LHS--------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	547173729	1
Bin	False	True	460	1
Bin	True	False	145	1

"=" expression on line 792:

overrun_condition = '1'

	Evaluated to	Count	Threshold
Bin	False	547174189	1
Bin	True	145	1

"=" expression on line 792:

mr_command_rrb = '1'

	Evaluated to	Count	Threshold
Bin	False	547173874	1
Bin	True	460	1

"=" expression on line 794:

reset_overrun_flag = '1'

	Evaluated to	Count	Threshold
Bin	False	107876276	1
Bin	True	439297453	1

"or" expression on line 808:

 rxb_port_a_write = '1' or read_attempt = '1' 
 <--------LHS--------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	234637	1
Bin	False	True	50873	1
Bin	True	False	125481	1

"=" expression on line 808:

rxb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	285510	1
Bin	True	125642	1

"=" expression on line 808:

read_attempt = '1'

	Evaluated to	Count	Threshold
Bin	False	360118	1
Bin	True	51034	1

"=" expression on line 810:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	233989	1
Bin	True	648	1

"or" expression on lines 864 to 865:

 write_raw_OK = '1' or (select_ts_wptr = '1' and data_overrun_i = '0') 
 <------LHS------->     <--------------------RHS-------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	131164	1
Bin	False	True	12945	1
Bin	True	False	112334	1

"=" expression on line 864:

write_raw_OK = '1'

	Evaluated to	Count	Threshold
Bin	False	144109	1
Bin	True	112334	1

"and" expression on line 865:

 select_ts_wptr = '1' and data_overrun_i = '0' 
 <-------LHS-------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	239711	1
Bin	True	False	44	1
Bin	True	True	12945	1

"=" expression on line 865:

select_ts_wptr = '1'

	Evaluated to	Count	Threshold
Bin	False	243454	1
Bin	True	12989	1

"=" expression on line 865:

data_overrun_i = '0'

	Evaluated to	Count	Threshold
Bin	False	3787	1
Bin	True	252656	1

"=" expression on line 873:

select_ts_wptr = '1'

	Evaluated to	Count	Threshold
Bin	False	224755	1
Bin	True	25978	1

"=" expression on line 882:

read_increment = '1'

	Evaluated to	Count	Threshold
Bin	False	60555	1
Bin	True	145838	1

"=" expression on line 901:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"and" expression on line 904:

 mr_rx_data_read = '1' and rx_parity_mismatch_comb = '1' and mr_settings_pchke = '1' 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	994185	1
Bin	True	False	28	1
Bin	True	True	13	1

"and" expression on line 904:

 mr_rx_data_read = '1' and rx_parity_mismatch_comb = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	44553922	1
Bin	True	False	50962	1
Bin	True	True	41	1

"=" expression on line 904:

mr_rx_data_read = '1'

	Evaluated to	Count	Threshold
Bin	False	547123331	1
Bin	True	51003	1

"=" expression on line 904:

rx_parity_mismatch_comb = '1'

	Evaluated to	Count	Threshold
Bin	False	502620371	1
Bin	True	44553963	1

"=" expression on line 904:

mr_settings_pchke = '1'

	Evaluated to	Count	Threshold
Bin	False	546180136	1
Bin	True	994198	1

"=" expression on line 907:

mr_command_crxpe = '1'

	Evaluated to	Count	Threshold
Bin	False	547174281	1
Bin	True	40	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_RXB_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

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