NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/generated/memory_reg_rw_lock.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.G_TEST_REGISTERS_TRUE.I_TEST_REGISTERS_REG_MAP.I_TST_DEST_TST_ADDR_SLICE_1_REG.G_BIT(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.G_TEST_REGISTERS_TRUE.I_TEST_REGISTERS_REG_MAP.I_TST_DEST_TST_ADDR_SLICE_1_REG.G_BIT(5)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 154 to 160:

154:            if (rst_n = '0') then 
155:                reg_value_r(i)  <= reset_value_i(i); 
...
159:                end if; 
160:            end if;

Count: 26829265
Threshold: 1

Signal assignment statement on line 155:

155: reg_value_r(i) <= reset_value_i(i);
Count: 15862
Threshold: 1

If statement on lines 157 to 159:

157:                if (wr_en = '1') then 
158:                    reg_value_r(i)  <= data_in(i); 
159:                end if;

Count: 13400284
Threshold: 1

Signal assignment statement on line 158:

158: reg_value_r(i) <= data_in(i);
Count: 90878
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

154: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	15862	1
Bin	False	26813403	1

"if" / "when" / "else" condition on line 156:

156: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	13400284	1
Bin	False	13413119	1

"if" / "when" / "else" condition on line 157:

157: if (wr_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	90878	1
Bin	False	13309406	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 154:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	26813403	1
Bin	True	15862	1

"=" expression on line 157:

wr_en = '1'

	Evaluated to	Count	Threshold
Bin	False	13309406	1
Bin	True	90878	1