NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_TRIGGER_GENERATOR	100.0 % (16/16)	100.0 % (14/14)	100.0 % (22/22)	100.0 % (18/18)	N.A.	N.A.	100.0 % (70/70)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_TRIGGER_GENERATOR

100.0 % (16/16)

100.0 % (14/14)

100.0 % (22/22)

100.0 % (18/18)

N.A.

100.0 % (70/70)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 168 to 170:

168:    tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else 
169:                          '0' when (rx_trig_req_q = '0') else 
170:                          tx_trig_req_flag_q;

Count: 68562434
Threshold: 1

Signal assignment statement on line 168:

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else
Count: 11423206
Threshold: 1

Signal assignment statement on line 169:

169: '0' when (rx_trig_req_q = '0') else
Count: 34290479
Threshold: 1

Signal assignment statement on line 170:

170: tx_trig_req_flag_q;
Count: 22848749
Threshold: 1

If statement on lines 174 to 178:

174:        if (rst_n = '0') then 
175:            tx_trig_req_flag_q <= '0'; 
176:        elsif (rising_edge(clk_sys)) then 
177:            tx_trig_req_flag_q <= tx_trig_req_flag_d; 
178:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 175:

175: tx_trig_req_flag_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 177:

177: tx_trig_req_flag_q <= tx_trig_req_flag_d;
Count: 547174334
Threshold: 1

Signal assignment statement on line 181:

181: tx_trig_req_flag_dq <= tx_trig_req or tx_trig_req_flag_q;
Count: 45715278
Threshold: 1

If statement on lines 188 to 192:

188:        if (rst_n = '0') then 
189:            rx_trig_req_q <= '0'; 
190:        elsif (rising_edge(clk_sys)) then 
191:            rx_trig_req_q <= rx_trig_req; 
192:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 189:

189: rx_trig_req_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 191:

191: rx_trig_req_q <= rx_trig_req;
Count: 547174334
Threshold: 1

Signal assignment statement on line 200:

200: rx_triggers(1) <= rx_trig_req;
Count: 45723324
Threshold: 1

Signal assignment statement on line 201:

201: rx_triggers(0) <= rx_trig_req_q;
Count: 22849620
Threshold: 1

If statement on lines 208 to 209:

208:    tx_trigger <= '0' when (rx_trig_req_q = '1') else 
209:                  tx_trig_req_flag_dq;

Count: 68559965
Threshold: 1

Signal assignment statement on line 208:

208: tx_trigger <= '0' when (rx_trig_req_q = '1') else
Count: 34268748
Threshold: 1

Signal assignment statement on line 209:

209: tx_trig_req_flag_dq;
Count: 34291217
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 168:

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else

	Evaluated to	Count	Threshold
Bin	True	11423206	1
Bin	False	57139228	1

"if" / "when" / "else" condition on line 169:

169: '0' when (rx_trig_req_q = '0') else

	Evaluated to	Count	Threshold
Bin	True	34290479	1
Bin	False	22848749	1

"if" / "when" / "else" condition on line 174:

174: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 176:

176: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 188:

188: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 190:

190: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 208:

208: tx_trigger <= '0' when (rx_trig_req_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	34268748	1
Bin	False	34291217	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_TRIG_REQ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIG_REQ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

RX_TRIGGERS

	Element	From	To	Count	Threshold
Bin	(1)	0	1	34283270	1
Bin	(1)	1	0	34286472	1
Bin	(0)	0	1	22846418	1
Bin	(0)	1	0	45721723	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11432038	1
Bin	1	0	11433636	1

Signal:

RX_TRIG_REQ_Q

	From	To	Count	Threshold
Bin	0	1	11423209	1
Bin	1	0	11424810	1

Signal:

TX_TRIG_REQ_FLAG_D

	From	To	Count	Threshold
Bin	0	1	11423206	1
Bin	1	0	11424807	1

Signal:

TX_TRIG_REQ_FLAG_Q

	From	To	Count	Threshold
Bin	0	1	863	1
Bin	1	0	2464	1

Signal:

TX_TRIG_REQ_FLAG_DQ

	From	To	Count	Threshold
Bin	0	1	22854376	1
Bin	1	0	22855974	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 168:

 rx_trig_req_q = '1' and tx_trig_req = '1' 
 <-------LHS------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11432038	1
Bin	True	False	22845547	1
Bin	True	True	11423206	1

"=" expression on line 168:

rx_trig_req_q = '1'

	Evaluated to	Count	Threshold
Bin	False	34293681	1
Bin	True	34268753	1

"=" expression on line 168:

tx_trig_req = '1'

	Evaluated to	Count	Threshold
Bin	False	45707190	1
Bin	True	22855244	1

"=" expression on line 169:

rx_trig_req_q = '0'

	Evaluated to	Count	Threshold
Bin	False	22848749	1
Bin	True	34290479	1

"=" expression on line 174:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"or" expression on line 181:

 tx_trig_req or tx_trig_req_flag_q 
 <---LHS--->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	22855974	1
Bin	'0'	'1'	863	1
Bin	'1'	'0'	22854376	1

"=" expression on line 188:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 208:

rx_trig_req_q = '1'

	Evaluated to	Count	Threshold
Bin	False	34291217	1
Bin	True	34268748	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_TRIGGER_GENERATOR

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 168 to 170:

Signal assignment statement on line 168:

Signal assignment statement on line 169:

Signal assignment statement on line 170:

If statement on lines 174 to 178:

Signal assignment statement on line 175:

Signal assignment statement on line 177:

Signal assignment statement on line 181:

If statement on lines 188 to 192:

Signal assignment statement on line 189:

Signal assignment statement on line 191:

Signal assignment statement on line 200:

Signal assignment statement on line 201:

If statement on lines 208 to 209:

Signal assignment statement on line 208:

Signal assignment statement on line 209:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 168:

"if" / "when" / "else" condition on line 169:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 176:

"if" / "when" / "else" condition on line 188:

"if" / "when" / "else" condition on line 190:

"if" / "when" / "else" condition on line 208:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 168:

"=" expression on line 168:

"=" expression on line 168:

"=" expression on line 169:

"=" expression on line 174:

"or" expression on line 181:

"=" expression on line 188:

"=" expression on line 208:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: