NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_COUNTERS_NBT	100.0 % (23/23)	100.0 % (20/20)	100.0 % (114/114)	100.0 % (29/29)	N.A.	N.A.	100.0 % (186/186)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_COUNTERS_NBT

100.0 % (23/23)

100.0 % (20/20)

100.0 % (114/114)

100.0 % (29/29)

N.A.

100.0 % (186/186)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

155:    tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp)) 
156:                              else 
157:                          '0';

Count: 331082050
Threshold: 1

Signal assignment statement on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))
Count: 99263834
Threshold: 1

Signal assignment statement on line 157:

157: '0';
Count: 231818216
Threshold: 1

If statement on lines 165 to 168:

165:    tq_counter_d <= 
166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
167:                                   else 
168:        std_logic_vector(unsigned(tq_counter_q) + 1);

Count: 575392062
Threshold: 1

Signal assignment statement on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')
Count: 242843114
Threshold: 1

Signal assignment statement on line 168:

168: std_logic_vector(unsigned(tq_counter_q) + 1);
Count: 332548948
Threshold: 1

If statement on lines 172 to 178:

172:        if (rst_n = '0') then 
173:            tq_counter_q <= std_logic_vector(C_TQ_RST); 
...
177:            end if; 
178:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 173:

173: tq_counter_q <= std_logic_vector(C_TQ_RST);
Count: 2422674
Threshold: 1

If statement on lines 175 to 177:

175:            if (ctrs_en = '1') then 
176:                tq_counter_q <= tq_counter_d; 
177:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 176:

176: tq_counter_q <= tq_counter_d;
Count: 547172733
Threshold: 1

Signal assignment statement on line 184:

184: tq_edge_i <= tq_counter_expired;
Count: 198530865
Threshold: 1

If statement on lines 189 to 190:

189:    segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else 
190:                      std_logic_vector(unsigned(segm_counter_q) + 1);

Count: 365566704
Threshold: 1

Signal assignment statement on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else
Count: 45756477
Threshold: 1

Signal assignment statement on line 190:

190: std_logic_vector(unsigned(segm_counter_q) + 1);
Count: 319810227
Threshold: 1

If statement on lines 192 to 194:

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
193:                           else 
194:                       '0';

Count: 244333416
Threshold: 1

Signal assignment statement on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')
Count: 139154439
Threshold: 1

Signal assignment statement on line 194:

194: '0';
Count: 105178977
Threshold: 1

If statement on lines 198 to 204:

198:        if (rst_n = '0') then 
199:            segm_counter_q <= (others => '0'); 
...
203:            end if; 
204:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 199:

199: segm_counter_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 201 to 203:

201:            if (segm_counter_ce = '1') then 
202:                segm_counter_q <= segm_counter_d; 
203:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 202:

202: segm_counter_q <= segm_counter_d;
Count: 319793894
Threshold: 1

Signal assignment statement on line 210:

210: segm_counter <= segm_counter_q;
Count: 319777107
Threshold: 1

Signal assignment statement on line 211:

211: tq_edge <= tq_edge_i;
Count: 198530865
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))

	Evaluated to	Count	Threshold
Bin	True	99263834	1
Bin	False	231818216	1

"if" / "when" / "else" condition on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	True	242843114	1
Bin	False	332548948	1

"if" / "when" / "else" condition on line 172:

172: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 174:

174: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 175:

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	547172733	1
Bin	False	1601	1

"if" / "when" / "else" condition on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	45756477	1
Bin	False	319810227	1

"if" / "when" / "else" condition on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	True	139154439	1
Bin	False	105178977	1

"if" / "when" / "else" condition on line 198:

198: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 200:

200: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 201:

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	319793894	1
Bin	False	227380440	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BRP

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TQ_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BT_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	99263834	1
Bin	1	0	99265430	1

Port:

SEGM_COUNTER

	Element	From	To	Count	Threshold
Bin	(7)	0	1	575352	1
Bin	(7)	1	0	576953	1
Bin	(6)	0	1	926888	1
Bin	(6)	1	0	928488	1
Bin	(5)	0	1	3240738	1
Bin	(5)	1	0	3242339	1
Bin	(4)	0	1	6980013	1
Bin	(4)	1	0	6981613	1
Bin	(3)	0	1	15522880	1
Bin	(3)	1	0	15524478	1
Bin	(2)	0	1	37911554	1
Bin	(2)	1	0	37913154	1
Bin	(1)	0	1	79493821	1
Bin	(1)	1	0	79495416	1
Bin	(0)	0	1	152248390	1
Bin	(0)	1	0	152249988	1

Signal:

TQ_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	2196	1
Bin	(7)	1	0	3797	1
Bin	(6)	0	1	4392	1
Bin	(6)	1	0	5993	1
Bin	(5)	0	1	16326	1
Bin	(5)	1	0	17927	1
Bin	(4)	0	1	49190	1
Bin	(4)	1	0	50791	1
Bin	(3)	0	1	814665	1
Bin	(3)	1	0	816266	1
Bin	(2)	0	1	65391475	1
Bin	(2)	1	0	65393076	1
Bin	(1)	0	1	106737032	1
Bin	(1)	1	0	106735436	1
Bin	(0)	0	1	173016149	1
Bin	(0)	1	0	173017744	1

Signal:

TQ_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	2196	1
Bin	(7)	1	0	3797	1
Bin	(6)	0	1	4392	1
Bin	(6)	1	0	5993	1
Bin	(5)	0	1	8784	1
Bin	(5)	1	0	10385	1
Bin	(4)	0	1	49190	1
Bin	(4)	1	0	50791	1
Bin	(3)	0	1	814609	1
Bin	(3)	1	0	816210	1
Bin	(2)	0	1	53382808	1
Bin	(2)	1	0	53384407	1
Bin	(1)	0	1	105264077	1
Bin	(1)	1	0	105265676	1
Bin	(0)	0	1	159527653	1
Bin	(0)	1	0	159526056	1

Signal:

TQ_COUNTER_EXPIRED

	From	To	Count	Threshold
Bin	0	1	99263834	1
Bin	1	0	99265430	1

Signal:

TQ_EDGE_I

	From	To	Count	Threshold
Bin	0	1	99263834	1
Bin	1	0	99265430	1

Signal:

SEGM_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	575374	1
Bin	(7)	1	0	576975	1
Bin	(6)	0	1	1204582	1
Bin	(6)	1	0	1206182	1
Bin	(5)	0	1	3248772	1
Bin	(5)	1	0	3250373	1
Bin	(4)	0	1	7168414	1
Bin	(4)	1	0	7170015	1
Bin	(3)	0	1	15866866	1
Bin	(3)	1	0	15868464	1
Bin	(2)	0	1	41368502	1
Bin	(2)	1	0	41370103	1
Bin	(1)	0	1	82817184	1
Bin	(1)	1	0	82818777	1
Bin	(0)	0	1	167555093	1
Bin	(0)	1	0	167553497	1

Signal:

SEGM_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	575352	1
Bin	(7)	1	0	576953	1
Bin	(6)	0	1	926888	1
Bin	(6)	1	0	928488	1
Bin	(5)	0	1	3240738	1
Bin	(5)	1	0	3242339	1
Bin	(4)	0	1	6980013	1
Bin	(4)	1	0	6981613	1
Bin	(3)	0	1	15522880	1
Bin	(3)	1	0	15524478	1
Bin	(2)	0	1	37911554	1
Bin	(2)	1	0	37913154	1
Bin	(1)	0	1	79493821	1
Bin	(1)	1	0	79495416	1
Bin	(0)	0	1	152248390	1
Bin	(0)	1	0	152249988	1

Signal:

SEGM_COUNTER_CE

	From	To	Count	Threshold
Bin	0	1	105164225	1
Bin	1	0	105165821	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

 tq_counter_expired = '1' or tq_reset = '1' 
 <---------LHS---------->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	332548948	1
Bin	False	True	14445928	1
Bin	True	False	207284386	1

"=" expression on line 166:

tq_counter_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	346994876	1
Bin	True	228397186	1

"=" expression on line 166:

tq_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	539833334	1
Bin	True	35558728	1

"=" expression on line 172:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 175:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	1601	1
Bin	True	547172733	1

"=" expression on line 189:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	319810227	1
Bin	True	45756477	1

"or" expression on line 192:

 (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
  <----LHS----->      <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	105178977	1
Bin	False	True	112142022	1
Bin	True	False	10017322	1

"=" expression on line 192:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	217320999	1
Bin	True	27012417	1

"and" expression on line 192:

 tq_edge_i = '1' and ctrs_en = '1' 
 <-----LHS----->     <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	115179149	1
Bin	True	False	7337	1
Bin	True	True	129137117	1

"=" expression on line 192:

tq_edge_i = '1'

	Evaluated to	Count	Threshold
Bin	False	115188962	1
Bin	True	129144454	1

"=" expression on line 192:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	17150	1
Bin	True	244316266	1

"=" expression on line 198:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 201:

segm_counter_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	227380440	1
Bin	True	319793894	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_COUNTERS_NBT

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

Signal assignment statement on line 155:

Signal assignment statement on line 157:

If statement on lines 165 to 168:

Signal assignment statement on line 166:

Signal assignment statement on line 168:

If statement on lines 172 to 178:

Signal assignment statement on line 173:

If statement on lines 175 to 177:

Signal assignment statement on line 176:

Signal assignment statement on line 184:

If statement on lines 189 to 190:

Signal assignment statement on line 189:

Signal assignment statement on line 190:

If statement on lines 192 to 194:

Signal assignment statement on line 192:

Signal assignment statement on line 194:

If statement on lines 198 to 204:

Signal assignment statement on line 199:

If statement on lines 201 to 203:

Signal assignment statement on line 202:

Signal assignment statement on line 210:

Signal assignment statement on line 211:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 172:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 175:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on line 192:

"if" / "when" / "else" condition on line 198:

"if" / "when" / "else" condition on line 200:

"if" / "when" / "else" condition on line 201:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 172:

"=" expression on line 175:

"=" expression on line 189:

"or" expression on line 192:

"=" expression on line 192:

"and" expression on line 192:

"=" expression on line 192:

"=" expression on line 192:

"=" expression on line 198:

"=" expression on line 201:

Uncovered FSM states:

Excluded FSM states: