NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_CTU_CAN_FD_VIP.G_FUNC_COV.I_FUNC_COV_AGENT.I_FUNC_COV_PRESCALER

File:  /__w/CTU-CAN-FD/CTU-CAN-FD/test/main_tb/agents/functional_coverage_agent/func_cov_agent.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_CTU_CAN_FD_VIP.G_FUNC_COV.I_FUNC_COV_AGENT.I_FUNC_COV_PRESCALER N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (25/25) 100.0 % (27/27)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

 CLK
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 162 to 163:

162:    -- psl nominal_sample_cov : cover 
163:    --  {sp_control = NOMINAL_SAMPLE}; 

Count: 416059850
Threshold: 1

PSL cover point on lines 165 to 166:

165:    -- psl data_sample_cov : cover 
166:    --  {sp_control = DATA_SAMPLE}; 

Count: 123218688
Threshold: 1

PSL cover point on lines 168 to 169:

168:    -- psl secondary_sample_cov : cover 
169:    --  {sp_control = SECONDARY_SAMPLE}; 

Count: 9102447
Threshold: 1

PSL cover point on lines 176 to 178:

176:    -- psl minimal_bit_time_nbt_cov : cover 
177:    --  {to_integer(unsigned(tseg1_nbt)) = 5 and to_integer(unsigned(tseg2_nbt)) = 3 
178:    --   and to_integer(unsigned(brp_nbt)) = 1}; 

Count: 37257353
Threshold: 1

PSL cover point on lines 180 to 182:

180:    -- psl minimal_bit_time_dbt_cov : cover 
181:    --  {to_integer(unsigned(tseg1_dbt)) = 3 and to_integer(unsigned(tseg2_dbt)) = 2 
182:    --   and to_integer(unsigned(brp_dbt)) = 1}; 

Count: 37404934
Threshold: 1

PSL cover point on lines 184 to 185:

184:    -- psl maximal_bit_time_nbt_cov : cover 
185:    --  {to_integer(unsigned(tseg1_nbt)) = 191 and to_integer(unsigned(tseg2_nbt)) = 63}; 

Count: 166049490
Threshold: 1

PSL cover point on lines 187 to 188:

187:    -- psl maximal_bit_time_dbt_cov : cover 
188:    --  {to_integer(unsigned(tseg1_dbt)) = 95 and to_integer(unsigned(tseg2_dbt)) = 31}; 

Count: 229112786
Threshold: 1

PSL cover point on lines 195 to 196:

195:    -- psl brp_bin_1_1_cov : cover 
196:    --  {to_integer(unsigned(brp_nbt)) = 1 and to_integer(unsigned(brp_dbt)) = 1}; 

Count: 198306458
Threshold: 1

PSL cover point on lines 198 to 199:

198:    -- psl brp_bin_2_1_cov : cover 
199:    --  {to_integer(unsigned(brp_nbt)) = 2 and to_integer(unsigned(brp_dbt)) = 1}; 

Count: 66862024
Threshold: 1

PSL cover point on lines 201 to 202:

201:    -- psl brp_bin_3_1_cov : cover 
202:    --  {to_integer(unsigned(brp_nbt)) = 3 and to_integer(unsigned(brp_dbt)) = 1}; 

Count: 31694095
Threshold: 1

PSL cover point on lines 204 to 205:

204:    -- psl brp_bin_4_1_cov : cover 
205:    --  {to_integer(unsigned(brp_nbt)) = 4 and to_integer(unsigned(brp_dbt)) = 1}; 

Count: 77749973
Threshold: 1

PSL cover point on lines 207 to 208:

207:    -- psl brp_bin_4_3_cov : cover 
208:    --  {to_integer(unsigned(brp_nbt)) = 4 and to_integer(unsigned(brp_dbt)) = 3}; 

Count: 3936200
Threshold: 1

PSL cover point on lines 215 to 216:

215:    -- psl brp_nbt_max_cov : cover 
216:    --  {to_integer(unsigned(brp_nbt)) = 255}; 

Count: 560063
Threshold: 1

PSL cover point on lines 218 to 219:

218:    -- psl brp_dbt_max_cov : cover 
219:    --  {to_integer(unsigned(brp_dbt)) = 255}; 

Count: 5867352
Threshold: 1

PSL cover point on lines 227 to 228:

227:    -- psl pos_resync_in_nominal_bit_rate_cov : cover 
228:    --  {resync_edge_valid = '1' and is_tseg1 = '1' and sp_control = NOMINAL_SAMPLE}; 

Count: 309721
Threshold: 1

PSL cover point on lines 231 to 232:

231:    -- psl neg_resync_in_nominal_bit_rate_cov : cover 
232:    --  {resync_edge_valid = '1' and is_tseg2 = '1' and sp_control = NOMINAL_SAMPLE}; 

Count: 10361
Threshold: 1

PSL cover point on lines 235 to 236:

235:    -- psl neg_resync_in_data_bit_rate_cov : cover 
236:    --  {resync_edge_valid = '1' and is_tseg2 = '1' and sp_control = DATA_SAMPLE}; 

Count: 6164
Threshold: 1

PSL cover point on lines 239 to 240:

239:    -- psl pos_resync_in_data_bit_rate_cov : cover 
240:    --  {resync_edge_valid = '1' and is_tseg1 = '1' and sp_control = DATA_SAMPLE}; 

Count: 398000
Threshold: 1

PSL cover point on lines 247 to 248:

247:    -- psl h_sync_ignored_due_to_previous_sync_cov : cover 
248:    --  {sync_flag = '1' and h_sync_edge = '1'}; 

Count: 48
Threshold: 1

PSL cover point on lines 250 to 251:

250:    -- psl re_sync_ignored_due_to_previous_sync_cov : cover 
251:    --  {sync_flag = '1' and resync_edge = '1'}; 

Count: 341
Threshold: 1

PSL cover point on lines 253 to 254:

253:    -- psl h_sync_in_tseg_1_cov : cover 
254:    --  {h_sync_edge_valid = '1' and is_tseg1 = '1'}; 

Count: 42738
Threshold: 1

PSL cover point on lines 256 to 257:

256:    -- psl h_sync_in_tseg_2_cov : cover 
257:    --  {h_sync_edge_valid = '1' and is_tseg2 = '1'}; 

Count: 7483
Threshold: 1

PSL cover point on lines 260 to 261:

260:    -- psl re_sync_in_tseg_1_cov : cover 
261:    --  {resync_edge_valid = '1' and is_tseg1 = '1'}; 

Count: 707721
Threshold: 1

PSL cover point on lines 263 to 264:

263:    -- psl re_sync_in_tseg_2_cov : cover 
264:    --  {resync_edge_valid = '1' and is_tseg2 = '1'}; 

Count: 16525
Threshold: 1

PSL cover point on lines 271 to 273:

271:    -- psl tx_trigger_throttling_cov : cover 
272:    --  {rx_trig_req_q = '1' and tx_trig_req = '1'} 
273:    --  report "TX trigger throtlled!"; 

Count: 863
Threshold: 1