NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/generated/control_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
G_ADDR_DEC(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(4)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(5)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(6)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(7)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(8)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(9)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(10)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(11)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(12)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(13)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(14)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(15)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(16)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(17)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(18)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(19)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(20)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(21)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(22)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(23)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(24)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(25)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(26)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(27)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(28)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(29)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(30)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(31)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(32)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(33)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(34)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(35)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(36)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(37)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC(38)	100.0 % (3/3)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (5/5)
G_ADDR_DEC_REG_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

G_ADDR_DEC(0)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(1)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(2)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(3)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(4)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(5)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(6)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(7)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(8)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(9)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(10)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(11)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(12)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(13)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(14)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(15)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(16)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(17)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(18)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(19)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(20)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(21)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(22)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(23)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(24)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(25)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(26)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(27)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(28)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(29)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(30)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(31)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(32)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(33)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(34)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(35)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(36)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(37)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC(38)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

G_ADDR_DEC_REG_F

100.0 % (1/1)

N.A.

100.0 % (1/1)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP.I_ADDRESS_DECODER_CONTROL_REGISTERS	100.0 % (3/3)	100.0 % (2/2)	100.0 % (252/252)	100.0 % (2/2)	N.A.	N.A.	100.0 % (259/259)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP.I_ADDRESS_DECODER_CONTROL_REGISTERS

100.0 % (3/3)

100.0 % (2/2)

100.0 % (252/252)

100.0 % (2/2)

N.A.

100.0 % (259/259)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 153 to 154:

153:    addr_dec_enabled_i <= addr_dec_i when (enable = '1') else 
154:                          (OTHERS => '0');

Count: 55728473
Threshold: 1

Signal assignment statement on line 153:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else
Count: 19663072
Threshold: 1

Signal assignment statement on line 154:

154: (OTHERS => '0');
Count: 36065401
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 153:

153: addr_dec_enabled_i <= addr_dec_i when (enable = '1') else

	Evaluated to	Count	Threshold
Bin	True	19663072	1
Bin	False	36065401	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

ADDR_DEC

	Element	From	To	Count	Threshold
Bin	(38)	0	1	3935	1
Bin	(38)	1	0	4421484	1
Bin	(37)	0	1	3935	1
Bin	(37)	1	0	4417542	1
Bin	(36)	0	1	45	1
Bin	(36)	1	0	4413832	1
Bin	(35)	0	1	10164430	1
Bin	(35)	1	0	29044639	1
Bin	(34)	0	1	1122	1
Bin	(34)	1	0	4496715	1
Bin	(33)	0	1	1122	1
Bin	(33)	1	0	4426979	1
Bin	(32)	0	1	3459	1
Bin	(32)	1	0	39324286	1
Bin	(31)	0	1	537	1
Bin	(31)	1	0	39327208	1
Bin	(30)	0	1	4066	1
Bin	(30)	1	0	39323679	1
Bin	(29)	0	1	28212	1
Bin	(29)	1	0	39299533	1
Bin	(28)	0	1	8204	1
Bin	(28)	1	0	39319541	1
Bin	(27)	0	1	51013	1
Bin	(27)	1	0	39276732	1
Bin	(26)	0	1	13223	1
Bin	(26)	1	0	39314522	1
Bin	(25)	0	1	12418	1
Bin	(25)	1	0	39290491	1
Bin	(24)	0	1	12418	1
Bin	(24)	1	0	24596787	1
Bin	(23)	0	1	20068	1
Bin	(23)	1	0	39307677	1
Bin	(22)	0	1	70	1
Bin	(22)	1	0	35576673	1
Bin	(21)	0	1	70	1
Bin	(21)	1	0	35559705	1
Bin	(20)	0	1	2835	1
Bin	(20)	1	0	39295600	1
Bin	(19)	0	1	2835	1
Bin	(19)	1	0	35559266	1
Bin	(18)	0	1	2835	1
Bin	(18)	1	0	35564094	1
Bin	(17)	0	1	2835	1
Bin	(17)	1	0	35559266	1
Bin	(16)	0	1	4082	1
Bin	(16)	1	0	39322249	1
Bin	(15)	0	1	4082	1
Bin	(15)	1	0	39322245	1
Bin	(14)	0	1	44153	1
Bin	(14)	1	0	39283592	1
Bin	(13)	0	1	2192	1
Bin	(13)	1	0	39263691	1
Bin	(12)	0	1	14066	1
Bin	(12)	1	0	36394023	1
Bin	(11)	0	1	112244	1
Bin	(11)	1	0	39215501	1
Bin	(10)	0	1	6711	1
Bin	(10)	1	0	39321034	1
Bin	(9)	0	1	6621	1
Bin	(9)	1	0	39321124	1
Bin	(8)	0	1	485	1
Bin	(8)	1	0	39327260	1
Bin	(7)	0	1	565	1
Bin	(7)	1	0	39327180	1
Bin	(6)	0	1	552	1
Bin	(6)	1	0	39327193	1
Bin	(5)	0	1	632	1
Bin	(5)	1	0	39327113	1
Bin	(4)	0	1	2154	1
Bin	(4)	1	0	39325591	1
Bin	(3)	0	1	1473	1
Bin	(3)	1	0	39326272	1
Bin	(2)	0	1	9047813	1
Bin	(2)	1	0	30279932	1
Bin	(1)	0	1	75535	1
Bin	(1)	1	0	39252210	1
Bin	(0)	0	1	25	1
Bin	(0)	1	0	39327720	1

Signal:

ADDR_DEC_I

	Element	From	To	Count	Threshold
Bin	(38)	0	1	3935	1
Bin	(38)	1	0	55722937	1
Bin	(37)	0	1	3935	1
Bin	(37)	1	0	55722937	1
Bin	(36)	0	1	45	1
Bin	(36)	1	0	55726827	1
Bin	(35)	0	1	16777225	1
Bin	(35)	1	0	38949647	1
Bin	(34)	0	1	1134	1
Bin	(34)	1	0	55725738	1
Bin	(33)	0	1	1134	1
Bin	(33)	1	0	55725738	1
Bin	(32)	0	1	5933	1
Bin	(32)	1	0	55720939	1
Bin	(31)	0	1	1770	1
Bin	(31)	1	0	55725102	1
Bin	(30)	0	1	4066	1
Bin	(30)	1	0	55722806	1
Bin	(29)	0	1	43258	1
Bin	(29)	1	0	55683614	1
Bin	(28)	0	1	17451	1
Bin	(28)	1	0	55709421	1
Bin	(27)	0	1	62059	1
Bin	(27)	1	0	55664813	1
Bin	(26)	0	1	13433	1
Bin	(26)	1	0	55713439	1
Bin	(25)	0	1	12628	1
Bin	(25)	1	0	55714244	1
Bin	(24)	0	1	12628	1
Bin	(24)	1	0	55714244	1
Bin	(23)	0	1	20068	1
Bin	(23)	1	0	55706804	1
Bin	(22)	0	1	70	1
Bin	(22)	1	0	55726802	1
Bin	(21)	0	1	70	1
Bin	(21)	1	0	55726802	1
Bin	(20)	0	1	26801	1
Bin	(20)	1	0	55700071	1
Bin	(19)	0	1	28012	1
Bin	(19)	1	0	55698860	1
Bin	(18)	0	1	28012	1
Bin	(18)	1	0	55698860	1
Bin	(17)	0	1	28012	1
Bin	(17)	1	0	55698860	1
Bin	(16)	0	1	29259	1
Bin	(16)	1	0	55697613	1
Bin	(15)	0	1	29542	1
Bin	(15)	1	0	55697330	1
Bin	(14)	0	1	72701	1
Bin	(14)	1	0	55654171	1
Bin	(13)	0	1	28452	1
Bin	(13)	1	0	55698420	1
Bin	(12)	0	1	40326	1
Bin	(12)	1	0	55686546	1
Bin	(11)	0	1	142297	1
Bin	(11)	1	0	55584575	1
Bin	(10)	0	1	35239	1
Bin	(10)	1	0	55691633	1
Bin	(9)	0	1	35828	1
Bin	(9)	1	0	55691044	1
Bin	(8)	0	1	27311	1
Bin	(8)	1	0	55699561	1
Bin	(7)	0	1	27772	1
Bin	(7)	1	0	55699100	1
Bin	(6)	0	1	28113	1
Bin	(6)	1	0	55698759	1
Bin	(5)	0	1	34161	1
Bin	(5)	1	0	55692711	1
Bin	(4)	0	1	56669	1
Bin	(4)	1	0	55670203	1
Bin	(3)	0	1	149740	1
Bin	(3)	1	0	55577132	1
Bin	(2)	0	1	9655644	1
Bin	(2)	1	0	46071228	1
Bin	(1)	0	1	279697	1
Bin	(1)	1	0	55447175	1
Bin	(0)	0	1	99006	1
Bin	(0)	1	0	55627866	1

Signal:

ADDR_DEC_ENABLED_I

	Element	From	To	Count	Threshold
Bin	(38)	0	1	3935	1
Bin	(38)	1	0	5536	1
Bin	(37)	0	1	3935	1
Bin	(37)	1	0	5536	1
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Bin	(36)	1	0	1646	1
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Bin	(35)	1	0	10166031	1
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Bin	(34)	1	0	2723	1
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Bin	(32)	1	0	5060	1
Bin	(31)	0	1	537	1
Bin	(31)	1	0	2138	1
Bin	(30)	0	1	4066	1
Bin	(30)	1	0	5667	1
Bin	(29)	0	1	28212	1
Bin	(29)	1	0	29813	1
Bin	(28)	0	1	8204	1
Bin	(28)	1	0	9805	1
Bin	(27)	0	1	51013	1
Bin	(27)	1	0	52614	1
Bin	(26)	0	1	13223	1
Bin	(26)	1	0	14824	1
Bin	(25)	0	1	12418	1
Bin	(25)	1	0	14019	1
Bin	(24)	0	1	12418	1
Bin	(24)	1	0	14019	1
Bin	(23)	0	1	20068	1
Bin	(23)	1	0	21669	1
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Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 153:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	36065401	1
Bin	True	19663072	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP.I_ADDRESS_DECODER_CONTROL_REGISTERS

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/generated/control_registers_reg_map.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 153 to 154:

Signal assignment statement on line 153:

Signal assignment statement on line 154:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 153:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 153:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: