File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/generated/control_registers_reg_map.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Register map implementation of: Control_registers
70: --------------------------------------------------------------------------------
71: -- This file is autogenerated, DO NOT EDIT!
72:
73: Library ieee;
74: use ieee.std_logic_1164.all;
75:
76: Library ctu_can_fd_rtl;
77: use ctu_can_fd_rtl.can_registers_pkg.all;
78: use ctu_can_fd_rtl.cmn_reg_map_pkg.all;
79:
80: entity control_registers_reg_map is
81: generic (
82: constant DATA_WIDTH : natural := 32;
83: constant ADDRESS_WIDTH : natural := 8;
84: constant REGISTERED_READ : boolean := true;
85: constant CLEAR_READ_DATA : boolean := true;
86: constant G_FILT_A_EN : boolean := true;
87: constant G_FILT_RANGE_EN : boolean := true;
88: constant G_FILT_C_EN : boolean := true;
89: constant G_FILT_B_EN : boolean := true;
90: constant G_TRAFFIC_CTRS_EN : boolean := true;
91: constant G_TXT_BUF_COUNT : integer := 0
92: );
93: port (
94: signal clk_sys :in std_logic;
95: signal rst_n :in std_logic;
96: signal address :in std_logic_vector(address_width - 1 downto 0);
97: signal w_data :in std_logic_vector(data_width - 1 downto 0);
98: signal r_data :out std_logic_vector(data_width - 1 downto 0);
99: signal cs :in std_logic;
100: signal read :in std_logic;
101: signal write :in std_logic;
102: signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
103: signal lock_1 :in std_logic;
104: signal lock_2 :in std_logic;
105: signal control_registers_out :out Control_registers_out_t;
106: signal control_registers_in :in Control_registers_in_t
107: );
108: end entity control_registers_reg_map;
109:
110:
111: architecture rtl of control_registers_reg_map is
112: signal reg_sel : std_logic_vector(38 downto 0);
113: constant ADDR_VECT
114: : std_logic_vector(233 downto 0) := "100110100101100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
115: signal r_data_comb : std_logic_vector(31 downto 0);
116: signal read_data_mask_n : std_logic_vector(31 downto 0);
117: signal control_registers_out_i : Control_registers_out_t;
118: signal write_en : std_logic_vector(3 downto 0);
119: begin
120:
121: write_en <= be when (write = '1' and cs = '1') else (others => '0');
122:
123: ----------------------------------------------------------------------------
124: -- Write address to One-hot decoder
125: ----------------------------------------------------------------------------
126:
127: i_address_decoder_control_registers : address_decoder
128: generic map(
129: address_width => 6 ,
130: address_entries => 39 ,
131: addr_vect => ADDR_VECT ,
132: registered_out => false
133: )
134: port map(
135: clk_sys => clk_sys ,-- in
136: rst_n => rst_n ,-- in
137: address => address(7 downto 2) ,-- in
138: enable => cs ,-- in
139: addr_dec => reg_sel -- out
140: );
141:
142: ----------------------------------------------------------------------------
143: -- MODE[RST]
144: ----------------------------------------------------------------------------
145:
146: i_mode_rst_reg : memory_reg_os
147: generic map(
148: data_width => 1 ,
149: reset_value => "0"
150: )
151: port map(
152: clk_sys => clk_sys ,-- in
153: rst_n => rst_n ,-- in
154: data_in => w_data(0 downto 0) ,-- in
155: write => write_en(0) ,-- in
156: cs => reg_sel(1) ,-- in
157: reg_value(0) => control_registers_out_i.mode_rst -- out
158: );
159:
160: ----------------------------------------------------------------------------
161: -- MODE[BMM]
162: ----------------------------------------------------------------------------
163:
164: i_mode_bmm_reg : memory_reg_rw
165: generic map(
166: data_width => 1 ,
167: reset_value => "0"
168: )
169: port map(
170: clk_sys => clk_sys ,-- in
171: rst_n => rst_n ,-- in
172: data_in => w_data(1 downto 1) ,-- in
173: write => write_en(0) ,-- in
174: cs => reg_sel(1) ,-- in
175: reg_value(0) => control_registers_out_i.mode_bmm -- out
176: );
177:
178: ----------------------------------------------------------------------------
179: -- MODE[STM]
180: ----------------------------------------------------------------------------
181:
182: i_mode_stm_reg : memory_reg_rw
183: generic map(
184: data_width => 1 ,
185: reset_value => "0"
186: )
187: port map(
188: clk_sys => clk_sys ,-- in
189: rst_n => rst_n ,-- in
190: data_in => w_data(2 downto 2) ,-- in
191: write => write_en(0) ,-- in
192: cs => reg_sel(1) ,-- in
193: reg_value(0) => control_registers_out_i.mode_stm -- out
194: );
195:
196: ----------------------------------------------------------------------------
197: -- MODE[AFM]
198: ----------------------------------------------------------------------------
199:
200: i_mode_afm_reg : memory_reg_rw
201: generic map(
202: data_width => 1 ,
203: reset_value => "0"
204: )
205: port map(
206: clk_sys => clk_sys ,-- in
207: rst_n => rst_n ,-- in
208: data_in => w_data(3 downto 3) ,-- in
209: write => write_en(0) ,-- in
210: cs => reg_sel(1) ,-- in
211: reg_value(0) => control_registers_out_i.mode_afm -- out
212: );
213:
214: ----------------------------------------------------------------------------
215: -- MODE[FDE]
216: ----------------------------------------------------------------------------
217:
218: i_mode_fde_reg : memory_reg_rw
219: generic map(
220: data_width => 1 ,
221: reset_value => "1"
222: )
223: port map(
224: clk_sys => clk_sys ,-- in
225: rst_n => rst_n ,-- in
226: data_in => w_data(4 downto 4) ,-- in
227: write => write_en(0) ,-- in
228: cs => reg_sel(1) ,-- in
229: reg_value(0) => control_registers_out_i.mode_fde -- out
230: );
231:
232: ----------------------------------------------------------------------------
233: -- MODE[TTTM]
234: ----------------------------------------------------------------------------
235:
236: i_mode_tttm_reg : memory_reg_rw
237: generic map(
238: data_width => 1 ,
239: reset_value => "0"
240: )
241: port map(
242: clk_sys => clk_sys ,-- in
243: rst_n => rst_n ,-- in
244: data_in => w_data(5 downto 5) ,-- in
245: write => write_en(0) ,-- in
246: cs => reg_sel(1) ,-- in
247: reg_value(0) => control_registers_out_i.mode_tttm -- out
248: );
249:
250: ----------------------------------------------------------------------------
251: -- MODE[ROM]
252: ----------------------------------------------------------------------------
253:
254: i_mode_rom_reg : memory_reg_rw
255: generic map(
256: data_width => 1 ,
257: reset_value => "0"
258: )
259: port map(
260: clk_sys => clk_sys ,-- in
261: rst_n => rst_n ,-- in
262: data_in => w_data(6 downto 6) ,-- in
263: write => write_en(0) ,-- in
264: cs => reg_sel(1) ,-- in
265: reg_value(0) => control_registers_out_i.mode_rom -- out
266: );
267:
268: ----------------------------------------------------------------------------
269: -- MODE[ACF]
270: ----------------------------------------------------------------------------
271:
272: i_mode_acf_reg : memory_reg_rw
273: generic map(
274: data_width => 1 ,
275: reset_value => "0"
276: )
277: port map(
278: clk_sys => clk_sys ,-- in
279: rst_n => rst_n ,-- in
280: data_in => w_data(7 downto 7) ,-- in
281: write => write_en(0) ,-- in
282: cs => reg_sel(1) ,-- in
283: reg_value(0) => control_registers_out_i.mode_acf -- out
284: );
285:
286: ----------------------------------------------------------------------------
287: -- MODE[TSTM]
288: ----------------------------------------------------------------------------
289:
290: i_mode_tstm_reg : memory_reg_rw
291: generic map(
292: data_width => 1 ,
293: reset_value => "0"
294: )
295: port map(
296: clk_sys => clk_sys ,-- in
297: rst_n => rst_n ,-- in
298: data_in => w_data(8 downto 8) ,-- in
299: write => write_en(1) ,-- in
300: cs => reg_sel(1) ,-- in
301: reg_value(0) => control_registers_out_i.mode_tstm -- out
302: );
303:
304: ----------------------------------------------------------------------------
305: -- MODE[RXBAM]
306: ----------------------------------------------------------------------------
307:
308: i_mode_rxbam_reg : memory_reg_rw
309: generic map(
310: data_width => 1 ,
311: reset_value => "1"
312: )
313: port map(
314: clk_sys => clk_sys ,-- in
315: rst_n => rst_n ,-- in
316: data_in => w_data(9 downto 9) ,-- in
317: write => write_en(1) ,-- in
318: cs => reg_sel(1) ,-- in
319: reg_value(0) => control_registers_out_i.mode_rxbam -- out
320: );
321:
322: ----------------------------------------------------------------------------
323: -- MODE[TXBBM]
324: ----------------------------------------------------------------------------
325:
326: i_mode_txbbm_reg : memory_reg_rw
327: generic map(
328: data_width => 1 ,
329: reset_value => "0"
330: )
331: port map(
332: clk_sys => clk_sys ,-- in
333: rst_n => rst_n ,-- in
334: data_in => w_data(10 downto 10) ,-- in
335: write => write_en(1) ,-- in
336: cs => reg_sel(1) ,-- in
337: reg_value(0) => control_registers_out_i.mode_txbbm -- out
338: );
339:
340: ----------------------------------------------------------------------------
341: -- MODE[SAM]
342: ----------------------------------------------------------------------------
343:
344: i_mode_sam_reg : memory_reg_rw
345: generic map(
346: data_width => 1 ,
347: reset_value => "0"
348: )
349: port map(
350: clk_sys => clk_sys ,-- in
351: rst_n => rst_n ,-- in
352: data_in => w_data(11 downto 11) ,-- in
353: write => write_en(1) ,-- in
354: cs => reg_sel(1) ,-- in
355: reg_value(0) => control_registers_out_i.mode_sam -- out
356: );
357:
358: ----------------------------------------------------------------------------
359: -- MODE[ERFM]
360: ----------------------------------------------------------------------------
361:
362: i_mode_erfm_reg : memory_reg_rw
363: generic map(
364: data_width => 1 ,
365: reset_value => "0"
366: )
367: port map(
368: clk_sys => clk_sys ,-- in
369: rst_n => rst_n ,-- in
370: data_in => w_data(12 downto 12) ,-- in
371: write => write_en(1) ,-- in
372: cs => reg_sel(1) ,-- in
373: reg_value(0) => control_registers_out_i.mode_erfm -- out
374: );
375:
376: ----------------------------------------------------------------------------
377: -- SETTINGS[RTRLE]
378: ----------------------------------------------------------------------------
379:
380: i_settings_rtrle_reg : memory_reg_rw
381: generic map(
382: data_width => 1 ,
383: reset_value => "0"
384: )
385: port map(
386: clk_sys => clk_sys ,-- in
387: rst_n => rst_n ,-- in
388: data_in => w_data(16 downto 16) ,-- in
389: write => write_en(2) ,-- in
390: cs => reg_sel(1) ,-- in
391: reg_value(0) => control_registers_out_i.settings_rtrle -- out
392: );
393:
394: ----------------------------------------------------------------------------
395: -- SETTINGS[RTRTH]
396: ----------------------------------------------------------------------------
397:
398: i_settings_rtrth_reg : memory_reg_rw
399: generic map(
400: data_width => 4 ,
401: reset_value => "0000"
402: )
403: port map(
404: clk_sys => clk_sys ,-- in
405: rst_n => rst_n ,-- in
406: data_in => w_data(20 downto 17) ,-- in
407: write => write_en(2) ,-- in
408: cs => reg_sel(1) ,-- in
409: reg_value => control_registers_out_i.settings_rtrth -- out
410: );
411:
412: ----------------------------------------------------------------------------
413: -- SETTINGS[ILBP]
414: ----------------------------------------------------------------------------
415:
416: i_settings_ilbp_reg : memory_reg_rw
417: generic map(
418: data_width => 1 ,
419: reset_value => "0"
420: )
421: port map(
422: clk_sys => clk_sys ,-- in
423: rst_n => rst_n ,-- in
424: data_in => w_data(21 downto 21) ,-- in
425: write => write_en(2) ,-- in
426: cs => reg_sel(1) ,-- in
427: reg_value(0) => control_registers_out_i.settings_ilbp -- out
428: );
429:
430: ----------------------------------------------------------------------------
431: -- SETTINGS[ENA]
432: ----------------------------------------------------------------------------
433:
434: i_settings_ena_reg : memory_reg_rw
435: generic map(
436: data_width => 1 ,
437: reset_value => "0"
438: )
439: port map(
440: clk_sys => clk_sys ,-- in
441: rst_n => rst_n ,-- in
442: data_in => w_data(22 downto 22) ,-- in
443: write => write_en(2) ,-- in
444: cs => reg_sel(1) ,-- in
445: reg_value(0) => control_registers_out_i.settings_ena -- out
446: );
447:
448: ----------------------------------------------------------------------------
449: -- SETTINGS[NISOFD]
450: ----------------------------------------------------------------------------
451:
452: i_settings_nisofd_reg : memory_reg_rw
453: generic map(
454: data_width => 1 ,
455: reset_value => "0"
456: )
457: port map(
458: clk_sys => clk_sys ,-- in
459: rst_n => rst_n ,-- in
460: data_in => w_data(23 downto 23) ,-- in
461: write => write_en(2) ,-- in
462: cs => reg_sel(1) ,-- in
463: reg_value(0) => control_registers_out_i.settings_nisofd -- out
464: );
465:
466: ----------------------------------------------------------------------------
467: -- SETTINGS[PEX]
468: ----------------------------------------------------------------------------
469:
470: i_settings_pex_reg : memory_reg_rw
471: generic map(
472: data_width => 1 ,
473: reset_value => "0"
474: )
475: port map(
476: clk_sys => clk_sys ,-- in
477: rst_n => rst_n ,-- in
478: data_in => w_data(24 downto 24) ,-- in
479: write => write_en(3) ,-- in
480: cs => reg_sel(1) ,-- in
481: reg_value(0) => control_registers_out_i.settings_pex -- out
482: );
483:
484: ----------------------------------------------------------------------------
485: -- SETTINGS[TBFBO]
486: ----------------------------------------------------------------------------
487:
488: i_settings_tbfbo_reg : memory_reg_rw
489: generic map(
490: data_width => 1 ,
491: reset_value => "1"
492: )
493: port map(
494: clk_sys => clk_sys ,-- in
495: rst_n => rst_n ,-- in
496: data_in => w_data(25 downto 25) ,-- in
497: write => write_en(3) ,-- in
498: cs => reg_sel(1) ,-- in
499: reg_value(0) => control_registers_out_i.settings_tbfbo -- out
500: );
501:
502: ----------------------------------------------------------------------------
503: -- SETTINGS[FDRF]
504: ----------------------------------------------------------------------------
505:
506: i_settings_fdrf_reg : memory_reg_rw
507: generic map(
508: data_width => 1 ,
509: reset_value => "0"
510: )
511: port map(
512: clk_sys => clk_sys ,-- in
513: rst_n => rst_n ,-- in
514: data_in => w_data(26 downto 26) ,-- in
515: write => write_en(3) ,-- in
516: cs => reg_sel(1) ,-- in
517: reg_value(0) => control_registers_out_i.settings_fdrf -- out
518: );
519:
520: ----------------------------------------------------------------------------
521: -- SETTINGS[PCHKE]
522: ----------------------------------------------------------------------------
523:
524: i_settings_pchke_reg : memory_reg_rw
525: generic map(
526: data_width => 1 ,
527: reset_value => "0"
528: )
529: port map(
530: clk_sys => clk_sys ,-- in
531: rst_n => rst_n ,-- in
532: data_in => w_data(27 downto 27) ,-- in
533: write => write_en(3) ,-- in
534: cs => reg_sel(1) ,-- in
535: reg_value(0) => control_registers_out_i.settings_pchke -- out
536: );
537:
538: ----------------------------------------------------------------------------
539: -- COMMAND[RXRPMV]
540: ----------------------------------------------------------------------------
541:
542: i_command_rxrpmv_reg : memory_reg_os
543: generic map(
544: data_width => 1 ,
545: reset_value => "0"
546: )
547: port map(
548: clk_sys => clk_sys ,-- in
549: rst_n => rst_n ,-- in
550: data_in => w_data(1 downto 1) ,-- in
551: write => write_en(0) ,-- in
552: cs => reg_sel(3) ,-- in
553: reg_value(0) => control_registers_out_i.command_rxrpmv -- out
554: );
555:
556: ----------------------------------------------------------------------------
557: -- COMMAND[RRB]
558: ----------------------------------------------------------------------------
559:
560: i_command_rrb_reg : memory_reg_os
561: generic map(
562: data_width => 1 ,
563: reset_value => "0"
564: )
565: port map(
566: clk_sys => clk_sys ,-- in
567: rst_n => rst_n ,-- in
568: data_in => w_data(2 downto 2) ,-- in
569: write => write_en(0) ,-- in
570: cs => reg_sel(3) ,-- in
571: reg_value(0) => control_registers_out_i.command_rrb -- out
572: );
573:
574: ----------------------------------------------------------------------------
575: -- COMMAND[CDO]
576: ----------------------------------------------------------------------------
577:
578: i_command_cdo_reg : memory_reg_os
579: generic map(
580: data_width => 1 ,
581: reset_value => "0"
582: )
583: port map(
584: clk_sys => clk_sys ,-- in
585: rst_n => rst_n ,-- in
586: data_in => w_data(3 downto 3) ,-- in
587: write => write_en(0) ,-- in
588: cs => reg_sel(3) ,-- in
589: reg_value(0) => control_registers_out_i.command_cdo -- out
590: );
591:
592: ----------------------------------------------------------------------------
593: -- COMMAND[ERCRST]
594: ----------------------------------------------------------------------------
595:
596: i_command_ercrst_reg : memory_reg_os
597: generic map(
598: data_width => 1 ,
599: reset_value => "0"
600: )
601: port map(
602: clk_sys => clk_sys ,-- in
603: rst_n => rst_n ,-- in
604: data_in => w_data(4 downto 4) ,-- in
605: write => write_en(0) ,-- in
606: cs => reg_sel(3) ,-- in
607: reg_value(0) => control_registers_out_i.command_ercrst -- out
608: );
609:
610: ----------------------------------------------------------------------------
611: -- COMMAND[RXFCRST]
612: ----------------------------------------------------------------------------
613:
614: i_command_rxfcrst_reg : memory_reg_os
615: generic map(
616: data_width => 1 ,
617: reset_value => "0"
618: )
619: port map(
620: clk_sys => clk_sys ,-- in
621: rst_n => rst_n ,-- in
622: data_in => w_data(5 downto 5) ,-- in
623: write => write_en(0) ,-- in
624: cs => reg_sel(3) ,-- in
625: reg_value(0) => control_registers_out_i.command_rxfcrst -- out
626: );
627:
628: ----------------------------------------------------------------------------
629: -- COMMAND[TXFCRST]
630: ----------------------------------------------------------------------------
631:
632: i_command_txfcrst_reg : memory_reg_os
633: generic map(
634: data_width => 1 ,
635: reset_value => "0"
636: )
637: port map(
638: clk_sys => clk_sys ,-- in
639: rst_n => rst_n ,-- in
640: data_in => w_data(6 downto 6) ,-- in
641: write => write_en(0) ,-- in
642: cs => reg_sel(3) ,-- in
643: reg_value(0) => control_registers_out_i.command_txfcrst -- out
644: );
645:
646: ----------------------------------------------------------------------------
647: -- COMMAND[CPEXS]
648: ----------------------------------------------------------------------------
649:
650: i_command_cpexs_reg : memory_reg_os
651: generic map(
652: data_width => 1 ,
653: reset_value => "0"
654: )
655: port map(
656: clk_sys => clk_sys ,-- in
657: rst_n => rst_n ,-- in
658: data_in => w_data(7 downto 7) ,-- in
659: write => write_en(0) ,-- in
660: cs => reg_sel(3) ,-- in
661: reg_value(0) => control_registers_out_i.command_cpexs -- out
662: );
663:
664: ----------------------------------------------------------------------------
665: -- COMMAND[CRXPE]
666: ----------------------------------------------------------------------------
667:
668: i_command_crxpe_reg : memory_reg_os
669: generic map(
670: data_width => 1 ,
671: reset_value => "0"
672: )
673: port map(
674: clk_sys => clk_sys ,-- in
675: rst_n => rst_n ,-- in
676: data_in => w_data(8 downto 8) ,-- in
677: write => write_en(1) ,-- in
678: cs => reg_sel(3) ,-- in
679: reg_value(0) => control_registers_out_i.command_crxpe -- out
680: );
681:
682: ----------------------------------------------------------------------------
683: -- COMMAND[CTXPE]
684: ----------------------------------------------------------------------------
685:
686: i_command_ctxpe_reg : memory_reg_os
687: generic map(
688: data_width => 1 ,
689: reset_value => "0"
690: )
691: port map(
692: clk_sys => clk_sys ,-- in
693: rst_n => rst_n ,-- in
694: data_in => w_data(9 downto 9) ,-- in
695: write => write_en(1) ,-- in
696: cs => reg_sel(3) ,-- in
697: reg_value(0) => control_registers_out_i.command_ctxpe -- out
698: );
699:
700: ----------------------------------------------------------------------------
701: -- COMMAND[CTXDPE]
702: ----------------------------------------------------------------------------
703:
704: i_command_ctxdpe_reg : memory_reg_os
705: generic map(
706: data_width => 1 ,
707: reset_value => "0"
708: )
709: port map(
710: clk_sys => clk_sys ,-- in
711: rst_n => rst_n ,-- in
712: data_in => w_data(10 downto 10) ,-- in
713: write => write_en(1) ,-- in
714: cs => reg_sel(3) ,-- in
715: reg_value(0) => control_registers_out_i.command_ctxdpe -- out
716: );
717:
718: ----------------------------------------------------------------------------
719: -- INT_STAT[RXI]
720: ----------------------------------------------------------------------------
721:
722: i_int_stat_rxi_reg : memory_reg_os
723: generic map(
724: data_width => 1 ,
725: reset_value => "0"
726: )
727: port map(
728: clk_sys => clk_sys ,-- in
729: rst_n => rst_n ,-- in
730: data_in => w_data(0 downto 0) ,-- in
731: write => write_en(0) ,-- in
732: cs => reg_sel(4) ,-- in
733: reg_value(0) => control_registers_out_i.int_stat_rxi -- out
734: );
735:
736: ----------------------------------------------------------------------------
737: -- INT_STAT[TXI]
738: ----------------------------------------------------------------------------
739:
740: i_int_stat_txi_reg : memory_reg_os
741: generic map(
742: data_width => 1 ,
743: reset_value => "0"
744: )
745: port map(
746: clk_sys => clk_sys ,-- in
747: rst_n => rst_n ,-- in
748: data_in => w_data(1 downto 1) ,-- in
749: write => write_en(0) ,-- in
750: cs => reg_sel(4) ,-- in
751: reg_value(0) => control_registers_out_i.int_stat_txi -- out
752: );
753:
754: ----------------------------------------------------------------------------
755: -- INT_STAT[EWLI]
756: ----------------------------------------------------------------------------
757:
758: i_int_stat_ewli_reg : memory_reg_os
759: generic map(
760: data_width => 1 ,
761: reset_value => "0"
762: )
763: port map(
764: clk_sys => clk_sys ,-- in
765: rst_n => rst_n ,-- in
766: data_in => w_data(2 downto 2) ,-- in
767: write => write_en(0) ,-- in
768: cs => reg_sel(4) ,-- in
769: reg_value(0) => control_registers_out_i.int_stat_ewli -- out
770: );
771:
772: ----------------------------------------------------------------------------
773: -- INT_STAT[DOI]
774: ----------------------------------------------------------------------------
775:
776: i_int_stat_doi_reg : memory_reg_os
777: generic map(
778: data_width => 1 ,
779: reset_value => "0"
780: )
781: port map(
782: clk_sys => clk_sys ,-- in
783: rst_n => rst_n ,-- in
784: data_in => w_data(3 downto 3) ,-- in
785: write => write_en(0) ,-- in
786: cs => reg_sel(4) ,-- in
787: reg_value(0) => control_registers_out_i.int_stat_doi -- out
788: );
789:
790: ----------------------------------------------------------------------------
791: -- INT_STAT[FCSI]
792: ----------------------------------------------------------------------------
793:
794: i_int_stat_fcsi_reg : memory_reg_os
795: generic map(
796: data_width => 1 ,
797: reset_value => "0"
798: )
799: port map(
800: clk_sys => clk_sys ,-- in
801: rst_n => rst_n ,-- in
802: data_in => w_data(4 downto 4) ,-- in
803: write => write_en(0) ,-- in
804: cs => reg_sel(4) ,-- in
805: reg_value(0) => control_registers_out_i.int_stat_fcsi -- out
806: );
807:
808: ----------------------------------------------------------------------------
809: -- INT_STAT[ALI]
810: ----------------------------------------------------------------------------
811:
812: i_int_stat_ali_reg : memory_reg_os
813: generic map(
814: data_width => 1 ,
815: reset_value => "0"
816: )
817: port map(
818: clk_sys => clk_sys ,-- in
819: rst_n => rst_n ,-- in
820: data_in => w_data(5 downto 5) ,-- in
821: write => write_en(0) ,-- in
822: cs => reg_sel(4) ,-- in
823: reg_value(0) => control_registers_out_i.int_stat_ali -- out
824: );
825:
826: ----------------------------------------------------------------------------
827: -- INT_STAT[BEI]
828: ----------------------------------------------------------------------------
829:
830: i_int_stat_bei_reg : memory_reg_os
831: generic map(
832: data_width => 1 ,
833: reset_value => "0"
834: )
835: port map(
836: clk_sys => clk_sys ,-- in
837: rst_n => rst_n ,-- in
838: data_in => w_data(6 downto 6) ,-- in
839: write => write_en(0) ,-- in
840: cs => reg_sel(4) ,-- in
841: reg_value(0) => control_registers_out_i.int_stat_bei -- out
842: );
843:
844: ----------------------------------------------------------------------------
845: -- INT_STAT[OFI]
846: ----------------------------------------------------------------------------
847:
848: i_int_stat_ofi_reg : memory_reg_os
849: generic map(
850: data_width => 1 ,
851: reset_value => "0"
852: )
853: port map(
854: clk_sys => clk_sys ,-- in
855: rst_n => rst_n ,-- in
856: data_in => w_data(7 downto 7) ,-- in
857: write => write_en(0) ,-- in
858: cs => reg_sel(4) ,-- in
859: reg_value(0) => control_registers_out_i.int_stat_ofi -- out
860: );
861:
862: ----------------------------------------------------------------------------
863: -- INT_STAT[RXFI]
864: ----------------------------------------------------------------------------
865:
866: i_int_stat_rxfi_reg : memory_reg_os
867: generic map(
868: data_width => 1 ,
869: reset_value => "0"
870: )
871: port map(
872: clk_sys => clk_sys ,-- in
873: rst_n => rst_n ,-- in
874: data_in => w_data(8 downto 8) ,-- in
875: write => write_en(1) ,-- in
876: cs => reg_sel(4) ,-- in
877: reg_value(0) => control_registers_out_i.int_stat_rxfi -- out
878: );
879:
880: ----------------------------------------------------------------------------
881: -- INT_STAT[BSI]
882: ----------------------------------------------------------------------------
883:
884: i_int_stat_bsi_reg : memory_reg_os
885: generic map(
886: data_width => 1 ,
887: reset_value => "0"
888: )
889: port map(
890: clk_sys => clk_sys ,-- in
891: rst_n => rst_n ,-- in
892: data_in => w_data(9 downto 9) ,-- in
893: write => write_en(1) ,-- in
894: cs => reg_sel(4) ,-- in
895: reg_value(0) => control_registers_out_i.int_stat_bsi -- out
896: );
897:
898: ----------------------------------------------------------------------------
899: -- INT_STAT[RBNEI]
900: ----------------------------------------------------------------------------
901:
902: i_int_stat_rbnei_reg : memory_reg_os
903: generic map(
904: data_width => 1 ,
905: reset_value => "0"
906: )
907: port map(
908: clk_sys => clk_sys ,-- in
909: rst_n => rst_n ,-- in
910: data_in => w_data(10 downto 10) ,-- in
911: write => write_en(1) ,-- in
912: cs => reg_sel(4) ,-- in
913: reg_value(0) => control_registers_out_i.int_stat_rbnei -- out
914: );
915:
916: ----------------------------------------------------------------------------
917: -- INT_STAT[TXBHCI]
918: ----------------------------------------------------------------------------
919:
920: i_int_stat_txbhci_reg : memory_reg_os
921: generic map(
922: data_width => 1 ,
923: reset_value => "0"
924: )
925: port map(
926: clk_sys => clk_sys ,-- in
927: rst_n => rst_n ,-- in
928: data_in => w_data(11 downto 11) ,-- in
929: write => write_en(1) ,-- in
930: cs => reg_sel(4) ,-- in
931: reg_value(0) => control_registers_out_i.int_stat_txbhci -- out
932: );
933:
934: ----------------------------------------------------------------------------
935: -- INT_ENA_SET[INT_ENA_SET_SLICE_1]
936: ----------------------------------------------------------------------------
937:
938: i_int_ena_set_int_ena_set_slice_1_reg : memory_reg_os
939: generic map(
940: data_width => 8 ,
941: reset_value => "00000000"
942: )
943: port map(
944: clk_sys => clk_sys ,-- in
945: rst_n => rst_n ,-- in
946: data_in => w_data(7 downto 0) ,-- in
947: write => write_en(0) ,-- in
948: cs => reg_sel(5) ,-- in
949: reg_value => control_registers_out_i.int_ena_set_int_ena_set(7 downto 0) -- out
950: );
951:
952: ----------------------------------------------------------------------------
953: -- INT_ENA_SET[INT_ENA_SET_SLICE_2]
954: ----------------------------------------------------------------------------
955:
956: i_int_ena_set_int_ena_set_slice_2_reg : memory_reg_os
957: generic map(
958: data_width => 4 ,
959: reset_value => "0000"
960: )
961: port map(
962: clk_sys => clk_sys ,-- in
963: rst_n => rst_n ,-- in
964: data_in => w_data(11 downto 8) ,-- in
965: write => write_en(1) ,-- in
966: cs => reg_sel(5) ,-- in
967: reg_value => control_registers_out_i.int_ena_set_int_ena_set(11 downto 8) -- out
968: );
969:
970: ----------------------------------------------------------------------------
971: -- INT_ENA_CLR[INT_ENA_CLR_SLICE_1]
972: ----------------------------------------------------------------------------
973:
974: i_int_ena_clr_int_ena_clr_slice_1_reg : memory_reg_os
975: generic map(
976: data_width => 8 ,
977: reset_value => "00000000"
978: )
979: port map(
980: clk_sys => clk_sys ,-- in
981: rst_n => rst_n ,-- in
982: data_in => w_data(7 downto 0) ,-- in
983: write => write_en(0) ,-- in
984: cs => reg_sel(6) ,-- in
985: reg_value => control_registers_out_i.int_ena_clr_int_ena_clr(7 downto 0) -- out
986: );
987:
988: ----------------------------------------------------------------------------
989: -- INT_ENA_CLR[INT_ENA_CLR_SLICE_2]
990: ----------------------------------------------------------------------------
991:
992: i_int_ena_clr_int_ena_clr_slice_2_reg : memory_reg_os
993: generic map(
994: data_width => 4 ,
995: reset_value => "0000"
996: )
997: port map(
998: clk_sys => clk_sys ,-- in
999: rst_n => rst_n ,-- in
1000: data_in => w_data(11 downto 8) ,-- in
1001: write => write_en(1) ,-- in
1002: cs => reg_sel(6) ,-- in
1003: reg_value => control_registers_out_i.int_ena_clr_int_ena_clr(11 downto 8) -- out
1004: );
1005:
1006: ----------------------------------------------------------------------------
1007: -- INT_MASK_SET[INT_MASK_SET_SLICE_1]
1008: ----------------------------------------------------------------------------
1009:
1010: i_int_mask_set_int_mask_set_slice_1_reg : memory_reg_os
1011: generic map(
1012: data_width => 8 ,
1013: reset_value => "00000000"
1014: )
1015: port map(
1016: clk_sys => clk_sys ,-- in
1017: rst_n => rst_n ,-- in
1018: data_in => w_data(7 downto 0) ,-- in
1019: write => write_en(0) ,-- in
1020: cs => reg_sel(7) ,-- in
1021: reg_value => control_registers_out_i.int_mask_set_int_mask_set(7 downto 0) -- out
1022: );
1023:
1024: ----------------------------------------------------------------------------
1025: -- INT_MASK_SET[INT_MASK_SET_SLICE_2]
1026: ----------------------------------------------------------------------------
1027:
1028: i_int_mask_set_int_mask_set_slice_2_reg : memory_reg_os
1029: generic map(
1030: data_width => 4 ,
1031: reset_value => "0000"
1032: )
1033: port map(
1034: clk_sys => clk_sys ,-- in
1035: rst_n => rst_n ,-- in
1036: data_in => w_data(11 downto 8) ,-- in
1037: write => write_en(1) ,-- in
1038: cs => reg_sel(7) ,-- in
1039: reg_value => control_registers_out_i.int_mask_set_int_mask_set(11 downto 8) -- out
1040: );
1041:
1042: ----------------------------------------------------------------------------
1043: -- INT_MASK_CLR[INT_MASK_CLR_SLICE_1]
1044: ----------------------------------------------------------------------------
1045:
1046: i_int_mask_clr_int_mask_clr_slice_1_reg : memory_reg_os
1047: generic map(
1048: data_width => 8 ,
1049: reset_value => "00000000"
1050: )
1051: port map(
1052: clk_sys => clk_sys ,-- in
1053: rst_n => rst_n ,-- in
1054: data_in => w_data(7 downto 0) ,-- in
1055: write => write_en(0) ,-- in
1056: cs => reg_sel(8) ,-- in
1057: reg_value => control_registers_out_i.int_mask_clr_int_mask_clr(7 downto 0) -- out
1058: );
1059:
1060: ----------------------------------------------------------------------------
1061: -- INT_MASK_CLR[INT_MASK_CLR_SLICE_2]
1062: ----------------------------------------------------------------------------
1063:
1064: i_int_mask_clr_int_mask_clr_slice_2_reg : memory_reg_os
1065: generic map(
1066: data_width => 4 ,
1067: reset_value => "0000"
1068: )
1069: port map(
1070: clk_sys => clk_sys ,-- in
1071: rst_n => rst_n ,-- in
1072: data_in => w_data(11 downto 8) ,-- in
1073: write => write_en(1) ,-- in
1074: cs => reg_sel(8) ,-- in
1075: reg_value => control_registers_out_i.int_mask_clr_int_mask_clr(11 downto 8) -- out
1076: );
1077:
1078: ----------------------------------------------------------------------------
1079: -- BTR[PROP]
1080: ----------------------------------------------------------------------------
1081:
1082: i_btr_prop_reg : memory_reg_rw_lock
1083: generic map(
1084: data_width => 7 ,
1085: reset_value => "0000101"
1086: )
1087: port map(
1088: clk_sys => clk_sys ,-- in
1089: rst_n => rst_n ,-- in
1090: data_in => w_data(6 downto 0) ,-- in
1091: write => write_en(0) ,-- in
1092: cs => reg_sel(9) ,-- in
1093: lock => lock_2 ,-- in
1094: reg_value => control_registers_out_i.btr_prop -- out
1095: );
1096:
1097: ----------------------------------------------------------------------------
1098: -- BTR[PH1_SLICE_1]
1099: ----------------------------------------------------------------------------
1100:
1101: i_btr_ph1_slice_1_reg : memory_reg_rw_lock
1102: generic map(
1103: data_width => 1 ,
1104: reset_value => "1"
1105: )
1106: port map(
1107: clk_sys => clk_sys ,-- in
1108: rst_n => rst_n ,-- in
1109: data_in => w_data(7 downto 7) ,-- in
1110: write => write_en(0) ,-- in
1111: cs => reg_sel(9) ,-- in
1112: lock => lock_2 ,-- in
1113: reg_value(0) => control_registers_out_i.btr_ph1(0) -- out
1114: );
1115:
1116: ----------------------------------------------------------------------------
1117: -- BTR[PH1_SLICE_2]
1118: ----------------------------------------------------------------------------
1119:
1120: i_btr_ph1_slice_2_reg : memory_reg_rw_lock
1121: generic map(
1122: data_width => 5 ,
1123: reset_value => "00001"
1124: )
1125: port map(
1126: clk_sys => clk_sys ,-- in
1127: rst_n => rst_n ,-- in
1128: data_in => w_data(12 downto 8) ,-- in
1129: write => write_en(1) ,-- in
1130: cs => reg_sel(9) ,-- in
1131: lock => lock_2 ,-- in
1132: reg_value => control_registers_out_i.btr_ph1(5 downto 1) -- out
1133: );
1134:
1135: ----------------------------------------------------------------------------
1136: -- BTR[PH2_SLICE_1]
1137: ----------------------------------------------------------------------------
1138:
1139: i_btr_ph2_slice_1_reg : memory_reg_rw_lock
1140: generic map(
1141: data_width => 3 ,
1142: reset_value => "101"
1143: )
1144: port map(
1145: clk_sys => clk_sys ,-- in
1146: rst_n => rst_n ,-- in
1147: data_in => w_data(15 downto 13) ,-- in
1148: write => write_en(1) ,-- in
1149: cs => reg_sel(9) ,-- in
1150: lock => lock_2 ,-- in
1151: reg_value => control_registers_out_i.btr_ph2(2 downto 0) -- out
1152: );
1153:
1154: ----------------------------------------------------------------------------
1155: -- BTR[PH2_SLICE_2]
1156: ----------------------------------------------------------------------------
1157:
1158: i_btr_ph2_slice_2_reg : memory_reg_rw_lock
1159: generic map(
1160: data_width => 3 ,
1161: reset_value => "000"
1162: )
1163: port map(
1164: clk_sys => clk_sys ,-- in
1165: rst_n => rst_n ,-- in
1166: data_in => w_data(18 downto 16) ,-- in
1167: write => write_en(2) ,-- in
1168: cs => reg_sel(9) ,-- in
1169: lock => lock_2 ,-- in
1170: reg_value => control_registers_out_i.btr_ph2(5 downto 3) -- out
1171: );
1172:
1173: ----------------------------------------------------------------------------
1174: -- BTR[BRP_SLICE_1]
1175: ----------------------------------------------------------------------------
1176:
1177: i_btr_brp_slice_1_reg : memory_reg_rw_lock
1178: generic map(
1179: data_width => 5 ,
1180: reset_value => "01010"
1181: )
1182: port map(
1183: clk_sys => clk_sys ,-- in
1184: rst_n => rst_n ,-- in
1185: data_in => w_data(23 downto 19) ,-- in
1186: write => write_en(2) ,-- in
1187: cs => reg_sel(9) ,-- in
1188: lock => lock_2 ,-- in
1189: reg_value => control_registers_out_i.btr_brp(4 downto 0) -- out
1190: );
1191:
1192: ----------------------------------------------------------------------------
1193: -- BTR[BRP_SLICE_2]
1194: ----------------------------------------------------------------------------
1195:
1196: i_btr_brp_slice_2_reg : memory_reg_rw_lock
1197: generic map(
1198: data_width => 3 ,
1199: reset_value => "000"
1200: )
1201: port map(
1202: clk_sys => clk_sys ,-- in
1203: rst_n => rst_n ,-- in
1204: data_in => w_data(26 downto 24) ,-- in
1205: write => write_en(3) ,-- in
1206: cs => reg_sel(9) ,-- in
1207: lock => lock_2 ,-- in
1208: reg_value => control_registers_out_i.btr_brp(7 downto 5) -- out
1209: );
1210:
1211: ----------------------------------------------------------------------------
1212: -- BTR[SJW]
1213: ----------------------------------------------------------------------------
1214:
1215: i_btr_sjw_reg : memory_reg_rw_lock
1216: generic map(
1217: data_width => 5 ,
1218: reset_value => "00010"
1219: )
1220: port map(
1221: clk_sys => clk_sys ,-- in
1222: rst_n => rst_n ,-- in
1223: data_in => w_data(31 downto 27) ,-- in
1224: write => write_en(3) ,-- in
1225: cs => reg_sel(9) ,-- in
1226: lock => lock_2 ,-- in
1227: reg_value => control_registers_out_i.btr_sjw -- out
1228: );
1229:
1230: ----------------------------------------------------------------------------
1231: -- BTR_FD[PROP_FD]
1232: ----------------------------------------------------------------------------
1233:
1234: i_btr_fd_prop_fd_reg : memory_reg_rw_lock
1235: generic map(
1236: data_width => 6 ,
1237: reset_value => "000011"
1238: )
1239: port map(
1240: clk_sys => clk_sys ,-- in
1241: rst_n => rst_n ,-- in
1242: data_in => w_data(5 downto 0) ,-- in
1243: write => write_en(0) ,-- in
1244: cs => reg_sel(10) ,-- in
1245: lock => lock_2 ,-- in
1246: reg_value => control_registers_out_i.btr_fd_prop_fd -- out
1247: );
1248:
1249: ----------------------------------------------------------------------------
1250: -- BTR_FD[PH1_FD_SLICE_1]
1251: ----------------------------------------------------------------------------
1252:
1253: i_btr_fd_ph1_fd_slice_1_reg : memory_reg_rw_lock
1254: generic map(
1255: data_width => 1 ,
1256: reset_value => "1"
1257: )
1258: port map(
1259: clk_sys => clk_sys ,-- in
1260: rst_n => rst_n ,-- in
1261: data_in => w_data(7 downto 7) ,-- in
1262: write => write_en(0) ,-- in
1263: cs => reg_sel(10) ,-- in
1264: lock => lock_2 ,-- in
1265: reg_value(0) => control_registers_out_i.btr_fd_ph1_fd(0) -- out
1266: );
1267:
1268: ----------------------------------------------------------------------------
1269: -- BTR_FD[PH1_FD_SLICE_2]
1270: ----------------------------------------------------------------------------
1271:
1272: i_btr_fd_ph1_fd_slice_2_reg : memory_reg_rw_lock
1273: generic map(
1274: data_width => 4 ,
1275: reset_value => "0001"
1276: )
1277: port map(
1278: clk_sys => clk_sys ,-- in
1279: rst_n => rst_n ,-- in
1280: data_in => w_data(11 downto 8) ,-- in
1281: write => write_en(1) ,-- in
1282: cs => reg_sel(10) ,-- in
1283: lock => lock_2 ,-- in
1284: reg_value => control_registers_out_i.btr_fd_ph1_fd(4 downto 1) -- out
1285: );
1286:
1287: ----------------------------------------------------------------------------
1288: -- BTR_FD[PH2_FD_SLICE_1]
1289: ----------------------------------------------------------------------------
1290:
1291: i_btr_fd_ph2_fd_slice_1_reg : memory_reg_rw_lock
1292: generic map(
1293: data_width => 3 ,
1294: reset_value => "011"
1295: )
1296: port map(
1297: clk_sys => clk_sys ,-- in
1298: rst_n => rst_n ,-- in
1299: data_in => w_data(15 downto 13) ,-- in
1300: write => write_en(1) ,-- in
1301: cs => reg_sel(10) ,-- in
1302: lock => lock_2 ,-- in
1303: reg_value => control_registers_out_i.btr_fd_ph2_fd(2 downto 0) -- out
1304: );
1305:
1306: ----------------------------------------------------------------------------
1307: -- BTR_FD[PH2_FD_SLICE_2]
1308: ----------------------------------------------------------------------------
1309:
1310: i_btr_fd_ph2_fd_slice_2_reg : memory_reg_rw_lock
1311: generic map(
1312: data_width => 2 ,
1313: reset_value => "00"
1314: )
1315: port map(
1316: clk_sys => clk_sys ,-- in
1317: rst_n => rst_n ,-- in
1318: data_in => w_data(17 downto 16) ,-- in
1319: write => write_en(2) ,-- in
1320: cs => reg_sel(10) ,-- in
1321: lock => lock_2 ,-- in
1322: reg_value => control_registers_out_i.btr_fd_ph2_fd(4 downto 3) -- out
1323: );
1324:
1325: ----------------------------------------------------------------------------
1326: -- BTR_FD[BRP_FD_SLICE_1]
1327: ----------------------------------------------------------------------------
1328:
1329: i_btr_fd_brp_fd_slice_1_reg : memory_reg_rw_lock
1330: generic map(
1331: data_width => 5 ,
1332: reset_value => "00100"
1333: )
1334: port map(
1335: clk_sys => clk_sys ,-- in
1336: rst_n => rst_n ,-- in
1337: data_in => w_data(23 downto 19) ,-- in
1338: write => write_en(2) ,-- in
1339: cs => reg_sel(10) ,-- in
1340: lock => lock_2 ,-- in
1341: reg_value => control_registers_out_i.btr_fd_brp_fd(4 downto 0) -- out
1342: );
1343:
1344: ----------------------------------------------------------------------------
1345: -- BTR_FD[BRP_FD_SLICE_2]
1346: ----------------------------------------------------------------------------
1347:
1348: i_btr_fd_brp_fd_slice_2_reg : memory_reg_rw_lock
1349: generic map(
1350: data_width => 3 ,
1351: reset_value => "000"
1352: )
1353: port map(
1354: clk_sys => clk_sys ,-- in
1355: rst_n => rst_n ,-- in
1356: data_in => w_data(26 downto 24) ,-- in
1357: write => write_en(3) ,-- in
1358: cs => reg_sel(10) ,-- in
1359: lock => lock_2 ,-- in
1360: reg_value => control_registers_out_i.btr_fd_brp_fd(7 downto 5) -- out
1361: );
1362:
1363: ----------------------------------------------------------------------------
1364: -- BTR_FD[SJW_FD]
1365: ----------------------------------------------------------------------------
1366:
1367: i_btr_fd_sjw_fd_reg : memory_reg_rw_lock
1368: generic map(
1369: data_width => 5 ,
1370: reset_value => "00010"
1371: )
1372: port map(
1373: clk_sys => clk_sys ,-- in
1374: rst_n => rst_n ,-- in
1375: data_in => w_data(31 downto 27) ,-- in
1376: write => write_en(3) ,-- in
1377: cs => reg_sel(10) ,-- in
1378: lock => lock_2 ,-- in
1379: reg_value => control_registers_out_i.btr_fd_sjw_fd -- out
1380: );
1381:
1382: ----------------------------------------------------------------------------
1383: -- EWL[EW_LIMIT]
1384: ----------------------------------------------------------------------------
1385:
1386: i_ewl_ew_limit_reg : memory_reg_rw_lock
1387: generic map(
1388: data_width => 8 ,
1389: reset_value => "01100000"
1390: )
1391: port map(
1392: clk_sys => clk_sys ,-- in
1393: rst_n => rst_n ,-- in
1394: data_in => w_data(7 downto 0) ,-- in
1395: write => write_en(0) ,-- in
1396: cs => reg_sel(11) ,-- in
1397: lock => lock_1 ,-- in
1398: reg_value => control_registers_out_i.ewl_ew_limit -- out
1399: );
1400:
1401: ----------------------------------------------------------------------------
1402: -- ERP[ERP_LIMIT]
1403: ----------------------------------------------------------------------------
1404:
1405: i_erp_erp_limit_reg : memory_reg_rw_lock
1406: generic map(
1407: data_width => 8 ,
1408: reset_value => "10000000"
1409: )
1410: port map(
1411: clk_sys => clk_sys ,-- in
1412: rst_n => rst_n ,-- in
1413: data_in => w_data(15 downto 8) ,-- in
1414: write => write_en(1) ,-- in
1415: cs => reg_sel(11) ,-- in
1416: lock => lock_1 ,-- in
1417: reg_value => control_registers_out_i.erp_erp_limit -- out
1418: );
1419:
1420: ----------------------------------------------------------------------------
1421: -- CTR_PRES[CTPV_SLICE_1]
1422: ----------------------------------------------------------------------------
1423:
1424: i_ctr_pres_ctpv_slice_1_reg : memory_reg_rw_lock
1425: generic map(
1426: data_width => 8 ,
1427: reset_value => "00000000"
1428: )
1429: port map(
1430: clk_sys => clk_sys ,-- in
1431: rst_n => rst_n ,-- in
1432: data_in => w_data(7 downto 0) ,-- in
1433: write => write_en(0) ,-- in
1434: cs => reg_sel(14) ,-- in
1435: lock => lock_1 ,-- in
1436: reg_value => control_registers_out_i.ctr_pres_ctpv(7 downto 0) -- out
1437: );
1438:
1439: ----------------------------------------------------------------------------
1440: -- CTR_PRES[CTPV_SLICE_2]
1441: ----------------------------------------------------------------------------
1442:
1443: i_ctr_pres_ctpv_slice_2_reg : memory_reg_rw_lock
1444: generic map(
1445: data_width => 1 ,
1446: reset_value => "0"
1447: )
1448: port map(
1449: clk_sys => clk_sys ,-- in
1450: rst_n => rst_n ,-- in
1451: data_in => w_data(8 downto 8) ,-- in
1452: write => write_en(1) ,-- in
1453: cs => reg_sel(14) ,-- in
1454: lock => lock_1 ,-- in
1455: reg_value(0) => control_registers_out_i.ctr_pres_ctpv(8) -- out
1456: );
1457:
1458: ----------------------------------------------------------------------------
1459: -- CTR_PRES[PTX]
1460: ----------------------------------------------------------------------------
1461:
1462: i_ctr_pres_ptx_reg : memory_reg_os_lock
1463: generic map(
1464: data_width => 1 ,
1465: reset_value => "0"
1466: )
1467: port map(
1468: clk_sys => clk_sys ,-- in
1469: rst_n => rst_n ,-- in
1470: data_in => w_data(9 downto 9) ,-- in
1471: write => write_en(1) ,-- in
1472: cs => reg_sel(14) ,-- in
1473: lock => lock_1 ,-- in
1474: reg_value(0) => control_registers_out_i.ctr_pres_ptx -- out
1475: );
1476:
1477: ----------------------------------------------------------------------------
1478: -- CTR_PRES[PRX]
1479: ----------------------------------------------------------------------------
1480:
1481: i_ctr_pres_prx_reg : memory_reg_os_lock
1482: generic map(
1483: data_width => 1 ,
1484: reset_value => "0"
1485: )
1486: port map(
1487: clk_sys => clk_sys ,-- in
1488: rst_n => rst_n ,-- in
1489: data_in => w_data(10 downto 10) ,-- in
1490: write => write_en(1) ,-- in
1491: cs => reg_sel(14) ,-- in
1492: lock => lock_1 ,-- in
1493: reg_value(0) => control_registers_out_i.ctr_pres_prx -- out
1494: );
1495:
1496: ----------------------------------------------------------------------------
1497: -- CTR_PRES[ENORM]
1498: ----------------------------------------------------------------------------
1499:
1500: i_ctr_pres_enorm_reg : memory_reg_os_lock
1501: generic map(
1502: data_width => 1 ,
1503: reset_value => "0"
1504: )
1505: port map(
1506: clk_sys => clk_sys ,-- in
1507: rst_n => rst_n ,-- in
1508: data_in => w_data(11 downto 11) ,-- in
1509: write => write_en(1) ,-- in
1510: cs => reg_sel(14) ,-- in
1511: lock => lock_1 ,-- in
1512: reg_value(0) => control_registers_out_i.ctr_pres_enorm -- out
1513: );
1514:
1515: ----------------------------------------------------------------------------
1516: -- CTR_PRES[EFD]
1517: ----------------------------------------------------------------------------
1518:
1519: i_ctr_pres_efd_reg : memory_reg_os_lock
1520: generic map(
1521: data_width => 1 ,
1522: reset_value => "0"
1523: )
1524: port map(
1525: clk_sys => clk_sys ,-- in
1526: rst_n => rst_n ,-- in
1527: data_in => w_data(12 downto 12) ,-- in
1528: write => write_en(1) ,-- in
1529: cs => reg_sel(14) ,-- in
1530: lock => lock_1 ,-- in
1531: reg_value(0) => control_registers_out_i.ctr_pres_efd -- out
1532: );
1533:
1534: ----------------------------------------------------------------------------
1535: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_1]
1536: ----------------------------------------------------------------------------
1537: g_filter_a_mask_bit_mask_a_val_slice_1_t : if (G_FILT_A_EN) generate
1538:
1539: i_filter_a_mask_bit_mask_a_val_slice_1_reg : memory_reg_rw
1540: generic map(
1541: data_width => 8 ,
1542: reset_value => "00000000"
1543: )
1544: port map(
1545: clk_sys => clk_sys ,-- in
1546: rst_n => rst_n ,-- in
1547: data_in => w_data(7 downto 0) ,-- in
1548: write => write_en(0) ,-- in
1549: cs => reg_sel(15) ,-- in
1550: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(7 downto 0) -- out
1551: );
1552:
1553: end generate g_filter_a_mask_bit_mask_a_val_slice_1_t;
1554:
1555: g_filter_a_mask_bit_mask_a_val_slice_1_f : if (not(G_FILT_A_EN)) generate
1556: control_registers_out_i.filter_a_mask_bit_mask_a_val(7 downto 0) <= (others => '0');
1557: end generate g_filter_a_mask_bit_mask_a_val_slice_1_f;
1558:
1559: ----------------------------------------------------------------------------
1560: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_2]
1561: ----------------------------------------------------------------------------
1562: g_filter_a_mask_bit_mask_a_val_slice_2_t : if (G_FILT_A_EN) generate
1563:
1564: i_filter_a_mask_bit_mask_a_val_slice_2_reg : memory_reg_rw
1565: generic map(
1566: data_width => 8 ,
1567: reset_value => "00000000"
1568: )
1569: port map(
1570: clk_sys => clk_sys ,-- in
1571: rst_n => rst_n ,-- in
1572: data_in => w_data(15 downto 8) ,-- in
1573: write => write_en(1) ,-- in
1574: cs => reg_sel(15) ,-- in
1575: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(15 downto 8) -- out
1576: );
1577:
1578: end generate g_filter_a_mask_bit_mask_a_val_slice_2_t;
1579:
1580: g_filter_a_mask_bit_mask_a_val_slice_2_f : if (not(G_FILT_A_EN)) generate
1581: control_registers_out_i.filter_a_mask_bit_mask_a_val(15 downto 8) <= (others => '0');
1582: end generate g_filter_a_mask_bit_mask_a_val_slice_2_f;
1583:
1584: ----------------------------------------------------------------------------
1585: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_3]
1586: ----------------------------------------------------------------------------
1587: g_filter_a_mask_bit_mask_a_val_slice_3_t : if (G_FILT_A_EN) generate
1588:
1589: i_filter_a_mask_bit_mask_a_val_slice_3_reg : memory_reg_rw
1590: generic map(
1591: data_width => 8 ,
1592: reset_value => "00000000"
1593: )
1594: port map(
1595: clk_sys => clk_sys ,-- in
1596: rst_n => rst_n ,-- in
1597: data_in => w_data(23 downto 16) ,-- in
1598: write => write_en(2) ,-- in
1599: cs => reg_sel(15) ,-- in
1600: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(23 downto 16) -- out
1601: );
1602:
1603: end generate g_filter_a_mask_bit_mask_a_val_slice_3_t;
1604:
1605: g_filter_a_mask_bit_mask_a_val_slice_3_f : if (not(G_FILT_A_EN)) generate
1606: control_registers_out_i.filter_a_mask_bit_mask_a_val(23 downto 16) <= (others => '0');
1607: end generate g_filter_a_mask_bit_mask_a_val_slice_3_f;
1608:
1609: ----------------------------------------------------------------------------
1610: -- FILTER_A_MASK[BIT_MASK_A_VAL_SLICE_4]
1611: ----------------------------------------------------------------------------
1612: g_filter_a_mask_bit_mask_a_val_slice_4_t : if (G_FILT_A_EN) generate
1613:
1614: i_filter_a_mask_bit_mask_a_val_slice_4_reg : memory_reg_rw
1615: generic map(
1616: data_width => 5 ,
1617: reset_value => "00000"
1618: )
1619: port map(
1620: clk_sys => clk_sys ,-- in
1621: rst_n => rst_n ,-- in
1622: data_in => w_data(28 downto 24) ,-- in
1623: write => write_en(3) ,-- in
1624: cs => reg_sel(15) ,-- in
1625: reg_value => control_registers_out_i.filter_a_mask_bit_mask_a_val(28 downto 24) -- out
1626: );
1627:
1628: end generate g_filter_a_mask_bit_mask_a_val_slice_4_t;
1629:
1630: g_filter_a_mask_bit_mask_a_val_slice_4_f : if (not(G_FILT_A_EN)) generate
1631: control_registers_out_i.filter_a_mask_bit_mask_a_val(28 downto 24) <= (others => '0');
1632: end generate g_filter_a_mask_bit_mask_a_val_slice_4_f;
1633:
1634: ----------------------------------------------------------------------------
1635: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_1]
1636: ----------------------------------------------------------------------------
1637: g_filter_a_val_bit_val_a_val_slice_1_t : if (G_FILT_A_EN) generate
1638:
1639: i_filter_a_val_bit_val_a_val_slice_1_reg : memory_reg_rw
1640: generic map(
1641: data_width => 8 ,
1642: reset_value => "00000000"
1643: )
1644: port map(
1645: clk_sys => clk_sys ,-- in
1646: rst_n => rst_n ,-- in
1647: data_in => w_data(7 downto 0) ,-- in
1648: write => write_en(0) ,-- in
1649: cs => reg_sel(16) ,-- in
1650: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(7 downto 0) -- out
1651: );
1652:
1653: end generate g_filter_a_val_bit_val_a_val_slice_1_t;
1654:
1655: g_filter_a_val_bit_val_a_val_slice_1_f : if (not(G_FILT_A_EN)) generate
1656: control_registers_out_i.filter_a_val_bit_val_a_val(7 downto 0) <= (others => '0');
1657: end generate g_filter_a_val_bit_val_a_val_slice_1_f;
1658:
1659: ----------------------------------------------------------------------------
1660: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_2]
1661: ----------------------------------------------------------------------------
1662: g_filter_a_val_bit_val_a_val_slice_2_t : if (G_FILT_A_EN) generate
1663:
1664: i_filter_a_val_bit_val_a_val_slice_2_reg : memory_reg_rw
1665: generic map(
1666: data_width => 8 ,
1667: reset_value => "00000000"
1668: )
1669: port map(
1670: clk_sys => clk_sys ,-- in
1671: rst_n => rst_n ,-- in
1672: data_in => w_data(15 downto 8) ,-- in
1673: write => write_en(1) ,-- in
1674: cs => reg_sel(16) ,-- in
1675: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(15 downto 8) -- out
1676: );
1677:
1678: end generate g_filter_a_val_bit_val_a_val_slice_2_t;
1679:
1680: g_filter_a_val_bit_val_a_val_slice_2_f : if (not(G_FILT_A_EN)) generate
1681: control_registers_out_i.filter_a_val_bit_val_a_val(15 downto 8) <= (others => '0');
1682: end generate g_filter_a_val_bit_val_a_val_slice_2_f;
1683:
1684: ----------------------------------------------------------------------------
1685: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_3]
1686: ----------------------------------------------------------------------------
1687: g_filter_a_val_bit_val_a_val_slice_3_t : if (G_FILT_A_EN) generate
1688:
1689: i_filter_a_val_bit_val_a_val_slice_3_reg : memory_reg_rw
1690: generic map(
1691: data_width => 8 ,
1692: reset_value => "00000000"
1693: )
1694: port map(
1695: clk_sys => clk_sys ,-- in
1696: rst_n => rst_n ,-- in
1697: data_in => w_data(23 downto 16) ,-- in
1698: write => write_en(2) ,-- in
1699: cs => reg_sel(16) ,-- in
1700: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(23 downto 16) -- out
1701: );
1702:
1703: end generate g_filter_a_val_bit_val_a_val_slice_3_t;
1704:
1705: g_filter_a_val_bit_val_a_val_slice_3_f : if (not(G_FILT_A_EN)) generate
1706: control_registers_out_i.filter_a_val_bit_val_a_val(23 downto 16) <= (others => '0');
1707: end generate g_filter_a_val_bit_val_a_val_slice_3_f;
1708:
1709: ----------------------------------------------------------------------------
1710: -- FILTER_A_VAL[BIT_VAL_A_VAL_SLICE_4]
1711: ----------------------------------------------------------------------------
1712: g_filter_a_val_bit_val_a_val_slice_4_t : if (G_FILT_A_EN) generate
1713:
1714: i_filter_a_val_bit_val_a_val_slice_4_reg : memory_reg_rw
1715: generic map(
1716: data_width => 5 ,
1717: reset_value => "00000"
1718: )
1719: port map(
1720: clk_sys => clk_sys ,-- in
1721: rst_n => rst_n ,-- in
1722: data_in => w_data(28 downto 24) ,-- in
1723: write => write_en(3) ,-- in
1724: cs => reg_sel(16) ,-- in
1725: reg_value => control_registers_out_i.filter_a_val_bit_val_a_val(28 downto 24) -- out
1726: );
1727:
1728: end generate g_filter_a_val_bit_val_a_val_slice_4_t;
1729:
1730: g_filter_a_val_bit_val_a_val_slice_4_f : if (not(G_FILT_A_EN)) generate
1731: control_registers_out_i.filter_a_val_bit_val_a_val(28 downto 24) <= (others => '0');
1732: end generate g_filter_a_val_bit_val_a_val_slice_4_f;
1733:
1734: ----------------------------------------------------------------------------
1735: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_1]
1736: ----------------------------------------------------------------------------
1737: g_filter_b_mask_bit_mask_b_val_slice_1_t : if (G_FILT_B_EN) generate
1738:
1739: i_filter_b_mask_bit_mask_b_val_slice_1_reg : memory_reg_rw
1740: generic map(
1741: data_width => 8 ,
1742: reset_value => "00000000"
1743: )
1744: port map(
1745: clk_sys => clk_sys ,-- in
1746: rst_n => rst_n ,-- in
1747: data_in => w_data(7 downto 0) ,-- in
1748: write => write_en(0) ,-- in
1749: cs => reg_sel(17) ,-- in
1750: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(7 downto 0) -- out
1751: );
1752:
1753: end generate g_filter_b_mask_bit_mask_b_val_slice_1_t;
1754:
1755: g_filter_b_mask_bit_mask_b_val_slice_1_f : if (not(G_FILT_B_EN)) generate
1756: control_registers_out_i.filter_b_mask_bit_mask_b_val(7 downto 0) <= (others => '0');
1757: end generate g_filter_b_mask_bit_mask_b_val_slice_1_f;
1758:
1759: ----------------------------------------------------------------------------
1760: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_2]
1761: ----------------------------------------------------------------------------
1762: g_filter_b_mask_bit_mask_b_val_slice_2_t : if (G_FILT_B_EN) generate
1763:
1764: i_filter_b_mask_bit_mask_b_val_slice_2_reg : memory_reg_rw
1765: generic map(
1766: data_width => 8 ,
1767: reset_value => "00000000"
1768: )
1769: port map(
1770: clk_sys => clk_sys ,-- in
1771: rst_n => rst_n ,-- in
1772: data_in => w_data(15 downto 8) ,-- in
1773: write => write_en(1) ,-- in
1774: cs => reg_sel(17) ,-- in
1775: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(15 downto 8) -- out
1776: );
1777:
1778: end generate g_filter_b_mask_bit_mask_b_val_slice_2_t;
1779:
1780: g_filter_b_mask_bit_mask_b_val_slice_2_f : if (not(G_FILT_B_EN)) generate
1781: control_registers_out_i.filter_b_mask_bit_mask_b_val(15 downto 8) <= (others => '0');
1782: end generate g_filter_b_mask_bit_mask_b_val_slice_2_f;
1783:
1784: ----------------------------------------------------------------------------
1785: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_3]
1786: ----------------------------------------------------------------------------
1787: g_filter_b_mask_bit_mask_b_val_slice_3_t : if (G_FILT_B_EN) generate
1788:
1789: i_filter_b_mask_bit_mask_b_val_slice_3_reg : memory_reg_rw
1790: generic map(
1791: data_width => 8 ,
1792: reset_value => "00000000"
1793: )
1794: port map(
1795: clk_sys => clk_sys ,-- in
1796: rst_n => rst_n ,-- in
1797: data_in => w_data(23 downto 16) ,-- in
1798: write => write_en(2) ,-- in
1799: cs => reg_sel(17) ,-- in
1800: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(23 downto 16) -- out
1801: );
1802:
1803: end generate g_filter_b_mask_bit_mask_b_val_slice_3_t;
1804:
1805: g_filter_b_mask_bit_mask_b_val_slice_3_f : if (not(G_FILT_B_EN)) generate
1806: control_registers_out_i.filter_b_mask_bit_mask_b_val(23 downto 16) <= (others => '0');
1807: end generate g_filter_b_mask_bit_mask_b_val_slice_3_f;
1808:
1809: ----------------------------------------------------------------------------
1810: -- FILTER_B_MASK[BIT_MASK_B_VAL_SLICE_4]
1811: ----------------------------------------------------------------------------
1812: g_filter_b_mask_bit_mask_b_val_slice_4_t : if (G_FILT_B_EN) generate
1813:
1814: i_filter_b_mask_bit_mask_b_val_slice_4_reg : memory_reg_rw
1815: generic map(
1816: data_width => 5 ,
1817: reset_value => "00000"
1818: )
1819: port map(
1820: clk_sys => clk_sys ,-- in
1821: rst_n => rst_n ,-- in
1822: data_in => w_data(28 downto 24) ,-- in
1823: write => write_en(3) ,-- in
1824: cs => reg_sel(17) ,-- in
1825: reg_value => control_registers_out_i.filter_b_mask_bit_mask_b_val(28 downto 24) -- out
1826: );
1827:
1828: end generate g_filter_b_mask_bit_mask_b_val_slice_4_t;
1829:
1830: g_filter_b_mask_bit_mask_b_val_slice_4_f : if (not(G_FILT_B_EN)) generate
1831: control_registers_out_i.filter_b_mask_bit_mask_b_val(28 downto 24) <= (others => '0');
1832: end generate g_filter_b_mask_bit_mask_b_val_slice_4_f;
1833:
1834: ----------------------------------------------------------------------------
1835: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_1]
1836: ----------------------------------------------------------------------------
1837: g_filter_b_val_bit_val_b_val_slice_1_t : if (G_FILT_B_EN) generate
1838:
1839: i_filter_b_val_bit_val_b_val_slice_1_reg : memory_reg_rw
1840: generic map(
1841: data_width => 8 ,
1842: reset_value => "00000000"
1843: )
1844: port map(
1845: clk_sys => clk_sys ,-- in
1846: rst_n => rst_n ,-- in
1847: data_in => w_data(7 downto 0) ,-- in
1848: write => write_en(0) ,-- in
1849: cs => reg_sel(18) ,-- in
1850: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(7 downto 0) -- out
1851: );
1852:
1853: end generate g_filter_b_val_bit_val_b_val_slice_1_t;
1854:
1855: g_filter_b_val_bit_val_b_val_slice_1_f : if (not(G_FILT_B_EN)) generate
1856: control_registers_out_i.filter_b_val_bit_val_b_val(7 downto 0) <= (others => '0');
1857: end generate g_filter_b_val_bit_val_b_val_slice_1_f;
1858:
1859: ----------------------------------------------------------------------------
1860: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_2]
1861: ----------------------------------------------------------------------------
1862: g_filter_b_val_bit_val_b_val_slice_2_t : if (G_FILT_B_EN) generate
1863:
1864: i_filter_b_val_bit_val_b_val_slice_2_reg : memory_reg_rw
1865: generic map(
1866: data_width => 8 ,
1867: reset_value => "00000000"
1868: )
1869: port map(
1870: clk_sys => clk_sys ,-- in
1871: rst_n => rst_n ,-- in
1872: data_in => w_data(15 downto 8) ,-- in
1873: write => write_en(1) ,-- in
1874: cs => reg_sel(18) ,-- in
1875: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(15 downto 8) -- out
1876: );
1877:
1878: end generate g_filter_b_val_bit_val_b_val_slice_2_t;
1879:
1880: g_filter_b_val_bit_val_b_val_slice_2_f : if (not(G_FILT_B_EN)) generate
1881: control_registers_out_i.filter_b_val_bit_val_b_val(15 downto 8) <= (others => '0');
1882: end generate g_filter_b_val_bit_val_b_val_slice_2_f;
1883:
1884: ----------------------------------------------------------------------------
1885: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_3]
1886: ----------------------------------------------------------------------------
1887: g_filter_b_val_bit_val_b_val_slice_3_t : if (G_FILT_B_EN) generate
1888:
1889: i_filter_b_val_bit_val_b_val_slice_3_reg : memory_reg_rw
1890: generic map(
1891: data_width => 8 ,
1892: reset_value => "00000000"
1893: )
1894: port map(
1895: clk_sys => clk_sys ,-- in
1896: rst_n => rst_n ,-- in
1897: data_in => w_data(23 downto 16) ,-- in
1898: write => write_en(2) ,-- in
1899: cs => reg_sel(18) ,-- in
1900: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(23 downto 16) -- out
1901: );
1902:
1903: end generate g_filter_b_val_bit_val_b_val_slice_3_t;
1904:
1905: g_filter_b_val_bit_val_b_val_slice_3_f : if (not(G_FILT_B_EN)) generate
1906: control_registers_out_i.filter_b_val_bit_val_b_val(23 downto 16) <= (others => '0');
1907: end generate g_filter_b_val_bit_val_b_val_slice_3_f;
1908:
1909: ----------------------------------------------------------------------------
1910: -- FILTER_B_VAL[BIT_VAL_B_VAL_SLICE_4]
1911: ----------------------------------------------------------------------------
1912: g_filter_b_val_bit_val_b_val_slice_4_t : if (G_FILT_B_EN) generate
1913:
1914: i_filter_b_val_bit_val_b_val_slice_4_reg : memory_reg_rw
1915: generic map(
1916: data_width => 5 ,
1917: reset_value => "00000"
1918: )
1919: port map(
1920: clk_sys => clk_sys ,-- in
1921: rst_n => rst_n ,-- in
1922: data_in => w_data(28 downto 24) ,-- in
1923: write => write_en(3) ,-- in
1924: cs => reg_sel(18) ,-- in
1925: reg_value => control_registers_out_i.filter_b_val_bit_val_b_val(28 downto 24) -- out
1926: );
1927:
1928: end generate g_filter_b_val_bit_val_b_val_slice_4_t;
1929:
1930: g_filter_b_val_bit_val_b_val_slice_4_f : if (not(G_FILT_B_EN)) generate
1931: control_registers_out_i.filter_b_val_bit_val_b_val(28 downto 24) <= (others => '0');
1932: end generate g_filter_b_val_bit_val_b_val_slice_4_f;
1933:
1934: ----------------------------------------------------------------------------
1935: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_1]
1936: ----------------------------------------------------------------------------
1937: g_filter_c_mask_bit_mask_c_val_slice_1_t : if (G_FILT_C_EN) generate
1938:
1939: i_filter_c_mask_bit_mask_c_val_slice_1_reg : memory_reg_rw
1940: generic map(
1941: data_width => 8 ,
1942: reset_value => "00000000"
1943: )
1944: port map(
1945: clk_sys => clk_sys ,-- in
1946: rst_n => rst_n ,-- in
1947: data_in => w_data(7 downto 0) ,-- in
1948: write => write_en(0) ,-- in
1949: cs => reg_sel(19) ,-- in
1950: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(7 downto 0) -- out
1951: );
1952:
1953: end generate g_filter_c_mask_bit_mask_c_val_slice_1_t;
1954:
1955: g_filter_c_mask_bit_mask_c_val_slice_1_f : if (not(G_FILT_C_EN)) generate
1956: control_registers_out_i.filter_c_mask_bit_mask_c_val(7 downto 0) <= (others => '0');
1957: end generate g_filter_c_mask_bit_mask_c_val_slice_1_f;
1958:
1959: ----------------------------------------------------------------------------
1960: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_2]
1961: ----------------------------------------------------------------------------
1962: g_filter_c_mask_bit_mask_c_val_slice_2_t : if (G_FILT_C_EN) generate
1963:
1964: i_filter_c_mask_bit_mask_c_val_slice_2_reg : memory_reg_rw
1965: generic map(
1966: data_width => 8 ,
1967: reset_value => "00000000"
1968: )
1969: port map(
1970: clk_sys => clk_sys ,-- in
1971: rst_n => rst_n ,-- in
1972: data_in => w_data(15 downto 8) ,-- in
1973: write => write_en(1) ,-- in
1974: cs => reg_sel(19) ,-- in
1975: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(15 downto 8) -- out
1976: );
1977:
1978: end generate g_filter_c_mask_bit_mask_c_val_slice_2_t;
1979:
1980: g_filter_c_mask_bit_mask_c_val_slice_2_f : if (not(G_FILT_C_EN)) generate
1981: control_registers_out_i.filter_c_mask_bit_mask_c_val(15 downto 8) <= (others => '0');
1982: end generate g_filter_c_mask_bit_mask_c_val_slice_2_f;
1983:
1984: ----------------------------------------------------------------------------
1985: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_3]
1986: ----------------------------------------------------------------------------
1987: g_filter_c_mask_bit_mask_c_val_slice_3_t : if (G_FILT_C_EN) generate
1988:
1989: i_filter_c_mask_bit_mask_c_val_slice_3_reg : memory_reg_rw
1990: generic map(
1991: data_width => 8 ,
1992: reset_value => "00000000"
1993: )
1994: port map(
1995: clk_sys => clk_sys ,-- in
1996: rst_n => rst_n ,-- in
1997: data_in => w_data(23 downto 16) ,-- in
1998: write => write_en(2) ,-- in
1999: cs => reg_sel(19) ,-- in
2000: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(23 downto 16) -- out
2001: );
2002:
2003: end generate g_filter_c_mask_bit_mask_c_val_slice_3_t;
2004:
2005: g_filter_c_mask_bit_mask_c_val_slice_3_f : if (not(G_FILT_C_EN)) generate
2006: control_registers_out_i.filter_c_mask_bit_mask_c_val(23 downto 16) <= (others => '0');
2007: end generate g_filter_c_mask_bit_mask_c_val_slice_3_f;
2008:
2009: ----------------------------------------------------------------------------
2010: -- FILTER_C_MASK[BIT_MASK_C_VAL_SLICE_4]
2011: ----------------------------------------------------------------------------
2012: g_filter_c_mask_bit_mask_c_val_slice_4_t : if (G_FILT_C_EN) generate
2013:
2014: i_filter_c_mask_bit_mask_c_val_slice_4_reg : memory_reg_rw
2015: generic map(
2016: data_width => 5 ,
2017: reset_value => "00000"
2018: )
2019: port map(
2020: clk_sys => clk_sys ,-- in
2021: rst_n => rst_n ,-- in
2022: data_in => w_data(28 downto 24) ,-- in
2023: write => write_en(3) ,-- in
2024: cs => reg_sel(19) ,-- in
2025: reg_value => control_registers_out_i.filter_c_mask_bit_mask_c_val(28 downto 24) -- out
2026: );
2027:
2028: end generate g_filter_c_mask_bit_mask_c_val_slice_4_t;
2029:
2030: g_filter_c_mask_bit_mask_c_val_slice_4_f : if (not(G_FILT_C_EN)) generate
2031: control_registers_out_i.filter_c_mask_bit_mask_c_val(28 downto 24) <= (others => '0');
2032: end generate g_filter_c_mask_bit_mask_c_val_slice_4_f;
2033:
2034: ----------------------------------------------------------------------------
2035: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_1]
2036: ----------------------------------------------------------------------------
2037: g_filter_c_val_bit_val_c_val_slice_1_t : if (G_FILT_C_EN) generate
2038:
2039: i_filter_c_val_bit_val_c_val_slice_1_reg : memory_reg_rw
2040: generic map(
2041: data_width => 8 ,
2042: reset_value => "00000000"
2043: )
2044: port map(
2045: clk_sys => clk_sys ,-- in
2046: rst_n => rst_n ,-- in
2047: data_in => w_data(7 downto 0) ,-- in
2048: write => write_en(0) ,-- in
2049: cs => reg_sel(20) ,-- in
2050: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(7 downto 0) -- out
2051: );
2052:
2053: end generate g_filter_c_val_bit_val_c_val_slice_1_t;
2054:
2055: g_filter_c_val_bit_val_c_val_slice_1_f : if (not(G_FILT_C_EN)) generate
2056: control_registers_out_i.filter_c_val_bit_val_c_val(7 downto 0) <= (others => '0');
2057: end generate g_filter_c_val_bit_val_c_val_slice_1_f;
2058:
2059: ----------------------------------------------------------------------------
2060: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_2]
2061: ----------------------------------------------------------------------------
2062: g_filter_c_val_bit_val_c_val_slice_2_t : if (G_FILT_C_EN) generate
2063:
2064: i_filter_c_val_bit_val_c_val_slice_2_reg : memory_reg_rw
2065: generic map(
2066: data_width => 8 ,
2067: reset_value => "00000000"
2068: )
2069: port map(
2070: clk_sys => clk_sys ,-- in
2071: rst_n => rst_n ,-- in
2072: data_in => w_data(15 downto 8) ,-- in
2073: write => write_en(1) ,-- in
2074: cs => reg_sel(20) ,-- in
2075: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(15 downto 8) -- out
2076: );
2077:
2078: end generate g_filter_c_val_bit_val_c_val_slice_2_t;
2079:
2080: g_filter_c_val_bit_val_c_val_slice_2_f : if (not(G_FILT_C_EN)) generate
2081: control_registers_out_i.filter_c_val_bit_val_c_val(15 downto 8) <= (others => '0');
2082: end generate g_filter_c_val_bit_val_c_val_slice_2_f;
2083:
2084: ----------------------------------------------------------------------------
2085: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_3]
2086: ----------------------------------------------------------------------------
2087: g_filter_c_val_bit_val_c_val_slice_3_t : if (G_FILT_C_EN) generate
2088:
2089: i_filter_c_val_bit_val_c_val_slice_3_reg : memory_reg_rw
2090: generic map(
2091: data_width => 8 ,
2092: reset_value => "00000000"
2093: )
2094: port map(
2095: clk_sys => clk_sys ,-- in
2096: rst_n => rst_n ,-- in
2097: data_in => w_data(23 downto 16) ,-- in
2098: write => write_en(2) ,-- in
2099: cs => reg_sel(20) ,-- in
2100: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(23 downto 16) -- out
2101: );
2102:
2103: end generate g_filter_c_val_bit_val_c_val_slice_3_t;
2104:
2105: g_filter_c_val_bit_val_c_val_slice_3_f : if (not(G_FILT_C_EN)) generate
2106: control_registers_out_i.filter_c_val_bit_val_c_val(23 downto 16) <= (others => '0');
2107: end generate g_filter_c_val_bit_val_c_val_slice_3_f;
2108:
2109: ----------------------------------------------------------------------------
2110: -- FILTER_C_VAL[BIT_VAL_C_VAL_SLICE_4]
2111: ----------------------------------------------------------------------------
2112: g_filter_c_val_bit_val_c_val_slice_4_t : if (G_FILT_C_EN) generate
2113:
2114: i_filter_c_val_bit_val_c_val_slice_4_reg : memory_reg_rw
2115: generic map(
2116: data_width => 5 ,
2117: reset_value => "00000"
2118: )
2119: port map(
2120: clk_sys => clk_sys ,-- in
2121: rst_n => rst_n ,-- in
2122: data_in => w_data(28 downto 24) ,-- in
2123: write => write_en(3) ,-- in
2124: cs => reg_sel(20) ,-- in
2125: reg_value => control_registers_out_i.filter_c_val_bit_val_c_val(28 downto 24) -- out
2126: );
2127:
2128: end generate g_filter_c_val_bit_val_c_val_slice_4_t;
2129:
2130: g_filter_c_val_bit_val_c_val_slice_4_f : if (not(G_FILT_C_EN)) generate
2131: control_registers_out_i.filter_c_val_bit_val_c_val(28 downto 24) <= (others => '0');
2132: end generate g_filter_c_val_bit_val_c_val_slice_4_f;
2133:
2134: ----------------------------------------------------------------------------
2135: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_1]
2136: ----------------------------------------------------------------------------
2137: g_filter_ran_low_bit_ran_low_val_slice_1_t : if (G_FILT_RANGE_EN) generate
2138:
2139: i_filter_ran_low_bit_ran_low_val_slice_1_reg : memory_reg_rw
2140: generic map(
2141: data_width => 8 ,
2142: reset_value => "00000000"
2143: )
2144: port map(
2145: clk_sys => clk_sys ,-- in
2146: rst_n => rst_n ,-- in
2147: data_in => w_data(7 downto 0) ,-- in
2148: write => write_en(0) ,-- in
2149: cs => reg_sel(21) ,-- in
2150: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(7 downto 0) -- out
2151: );
2152:
2153: end generate g_filter_ran_low_bit_ran_low_val_slice_1_t;
2154:
2155: g_filter_ran_low_bit_ran_low_val_slice_1_f : if (not(G_FILT_RANGE_EN)) generate
2156: control_registers_out_i.filter_ran_low_bit_ran_low_val(7 downto 0) <= (others => '0');
2157: end generate g_filter_ran_low_bit_ran_low_val_slice_1_f;
2158:
2159: ----------------------------------------------------------------------------
2160: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_2]
2161: ----------------------------------------------------------------------------
2162: g_filter_ran_low_bit_ran_low_val_slice_2_t : if (G_FILT_RANGE_EN) generate
2163:
2164: i_filter_ran_low_bit_ran_low_val_slice_2_reg : memory_reg_rw
2165: generic map(
2166: data_width => 8 ,
2167: reset_value => "00000000"
2168: )
2169: port map(
2170: clk_sys => clk_sys ,-- in
2171: rst_n => rst_n ,-- in
2172: data_in => w_data(15 downto 8) ,-- in
2173: write => write_en(1) ,-- in
2174: cs => reg_sel(21) ,-- in
2175: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(15 downto 8) -- out
2176: );
2177:
2178: end generate g_filter_ran_low_bit_ran_low_val_slice_2_t;
2179:
2180: g_filter_ran_low_bit_ran_low_val_slice_2_f : if (not(G_FILT_RANGE_EN)) generate
2181: control_registers_out_i.filter_ran_low_bit_ran_low_val(15 downto 8) <= (others => '0');
2182: end generate g_filter_ran_low_bit_ran_low_val_slice_2_f;
2183:
2184: ----------------------------------------------------------------------------
2185: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_3]
2186: ----------------------------------------------------------------------------
2187: g_filter_ran_low_bit_ran_low_val_slice_3_t : if (G_FILT_RANGE_EN) generate
2188:
2189: i_filter_ran_low_bit_ran_low_val_slice_3_reg : memory_reg_rw
2190: generic map(
2191: data_width => 8 ,
2192: reset_value => "00000000"
2193: )
2194: port map(
2195: clk_sys => clk_sys ,-- in
2196: rst_n => rst_n ,-- in
2197: data_in => w_data(23 downto 16) ,-- in
2198: write => write_en(2) ,-- in
2199: cs => reg_sel(21) ,-- in
2200: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(23 downto 16) -- out
2201: );
2202:
2203: end generate g_filter_ran_low_bit_ran_low_val_slice_3_t;
2204:
2205: g_filter_ran_low_bit_ran_low_val_slice_3_f : if (not(G_FILT_RANGE_EN)) generate
2206: control_registers_out_i.filter_ran_low_bit_ran_low_val(23 downto 16) <= (others => '0');
2207: end generate g_filter_ran_low_bit_ran_low_val_slice_3_f;
2208:
2209: ----------------------------------------------------------------------------
2210: -- FILTER_RAN_LOW[BIT_RAN_LOW_VAL_SLICE_4]
2211: ----------------------------------------------------------------------------
2212: g_filter_ran_low_bit_ran_low_val_slice_4_t : if (G_FILT_RANGE_EN) generate
2213:
2214: i_filter_ran_low_bit_ran_low_val_slice_4_reg : memory_reg_rw
2215: generic map(
2216: data_width => 5 ,
2217: reset_value => "00000"
2218: )
2219: port map(
2220: clk_sys => clk_sys ,-- in
2221: rst_n => rst_n ,-- in
2222: data_in => w_data(28 downto 24) ,-- in
2223: write => write_en(3) ,-- in
2224: cs => reg_sel(21) ,-- in
2225: reg_value => control_registers_out_i.filter_ran_low_bit_ran_low_val(28 downto 24) -- out
2226: );
2227:
2228: end generate g_filter_ran_low_bit_ran_low_val_slice_4_t;
2229:
2230: g_filter_ran_low_bit_ran_low_val_slice_4_f : if (not(G_FILT_RANGE_EN)) generate
2231: control_registers_out_i.filter_ran_low_bit_ran_low_val(28 downto 24) <= (others => '0');
2232: end generate g_filter_ran_low_bit_ran_low_val_slice_4_f;
2233:
2234: ----------------------------------------------------------------------------
2235: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_1]
2236: ----------------------------------------------------------------------------
2237: g_filter_ran_high_bit_ran_high_val_slice_1_t : if (G_FILT_RANGE_EN) generate
2238:
2239: i_filter_ran_high_bit_ran_high_val_slice_1_reg : memory_reg_rw
2240: generic map(
2241: data_width => 8 ,
2242: reset_value => "00000000"
2243: )
2244: port map(
2245: clk_sys => clk_sys ,-- in
2246: rst_n => rst_n ,-- in
2247: data_in => w_data(7 downto 0) ,-- in
2248: write => write_en(0) ,-- in
2249: cs => reg_sel(22) ,-- in
2250: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(7 downto 0) -- out
2251: );
2252:
2253: end generate g_filter_ran_high_bit_ran_high_val_slice_1_t;
2254:
2255: g_filter_ran_high_bit_ran_high_val_slice_1_f : if (not(G_FILT_RANGE_EN)) generate
2256: control_registers_out_i.filter_ran_high_bit_ran_high_val(7 downto 0) <= (others => '0');
2257: end generate g_filter_ran_high_bit_ran_high_val_slice_1_f;
2258:
2259: ----------------------------------------------------------------------------
2260: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_2]
2261: ----------------------------------------------------------------------------
2262: g_filter_ran_high_bit_ran_high_val_slice_2_t : if (G_FILT_RANGE_EN) generate
2263:
2264: i_filter_ran_high_bit_ran_high_val_slice_2_reg : memory_reg_rw
2265: generic map(
2266: data_width => 8 ,
2267: reset_value => "00000000"
2268: )
2269: port map(
2270: clk_sys => clk_sys ,-- in
2271: rst_n => rst_n ,-- in
2272: data_in => w_data(15 downto 8) ,-- in
2273: write => write_en(1) ,-- in
2274: cs => reg_sel(22) ,-- in
2275: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(15 downto 8) -- out
2276: );
2277:
2278: end generate g_filter_ran_high_bit_ran_high_val_slice_2_t;
2279:
2280: g_filter_ran_high_bit_ran_high_val_slice_2_f : if (not(G_FILT_RANGE_EN)) generate
2281: control_registers_out_i.filter_ran_high_bit_ran_high_val(15 downto 8) <= (others => '0');
2282: end generate g_filter_ran_high_bit_ran_high_val_slice_2_f;
2283:
2284: ----------------------------------------------------------------------------
2285: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_3]
2286: ----------------------------------------------------------------------------
2287: g_filter_ran_high_bit_ran_high_val_slice_3_t : if (G_FILT_RANGE_EN) generate
2288:
2289: i_filter_ran_high_bit_ran_high_val_slice_3_reg : memory_reg_rw
2290: generic map(
2291: data_width => 8 ,
2292: reset_value => "00000000"
2293: )
2294: port map(
2295: clk_sys => clk_sys ,-- in
2296: rst_n => rst_n ,-- in
2297: data_in => w_data(23 downto 16) ,-- in
2298: write => write_en(2) ,-- in
2299: cs => reg_sel(22) ,-- in
2300: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(23 downto 16) -- out
2301: );
2302:
2303: end generate g_filter_ran_high_bit_ran_high_val_slice_3_t;
2304:
2305: g_filter_ran_high_bit_ran_high_val_slice_3_f : if (not(G_FILT_RANGE_EN)) generate
2306: control_registers_out_i.filter_ran_high_bit_ran_high_val(23 downto 16) <= (others => '0');
2307: end generate g_filter_ran_high_bit_ran_high_val_slice_3_f;
2308:
2309: ----------------------------------------------------------------------------
2310: -- FILTER_RAN_HIGH[BIT_RAN_HIGH_VAL_SLICE_4]
2311: ----------------------------------------------------------------------------
2312: g_filter_ran_high_bit_ran_high_val_slice_4_t : if (G_FILT_RANGE_EN) generate
2313:
2314: i_filter_ran_high_bit_ran_high_val_slice_4_reg : memory_reg_rw
2315: generic map(
2316: data_width => 5 ,
2317: reset_value => "00000"
2318: )
2319: port map(
2320: clk_sys => clk_sys ,-- in
2321: rst_n => rst_n ,-- in
2322: data_in => w_data(28 downto 24) ,-- in
2323: write => write_en(3) ,-- in
2324: cs => reg_sel(22) ,-- in
2325: reg_value => control_registers_out_i.filter_ran_high_bit_ran_high_val(28 downto 24) -- out
2326: );
2327:
2328: end generate g_filter_ran_high_bit_ran_high_val_slice_4_t;
2329:
2330: g_filter_ran_high_bit_ran_high_val_slice_4_f : if (not(G_FILT_RANGE_EN)) generate
2331: control_registers_out_i.filter_ran_high_bit_ran_high_val(28 downto 24) <= (others => '0');
2332: end generate g_filter_ran_high_bit_ran_high_val_slice_4_f;
2333:
2334: ----------------------------------------------------------------------------
2335: -- FILTER_CONTROL[FANB]
2336: ----------------------------------------------------------------------------
2337:
2338: i_filter_control_fanb_reg : memory_reg_rw
2339: generic map(
2340: data_width => 1 ,
2341: reset_value => "1"
2342: )
2343: port map(
2344: clk_sys => clk_sys ,-- in
2345: rst_n => rst_n ,-- in
2346: data_in => w_data(0 downto 0) ,-- in
2347: write => write_en(0) ,-- in
2348: cs => reg_sel(23) ,-- in
2349: reg_value(0) => control_registers_out_i.filter_control_fanb -- out
2350: );
2351:
2352: ----------------------------------------------------------------------------
2353: -- FILTER_CONTROL[FANE]
2354: ----------------------------------------------------------------------------
2355:
2356: i_filter_control_fane_reg : memory_reg_rw
2357: generic map(
2358: data_width => 1 ,
2359: reset_value => "1"
2360: )
2361: port map(
2362: clk_sys => clk_sys ,-- in
2363: rst_n => rst_n ,-- in
2364: data_in => w_data(1 downto 1) ,-- in
2365: write => write_en(0) ,-- in
2366: cs => reg_sel(23) ,-- in
2367: reg_value(0) => control_registers_out_i.filter_control_fane -- out
2368: );
2369:
2370: ----------------------------------------------------------------------------
2371: -- FILTER_CONTROL[FAFB]
2372: ----------------------------------------------------------------------------
2373:
2374: i_filter_control_fafb_reg : memory_reg_rw
2375: generic map(
2376: data_width => 1 ,
2377: reset_value => "1"
2378: )
2379: port map(
2380: clk_sys => clk_sys ,-- in
2381: rst_n => rst_n ,-- in
2382: data_in => w_data(2 downto 2) ,-- in
2383: write => write_en(0) ,-- in
2384: cs => reg_sel(23) ,-- in
2385: reg_value(0) => control_registers_out_i.filter_control_fafb -- out
2386: );
2387:
2388: ----------------------------------------------------------------------------
2389: -- FILTER_CONTROL[FAFE]
2390: ----------------------------------------------------------------------------
2391:
2392: i_filter_control_fafe_reg : memory_reg_rw
2393: generic map(
2394: data_width => 1 ,
2395: reset_value => "1"
2396: )
2397: port map(
2398: clk_sys => clk_sys ,-- in
2399: rst_n => rst_n ,-- in
2400: data_in => w_data(3 downto 3) ,-- in
2401: write => write_en(0) ,-- in
2402: cs => reg_sel(23) ,-- in
2403: reg_value(0) => control_registers_out_i.filter_control_fafe -- out
2404: );
2405:
2406: ----------------------------------------------------------------------------
2407: -- FILTER_CONTROL[FBNB]
2408: ----------------------------------------------------------------------------
2409:
2410: i_filter_control_fbnb_reg : memory_reg_rw
2411: generic map(
2412: data_width => 1 ,
2413: reset_value => "0"
2414: )
2415: port map(
2416: clk_sys => clk_sys ,-- in
2417: rst_n => rst_n ,-- in
2418: data_in => w_data(4 downto 4) ,-- in
2419: write => write_en(0) ,-- in
2420: cs => reg_sel(23) ,-- in
2421: reg_value(0) => control_registers_out_i.filter_control_fbnb -- out
2422: );
2423:
2424: ----------------------------------------------------------------------------
2425: -- FILTER_CONTROL[FBNE]
2426: ----------------------------------------------------------------------------
2427:
2428: i_filter_control_fbne_reg : memory_reg_rw
2429: generic map(
2430: data_width => 1 ,
2431: reset_value => "0"
2432: )
2433: port map(
2434: clk_sys => clk_sys ,-- in
2435: rst_n => rst_n ,-- in
2436: data_in => w_data(5 downto 5) ,-- in
2437: write => write_en(0) ,-- in
2438: cs => reg_sel(23) ,-- in
2439: reg_value(0) => control_registers_out_i.filter_control_fbne -- out
2440: );
2441:
2442: ----------------------------------------------------------------------------
2443: -- FILTER_CONTROL[FBFB]
2444: ----------------------------------------------------------------------------
2445:
2446: i_filter_control_fbfb_reg : memory_reg_rw
2447: generic map(
2448: data_width => 1 ,
2449: reset_value => "0"
2450: )
2451: port map(
2452: clk_sys => clk_sys ,-- in
2453: rst_n => rst_n ,-- in
2454: data_in => w_data(6 downto 6) ,-- in
2455: write => write_en(0) ,-- in
2456: cs => reg_sel(23) ,-- in
2457: reg_value(0) => control_registers_out_i.filter_control_fbfb -- out
2458: );
2459:
2460: ----------------------------------------------------------------------------
2461: -- FILTER_CONTROL[FBFE]
2462: ----------------------------------------------------------------------------
2463:
2464: i_filter_control_fbfe_reg : memory_reg_rw
2465: generic map(
2466: data_width => 1 ,
2467: reset_value => "0"
2468: )
2469: port map(
2470: clk_sys => clk_sys ,-- in
2471: rst_n => rst_n ,-- in
2472: data_in => w_data(7 downto 7) ,-- in
2473: write => write_en(0) ,-- in
2474: cs => reg_sel(23) ,-- in
2475: reg_value(0) => control_registers_out_i.filter_control_fbfe -- out
2476: );
2477:
2478: ----------------------------------------------------------------------------
2479: -- FILTER_CONTROL[FCNB]
2480: ----------------------------------------------------------------------------
2481:
2482: i_filter_control_fcnb_reg : memory_reg_rw
2483: generic map(
2484: data_width => 1 ,
2485: reset_value => "0"
2486: )
2487: port map(
2488: clk_sys => clk_sys ,-- in
2489: rst_n => rst_n ,-- in
2490: data_in => w_data(8 downto 8) ,-- in
2491: write => write_en(1) ,-- in
2492: cs => reg_sel(23) ,-- in
2493: reg_value(0) => control_registers_out_i.filter_control_fcnb -- out
2494: );
2495:
2496: ----------------------------------------------------------------------------
2497: -- FILTER_CONTROL[FCNE]
2498: ----------------------------------------------------------------------------
2499:
2500: i_filter_control_fcne_reg : memory_reg_rw
2501: generic map(
2502: data_width => 1 ,
2503: reset_value => "0"
2504: )
2505: port map(
2506: clk_sys => clk_sys ,-- in
2507: rst_n => rst_n ,-- in
2508: data_in => w_data(9 downto 9) ,-- in
2509: write => write_en(1) ,-- in
2510: cs => reg_sel(23) ,-- in
2511: reg_value(0) => control_registers_out_i.filter_control_fcne -- out
2512: );
2513:
2514: ----------------------------------------------------------------------------
2515: -- FILTER_CONTROL[FCFB]
2516: ----------------------------------------------------------------------------
2517:
2518: i_filter_control_fcfb_reg : memory_reg_rw
2519: generic map(
2520: data_width => 1 ,
2521: reset_value => "0"
2522: )
2523: port map(
2524: clk_sys => clk_sys ,-- in
2525: rst_n => rst_n ,-- in
2526: data_in => w_data(10 downto 10) ,-- in
2527: write => write_en(1) ,-- in
2528: cs => reg_sel(23) ,-- in
2529: reg_value(0) => control_registers_out_i.filter_control_fcfb -- out
2530: );
2531:
2532: ----------------------------------------------------------------------------
2533: -- FILTER_CONTROL[FCFE]
2534: ----------------------------------------------------------------------------
2535:
2536: i_filter_control_fcfe_reg : memory_reg_rw
2537: generic map(
2538: data_width => 1 ,
2539: reset_value => "0"
2540: )
2541: port map(
2542: clk_sys => clk_sys ,-- in
2543: rst_n => rst_n ,-- in
2544: data_in => w_data(11 downto 11) ,-- in
2545: write => write_en(1) ,-- in
2546: cs => reg_sel(23) ,-- in
2547: reg_value(0) => control_registers_out_i.filter_control_fcfe -- out
2548: );
2549:
2550: ----------------------------------------------------------------------------
2551: -- FILTER_CONTROL[FRNB]
2552: ----------------------------------------------------------------------------
2553:
2554: i_filter_control_frnb_reg : memory_reg_rw
2555: generic map(
2556: data_width => 1 ,
2557: reset_value => "0"
2558: )
2559: port map(
2560: clk_sys => clk_sys ,-- in
2561: rst_n => rst_n ,-- in
2562: data_in => w_data(12 downto 12) ,-- in
2563: write => write_en(1) ,-- in
2564: cs => reg_sel(23) ,-- in
2565: reg_value(0) => control_registers_out_i.filter_control_frnb -- out
2566: );
2567:
2568: ----------------------------------------------------------------------------
2569: -- FILTER_CONTROL[FRNE]
2570: ----------------------------------------------------------------------------
2571:
2572: i_filter_control_frne_reg : memory_reg_rw
2573: generic map(
2574: data_width => 1 ,
2575: reset_value => "0"
2576: )
2577: port map(
2578: clk_sys => clk_sys ,-- in
2579: rst_n => rst_n ,-- in
2580: data_in => w_data(13 downto 13) ,-- in
2581: write => write_en(1) ,-- in
2582: cs => reg_sel(23) ,-- in
2583: reg_value(0) => control_registers_out_i.filter_control_frne -- out
2584: );
2585:
2586: ----------------------------------------------------------------------------
2587: -- FILTER_CONTROL[FRFB]
2588: ----------------------------------------------------------------------------
2589:
2590: i_filter_control_frfb_reg : memory_reg_rw
2591: generic map(
2592: data_width => 1 ,
2593: reset_value => "0"
2594: )
2595: port map(
2596: clk_sys => clk_sys ,-- in
2597: rst_n => rst_n ,-- in
2598: data_in => w_data(14 downto 14) ,-- in
2599: write => write_en(1) ,-- in
2600: cs => reg_sel(23) ,-- in
2601: reg_value(0) => control_registers_out_i.filter_control_frfb -- out
2602: );
2603:
2604: ----------------------------------------------------------------------------
2605: -- FILTER_CONTROL[FRFE]
2606: ----------------------------------------------------------------------------
2607:
2608: i_filter_control_frfe_reg : memory_reg_rw
2609: generic map(
2610: data_width => 1 ,
2611: reset_value => "0"
2612: )
2613: port map(
2614: clk_sys => clk_sys ,-- in
2615: rst_n => rst_n ,-- in
2616: data_in => w_data(15 downto 15) ,-- in
2617: write => write_en(1) ,-- in
2618: cs => reg_sel(23) ,-- in
2619: reg_value(0) => control_registers_out_i.filter_control_frfe -- out
2620: );
2621:
2622: ----------------------------------------------------------------------------
2623: -- RX_SETTINGS[RTSOP]
2624: ----------------------------------------------------------------------------
2625:
2626: i_rx_settings_rtsop_reg : memory_reg_rw
2627: generic map(
2628: data_width => 1 ,
2629: reset_value => "0"
2630: )
2631: port map(
2632: clk_sys => clk_sys ,-- in
2633: rst_n => rst_n ,-- in
2634: data_in => w_data(16 downto 16) ,-- in
2635: write => write_en(2) ,-- in
2636: cs => reg_sel(26) ,-- in
2637: reg_value(0) => control_registers_out_i.rx_settings_rtsop -- out
2638: );
2639:
2640: ----------------------------------------------------------------------------
2641: -- RX_DATA access signallization
2642: ----------------------------------------------------------------------------
2643:
2644: i_rx_data_access_signaller : read_access_signaller
2645: generic map(
2646: data_width => 32
2647: )
2648: port map(
2649: clk_sys => clk_sys ,-- in
2650: rst_n => rst_n ,-- in
2651: cs => reg_sel(27) ,-- in
2652: read => read ,-- in
2653: be => be(3 downto 0) ,-- in
2654: read_signal => control_registers_out_i.rx_data_read -- out
2655: );
2656:
2657: ----------------------------------------------------------------------------
2658: -- TX_COMMAND[TXCE]
2659: ----------------------------------------------------------------------------
2660:
2661: i_tx_command_txce_reg : memory_reg_os
2662: generic map(
2663: data_width => 1 ,
2664: reset_value => "0"
2665: )
2666: port map(
2667: clk_sys => clk_sys ,-- in
2668: rst_n => rst_n ,-- in
2669: data_in => w_data(0 downto 0) ,-- in
2670: write => write_en(0) ,-- in
2671: cs => reg_sel(29) ,-- in
2672: reg_value(0) => control_registers_out_i.tx_command_txce -- out
2673: );
2674:
2675: ----------------------------------------------------------------------------
2676: -- TX_COMMAND[TXCR]
2677: ----------------------------------------------------------------------------
2678:
2679: i_tx_command_txcr_reg : memory_reg_os
2680: generic map(
2681: data_width => 1 ,
2682: reset_value => "0"
2683: )
2684: port map(
2685: clk_sys => clk_sys ,-- in
2686: rst_n => rst_n ,-- in
2687: data_in => w_data(1 downto 1) ,-- in
2688: write => write_en(0) ,-- in
2689: cs => reg_sel(29) ,-- in
2690: reg_value(0) => control_registers_out_i.tx_command_txcr -- out
2691: );
2692:
2693: ----------------------------------------------------------------------------
2694: -- TX_COMMAND[TXCA]
2695: ----------------------------------------------------------------------------
2696:
2697: i_tx_command_txca_reg : memory_reg_os
2698: generic map(
2699: data_width => 1 ,
2700: reset_value => "0"
2701: )
2702: port map(
2703: clk_sys => clk_sys ,-- in
2704: rst_n => rst_n ,-- in
2705: data_in => w_data(2 downto 2) ,-- in
2706: write => write_en(0) ,-- in
2707: cs => reg_sel(29) ,-- in
2708: reg_value(0) => control_registers_out_i.tx_command_txca -- out
2709: );
2710:
2711: ----------------------------------------------------------------------------
2712: -- TX_COMMAND[TXB1]
2713: ----------------------------------------------------------------------------
2714:
2715: i_tx_command_txb1_reg : memory_reg_rw
2716: generic map(
2717: data_width => 1 ,
2718: reset_value => "0"
2719: )
2720: port map(
2721: clk_sys => clk_sys ,-- in
2722: rst_n => rst_n ,-- in
2723: data_in => w_data(8 downto 8) ,-- in
2724: write => write_en(1) ,-- in
2725: cs => reg_sel(29) ,-- in
2726: reg_value(0) => control_registers_out_i.tx_command_txb1 -- out
2727: );
2728:
2729: ----------------------------------------------------------------------------
2730: -- TX_COMMAND[TXB2]
2731: ----------------------------------------------------------------------------
2732:
2733: i_tx_command_txb2_reg : memory_reg_rw
2734: generic map(
2735: data_width => 1 ,
2736: reset_value => "0"
2737: )
2738: port map(
2739: clk_sys => clk_sys ,-- in
2740: rst_n => rst_n ,-- in
2741: data_in => w_data(9 downto 9) ,-- in
2742: write => write_en(1) ,-- in
2743: cs => reg_sel(29) ,-- in
2744: reg_value(0) => control_registers_out_i.tx_command_txb2 -- out
2745: );
2746:
2747: ----------------------------------------------------------------------------
2748: -- TX_COMMAND[TXB3]
2749: ----------------------------------------------------------------------------
2750: g_tx_command_txb3_t : if (G_TXT_BUF_COUNT > 2) generate
2751:
2752: i_tx_command_txb3_reg : memory_reg_rw
2753: generic map(
2754: data_width => 1 ,
2755: reset_value => "0"
2756: )
2757: port map(
2758: clk_sys => clk_sys ,-- in
2759: rst_n => rst_n ,-- in
2760: data_in => w_data(10 downto 10) ,-- in
2761: write => write_en(1) ,-- in
2762: cs => reg_sel(29) ,-- in
2763: reg_value(0) => control_registers_out_i.tx_command_txb3 -- out
2764: );
2765:
2766: end generate g_tx_command_txb3_t;
2767:
2768: g_tx_command_txb3_f : if (not(G_TXT_BUF_COUNT > 2)) generate
2769: control_registers_out_i.tx_command_txb3 <= '0';
2770: end generate g_tx_command_txb3_f;
2771:
2772: ----------------------------------------------------------------------------
2773: -- TX_COMMAND[TXB4]
2774: ----------------------------------------------------------------------------
2775: g_tx_command_txb4_t : if (G_TXT_BUF_COUNT > 3) generate
2776:
2777: i_tx_command_txb4_reg : memory_reg_rw
2778: generic map(
2779: data_width => 1 ,
2780: reset_value => "0"
2781: )
2782: port map(
2783: clk_sys => clk_sys ,-- in
2784: rst_n => rst_n ,-- in
2785: data_in => w_data(11 downto 11) ,-- in
2786: write => write_en(1) ,-- in
2787: cs => reg_sel(29) ,-- in
2788: reg_value(0) => control_registers_out_i.tx_command_txb4 -- out
2789: );
2790:
2791: end generate g_tx_command_txb4_t;
2792:
2793: g_tx_command_txb4_f : if (not(G_TXT_BUF_COUNT > 3)) generate
2794: control_registers_out_i.tx_command_txb4 <= '0';
2795: end generate g_tx_command_txb4_f;
2796:
2797: ----------------------------------------------------------------------------
2798: -- TX_COMMAND[TXB5]
2799: ----------------------------------------------------------------------------
2800: g_tx_command_txb5_t : if (G_TXT_BUF_COUNT > 4) generate
2801:
2802: i_tx_command_txb5_reg : memory_reg_rw
2803: generic map(
2804: data_width => 1 ,
2805: reset_value => "0"
2806: )
2807: port map(
2808: clk_sys => clk_sys ,-- in
2809: rst_n => rst_n ,-- in
2810: data_in => w_data(12 downto 12) ,-- in
2811: write => write_en(1) ,-- in
2812: cs => reg_sel(29) ,-- in
2813: reg_value(0) => control_registers_out_i.tx_command_txb5 -- out
2814: );
2815:
2816: end generate g_tx_command_txb5_t;
2817:
2818: g_tx_command_txb5_f : if (not(G_TXT_BUF_COUNT > 4)) generate
2819: control_registers_out_i.tx_command_txb5 <= '0';
2820: end generate g_tx_command_txb5_f;
2821:
2822: ----------------------------------------------------------------------------
2823: -- TX_COMMAND[TXB6]
2824: ----------------------------------------------------------------------------
2825: g_tx_command_txb6_t : if (G_TXT_BUF_COUNT > 5) generate
2826:
2827: i_tx_command_txb6_reg : memory_reg_rw
2828: generic map(
2829: data_width => 1 ,
2830: reset_value => "0"
2831: )
2832: port map(
2833: clk_sys => clk_sys ,-- in
2834: rst_n => rst_n ,-- in
2835: data_in => w_data(13 downto 13) ,-- in
2836: write => write_en(1) ,-- in
2837: cs => reg_sel(29) ,-- in
2838: reg_value(0) => control_registers_out_i.tx_command_txb6 -- out
2839: );
2840:
2841: end generate g_tx_command_txb6_t;
2842:
2843: g_tx_command_txb6_f : if (not(G_TXT_BUF_COUNT > 5)) generate
2844: control_registers_out_i.tx_command_txb6 <= '0';
2845: end generate g_tx_command_txb6_f;
2846:
2847: ----------------------------------------------------------------------------
2848: -- TX_COMMAND[TXB7]
2849: ----------------------------------------------------------------------------
2850: g_tx_command_txb7_t : if (G_TXT_BUF_COUNT > 6) generate
2851:
2852: i_tx_command_txb7_reg : memory_reg_rw
2853: generic map(
2854: data_width => 1 ,
2855: reset_value => "0"
2856: )
2857: port map(
2858: clk_sys => clk_sys ,-- in
2859: rst_n => rst_n ,-- in
2860: data_in => w_data(14 downto 14) ,-- in
2861: write => write_en(1) ,-- in
2862: cs => reg_sel(29) ,-- in
2863: reg_value(0) => control_registers_out_i.tx_command_txb7 -- out
2864: );
2865:
2866: end generate g_tx_command_txb7_t;
2867:
2868: g_tx_command_txb7_f : if (not(G_TXT_BUF_COUNT > 6)) generate
2869: control_registers_out_i.tx_command_txb7 <= '0';
2870: end generate g_tx_command_txb7_f;
2871:
2872: ----------------------------------------------------------------------------
2873: -- TX_COMMAND[TXB8]
2874: ----------------------------------------------------------------------------
2875: g_tx_command_txb8_t : if (G_TXT_BUF_COUNT > 7) generate
2876:
2877: i_tx_command_txb8_reg : memory_reg_rw
2878: generic map(
2879: data_width => 1 ,
2880: reset_value => "0"
2881: )
2882: port map(
2883: clk_sys => clk_sys ,-- in
2884: rst_n => rst_n ,-- in
2885: data_in => w_data(15 downto 15) ,-- in
2886: write => write_en(1) ,-- in
2887: cs => reg_sel(29) ,-- in
2888: reg_value(0) => control_registers_out_i.tx_command_txb8 -- out
2889: );
2890:
2891: end generate g_tx_command_txb8_t;
2892:
2893: g_tx_command_txb8_f : if (not(G_TXT_BUF_COUNT > 7)) generate
2894: control_registers_out_i.tx_command_txb8 <= '0';
2895: end generate g_tx_command_txb8_f;
2896:
2897: ----------------------------------------------------------------------------
2898: -- TX_PRIORITY[TXT1P]
2899: ----------------------------------------------------------------------------
2900:
2901: i_tx_priority_txt1p_reg : memory_reg_rw
2902: generic map(
2903: data_width => 3 ,
2904: reset_value => "001"
2905: )
2906: port map(
2907: clk_sys => clk_sys ,-- in
2908: rst_n => rst_n ,-- in
2909: data_in => w_data(2 downto 0) ,-- in
2910: write => write_en(0) ,-- in
2911: cs => reg_sel(30) ,-- in
2912: reg_value => control_registers_out_i.tx_priority_txt1p -- out
2913: );
2914:
2915: ----------------------------------------------------------------------------
2916: -- TX_PRIORITY[TXT2P]
2917: ----------------------------------------------------------------------------
2918:
2919: i_tx_priority_txt2p_reg : memory_reg_rw
2920: generic map(
2921: data_width => 3 ,
2922: reset_value => "000"
2923: )
2924: port map(
2925: clk_sys => clk_sys ,-- in
2926: rst_n => rst_n ,-- in
2927: data_in => w_data(6 downto 4) ,-- in
2928: write => write_en(0) ,-- in
2929: cs => reg_sel(30) ,-- in
2930: reg_value => control_registers_out_i.tx_priority_txt2p -- out
2931: );
2932:
2933: ----------------------------------------------------------------------------
2934: -- TX_PRIORITY[TXT3P]
2935: ----------------------------------------------------------------------------
2936: g_tx_priority_txt3p_t : if (G_TXT_BUF_COUNT > 2) generate
2937:
2938: i_tx_priority_txt3p_reg : memory_reg_rw
2939: generic map(
2940: data_width => 3 ,
2941: reset_value => "000"
2942: )
2943: port map(
2944: clk_sys => clk_sys ,-- in
2945: rst_n => rst_n ,-- in
2946: data_in => w_data(10 downto 8) ,-- in
2947: write => write_en(1) ,-- in
2948: cs => reg_sel(30) ,-- in
2949: reg_value => control_registers_out_i.tx_priority_txt3p -- out
2950: );
2951:
2952: end generate g_tx_priority_txt3p_t;
2953:
2954: g_tx_priority_txt3p_f : if (not(G_TXT_BUF_COUNT > 2)) generate
2955: control_registers_out_i.tx_priority_txt3p <= (others => '0');
2956: end generate g_tx_priority_txt3p_f;
2957:
2958: ----------------------------------------------------------------------------
2959: -- TX_PRIORITY[TXT4P]
2960: ----------------------------------------------------------------------------
2961: g_tx_priority_txt4p_t : if (G_TXT_BUF_COUNT > 3) generate
2962:
2963: i_tx_priority_txt4p_reg : memory_reg_rw
2964: generic map(
2965: data_width => 3 ,
2966: reset_value => "000"
2967: )
2968: port map(
2969: clk_sys => clk_sys ,-- in
2970: rst_n => rst_n ,-- in
2971: data_in => w_data(14 downto 12) ,-- in
2972: write => write_en(1) ,-- in
2973: cs => reg_sel(30) ,-- in
2974: reg_value => control_registers_out_i.tx_priority_txt4p -- out
2975: );
2976:
2977: end generate g_tx_priority_txt4p_t;
2978:
2979: g_tx_priority_txt4p_f : if (not(G_TXT_BUF_COUNT > 3)) generate
2980: control_registers_out_i.tx_priority_txt4p <= (others => '0');
2981: end generate g_tx_priority_txt4p_f;
2982:
2983: ----------------------------------------------------------------------------
2984: -- TX_PRIORITY[TXT5P]
2985: ----------------------------------------------------------------------------
2986: g_tx_priority_txt5p_t : if (G_TXT_BUF_COUNT > 4) generate
2987:
2988: i_tx_priority_txt5p_reg : memory_reg_rw
2989: generic map(
2990: data_width => 3 ,
2991: reset_value => "000"
2992: )
2993: port map(
2994: clk_sys => clk_sys ,-- in
2995: rst_n => rst_n ,-- in
2996: data_in => w_data(18 downto 16) ,-- in
2997: write => write_en(2) ,-- in
2998: cs => reg_sel(30) ,-- in
2999: reg_value => control_registers_out_i.tx_priority_txt5p -- out
3000: );
3001:
3002: end generate g_tx_priority_txt5p_t;
3003:
3004: g_tx_priority_txt5p_f : if (not(G_TXT_BUF_COUNT > 4)) generate
3005: control_registers_out_i.tx_priority_txt5p <= (others => '0');
3006: end generate g_tx_priority_txt5p_f;
3007:
3008: ----------------------------------------------------------------------------
3009: -- TX_PRIORITY[TXT6P]
3010: ----------------------------------------------------------------------------
3011: g_tx_priority_txt6p_t : if (G_TXT_BUF_COUNT > 5) generate
3012:
3013: i_tx_priority_txt6p_reg : memory_reg_rw
3014: generic map(
3015: data_width => 3 ,
3016: reset_value => "000"
3017: )
3018: port map(
3019: clk_sys => clk_sys ,-- in
3020: rst_n => rst_n ,-- in
3021: data_in => w_data(22 downto 20) ,-- in
3022: write => write_en(2) ,-- in
3023: cs => reg_sel(30) ,-- in
3024: reg_value => control_registers_out_i.tx_priority_txt6p -- out
3025: );
3026:
3027: end generate g_tx_priority_txt6p_t;
3028:
3029: g_tx_priority_txt6p_f : if (not(G_TXT_BUF_COUNT > 5)) generate
3030: control_registers_out_i.tx_priority_txt6p <= (others => '0');
3031: end generate g_tx_priority_txt6p_f;
3032:
3033: ----------------------------------------------------------------------------
3034: -- TX_PRIORITY[TXT7P]
3035: ----------------------------------------------------------------------------
3036: g_tx_priority_txt7p_t : if (G_TXT_BUF_COUNT > 6) generate
3037:
3038: i_tx_priority_txt7p_reg : memory_reg_rw
3039: generic map(
3040: data_width => 3 ,
3041: reset_value => "000"
3042: )
3043: port map(
3044: clk_sys => clk_sys ,-- in
3045: rst_n => rst_n ,-- in
3046: data_in => w_data(26 downto 24) ,-- in
3047: write => write_en(3) ,-- in
3048: cs => reg_sel(30) ,-- in
3049: reg_value => control_registers_out_i.tx_priority_txt7p -- out
3050: );
3051:
3052: end generate g_tx_priority_txt7p_t;
3053:
3054: g_tx_priority_txt7p_f : if (not(G_TXT_BUF_COUNT > 6)) generate
3055: control_registers_out_i.tx_priority_txt7p <= (others => '0');
3056: end generate g_tx_priority_txt7p_f;
3057:
3058: ----------------------------------------------------------------------------
3059: -- TX_PRIORITY[TXT8P]
3060: ----------------------------------------------------------------------------
3061: g_tx_priority_txt8p_t : if (G_TXT_BUF_COUNT > 7) generate
3062:
3063: i_tx_priority_txt8p_reg : memory_reg_rw
3064: generic map(
3065: data_width => 3 ,
3066: reset_value => "000"
3067: )
3068: port map(
3069: clk_sys => clk_sys ,-- in
3070: rst_n => rst_n ,-- in
3071: data_in => w_data(30 downto 28) ,-- in
3072: write => write_en(3) ,-- in
3073: cs => reg_sel(30) ,-- in
3074: reg_value => control_registers_out_i.tx_priority_txt8p -- out
3075: );
3076:
3077: end generate g_tx_priority_txt8p_t;
3078:
3079: g_tx_priority_txt8p_f : if (not(G_TXT_BUF_COUNT > 7)) generate
3080: control_registers_out_i.tx_priority_txt8p <= (others => '0');
3081: end generate g_tx_priority_txt8p_f;
3082:
3083: ----------------------------------------------------------------------------
3084: -- SSP_CFG[SSP_OFFSET]
3085: ----------------------------------------------------------------------------
3086:
3087: i_ssp_cfg_ssp_offset_reg : memory_reg_rw_lock
3088: generic map(
3089: data_width => 8 ,
3090: reset_value => "00001010"
3091: )
3092: port map(
3093: clk_sys => clk_sys ,-- in
3094: rst_n => rst_n ,-- in
3095: data_in => w_data(23 downto 16) ,-- in
3096: write => write_en(2) ,-- in
3097: cs => reg_sel(32) ,-- in
3098: lock => lock_2 ,-- in
3099: reg_value => control_registers_out_i.ssp_cfg_ssp_offset -- out
3100: );
3101:
3102: ----------------------------------------------------------------------------
3103: -- SSP_CFG[SSP_SRC]
3104: ----------------------------------------------------------------------------
3105:
3106: i_ssp_cfg_ssp_src_reg : memory_reg_rw_lock
3107: generic map(
3108: data_width => 2 ,
3109: reset_value => "00"
3110: )
3111: port map(
3112: clk_sys => clk_sys ,-- in
3113: rst_n => rst_n ,-- in
3114: data_in => w_data(25 downto 24) ,-- in
3115: write => write_en(3) ,-- in
3116: cs => reg_sel(32) ,-- in
3117: lock => lock_2 ,-- in
3118: reg_value => control_registers_out_i.ssp_cfg_ssp_src -- out
3119: );
3120:
3121: ----------------------------------------------------------------------------
3122: -- Read data multiplexor
3123: ----------------------------------------------------------------------------
3124: with address(7 downto 2) select r_data_comb <=
3125: control_registers_in.version_ver_major &
3126: control_registers_in.version_ver_minor &
3127: control_registers_in.device_id_device_id when "000000",
3128: '0' & '0' & '0' & '0' &
3129: control_registers_out_i.settings_pchke &
3130: control_registers_out_i.settings_fdrf &
3131: control_registers_out_i.settings_tbfbo &
3132: control_registers_out_i.settings_pex &
3133: control_registers_out_i.settings_nisofd &
3134: control_registers_out_i.settings_ena &
3135: control_registers_out_i.settings_ilbp &
3136: control_registers_out_i.settings_rtrth &
3137: control_registers_out_i.settings_rtrle &
3138: '0' & '0' & '0' &
3139: control_registers_out_i.mode_erfm &
3140: control_registers_out_i.mode_sam &
3141: control_registers_out_i.mode_txbbm &
3142: control_registers_out_i.mode_rxbam &
3143: control_registers_out_i.mode_tstm &
3144: control_registers_out_i.mode_acf &
3145: control_registers_out_i.mode_rom &
3146: control_registers_out_i.mode_tttm &
3147: control_registers_out_i.mode_fde &
3148: control_registers_out_i.mode_afm &
3149: control_registers_out_i.mode_stm &
3150: control_registers_out_i.mode_bmm &
3151: control_registers_out_i.mode_rst when "000001",
3152: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3153: control_registers_in.status_sprt &
3154: control_registers_in.status_strgs &
3155: control_registers_in.status_stcnt &
3156: '0' & '0' & '0' & '0' &
3157: control_registers_in.status_txdpe &
3158: control_registers_in.status_txpe &
3159: control_registers_in.status_rxpe &
3160: control_registers_in.status_pexs &
3161: control_registers_in.status_idle &
3162: control_registers_in.status_ewl &
3163: control_registers_in.status_txs &
3164: control_registers_in.status_rxs &
3165: control_registers_in.status_eft &
3166: control_registers_in.status_txnf &
3167: control_registers_in.status_dor &
3168: control_registers_in.status_rxne when "000010",
3169: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000011",
3170: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3171: control_registers_in.int_stat_txbhci &
3172: control_registers_in.int_stat_rbnei &
3173: control_registers_in.int_stat_bsi &
3174: control_registers_in.int_stat_rxfi &
3175: control_registers_in.int_stat_ofi &
3176: control_registers_in.int_stat_bei &
3177: control_registers_in.int_stat_ali &
3178: control_registers_in.int_stat_fcsi &
3179: control_registers_in.int_stat_doi &
3180: control_registers_in.int_stat_ewli &
3181: control_registers_in.int_stat_txi &
3182: control_registers_in.int_stat_rxi when "000100",
3183: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3184: control_registers_in.int_ena_set_int_ena_set when "000101",
3185: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000110",
3186: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3187: control_registers_in.int_mask_set_int_mask_set when "000111",
3188: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001000",
3189: control_registers_out_i.btr_sjw &
3190: control_registers_out_i.btr_brp &
3191: control_registers_out_i.btr_ph2 &
3192: control_registers_out_i.btr_ph1 &
3193: control_registers_out_i.btr_prop when "001001",
3194: control_registers_out_i.btr_fd_sjw_fd &
3195: control_registers_out_i.btr_fd_brp_fd &
3196: '0' &
3197: control_registers_out_i.btr_fd_ph2_fd &
3198: '0' &
3199: control_registers_out_i.btr_fd_ph1_fd &
3200: '0' &
3201: control_registers_out_i.btr_fd_prop_fd when "001010",
3202: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3203: control_registers_in.fault_state_bof &
3204: control_registers_in.fault_state_erp &
3205: control_registers_in.fault_state_era &
3206: control_registers_out_i.erp_erp_limit &
3207: control_registers_out_i.ewl_ew_limit when "001011",
3208: '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3209: control_registers_in.tec_tec_val &
3210: '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3211: control_registers_in.rec_rec_val when "001100",
3212: control_registers_in.err_fd_err_fd_val &
3213: control_registers_in.err_norm_err_norm_val when "001101",
3214: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001110",
3215: '0' & '0' & '0' &
3216: control_registers_out_i.filter_a_mask_bit_mask_a_val when "001111",
3217: '0' & '0' & '0' &
3218: control_registers_out_i.filter_a_val_bit_val_a_val when "010000",
3219: '0' & '0' & '0' &
3220: control_registers_out_i.filter_b_mask_bit_mask_b_val when "010001",
3221: '0' & '0' & '0' &
3222: control_registers_out_i.filter_b_val_bit_val_b_val when "010010",
3223: '0' & '0' & '0' &
3224: control_registers_out_i.filter_c_mask_bit_mask_c_val when "010011",
3225: '0' & '0' & '0' &
3226: control_registers_out_i.filter_c_val_bit_val_c_val when "010100",
3227: '0' & '0' & '0' &
3228: control_registers_out_i.filter_ran_low_bit_ran_low_val when "010101",
3229: '0' & '0' & '0' &
3230: control_registers_out_i.filter_ran_high_bit_ran_high_val when "010110",
3231: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3232: control_registers_in.filter_status_sfr &
3233: control_registers_in.filter_status_sfc &
3234: control_registers_in.filter_status_sfb &
3235: control_registers_in.filter_status_sfa &
3236: control_registers_out_i.filter_control_frfe &
3237: control_registers_out_i.filter_control_frfb &
3238: control_registers_out_i.filter_control_frne &
3239: control_registers_out_i.filter_control_frnb &
3240: control_registers_out_i.filter_control_fcfe &
3241: control_registers_out_i.filter_control_fcfb &
3242: control_registers_out_i.filter_control_fcne &
3243: control_registers_out_i.filter_control_fcnb &
3244: control_registers_out_i.filter_control_fbfe &
3245: control_registers_out_i.filter_control_fbfb &
3246: control_registers_out_i.filter_control_fbne &
3247: control_registers_out_i.filter_control_fbnb &
3248: control_registers_out_i.filter_control_fafe &
3249: control_registers_out_i.filter_control_fafb &
3250: control_registers_out_i.filter_control_fane &
3251: control_registers_out_i.filter_control_fanb when "010111",
3252: '0' & '0' & '0' &
3253: control_registers_in.rx_mem_info_rx_mem_free &
3254: '0' & '0' & '0' &
3255: control_registers_in.rx_mem_info_rx_buff_size when "011000",
3256: '0' & '0' & '0' & '0' &
3257: control_registers_in.rx_pointers_rx_rpp &
3258: '0' & '0' & '0' & '0' &
3259: control_registers_in.rx_pointers_rx_wpp when "011001",
3260: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3261: control_registers_out_i.rx_settings_rtsop &
3262: '0' &
3263: control_registers_in.rx_status_rxfrc &
3264: '0' &
3265: control_registers_in.rx_status_rxmof &
3266: control_registers_in.rx_status_rxf &
3267: control_registers_in.rx_status_rxe when "011010",
3268: control_registers_in.rx_data_rx_data when "011011",
3269: control_registers_in.tx_status_tx8s &
3270: control_registers_in.tx_status_tx7s &
3271: control_registers_in.tx_status_tx6s &
3272: control_registers_in.tx_status_tx5s &
3273: control_registers_in.tx_status_tx4s &
3274: control_registers_in.tx_status_tx3s &
3275: control_registers_in.tx_status_tx2s &
3276: control_registers_in.tx_status_tx1s when "011100",
3277: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3278: control_registers_in.txtb_info_txt_buffer_count &
3279: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "011101",
3280: '0' &
3281: control_registers_out_i.tx_priority_txt8p &
3282: '0' &
3283: control_registers_out_i.tx_priority_txt7p &
3284: '0' &
3285: control_registers_out_i.tx_priority_txt6p &
3286: '0' &
3287: control_registers_out_i.tx_priority_txt5p &
3288: '0' &
3289: control_registers_out_i.tx_priority_txt4p &
3290: '0' &
3291: control_registers_out_i.tx_priority_txt3p &
3292: '0' &
3293: control_registers_out_i.tx_priority_txt2p &
3294: '0' &
3295: control_registers_out_i.tx_priority_txt1p when "011110",
3296: '0' & '0' &
3297: control_registers_in.ts_info_ts_bits &
3298: control_registers_in.alc_alc_id_field &
3299: control_registers_in.alc_alc_bit &
3300: '0' & '0' & '0' & '0' &
3301: control_registers_in.retr_ctr_retr_ctr_val &
3302: control_registers_in.err_capt_err_type &
3303: control_registers_in.err_capt_err_erp &
3304: control_registers_in.err_capt_err_pos when "011111",
3305: '0' & '0' & '0' & '0' & '0' & '0' &
3306: control_registers_out_i.ssp_cfg_ssp_src &
3307: control_registers_out_i.ssp_cfg_ssp_offset &
3308: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3309: control_registers_in.trv_delay_trv_delay_value when "100000",
3310: control_registers_in.rx_fr_ctr_rx_fr_ctr_val when "100001",
3311: control_registers_in.tx_fr_ctr_tx_fr_ctr_val when "100010",
3312: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3313: control_registers_in.debug_register_pc_sof &
3314: control_registers_in.debug_register_pc_ovr &
3315: control_registers_in.debug_register_pc_susp &
3316: control_registers_in.debug_register_pc_int &
3317: control_registers_in.debug_register_pc_eof &
3318: control_registers_in.debug_register_pc_ackd &
3319: control_registers_in.debug_register_pc_ack &
3320: control_registers_in.debug_register_pc_crcd &
3321: control_registers_in.debug_register_pc_crc &
3322: control_registers_in.debug_register_pc_stc &
3323: control_registers_in.debug_register_pc_dat &
3324: control_registers_in.debug_register_pc_con &
3325: control_registers_in.debug_register_pc_arb &
3326: control_registers_in.debug_register_destuff_count &
3327: control_registers_in.debug_register_stuff_count when "100011",
3328: control_registers_in.yolo_reg_yolo_val when "100100",
3329: control_registers_in.timestamp_low_timestamp_low when "100101",
3330: control_registers_in.timestamp_high_timestamp_high when "100110",
3331: (others => '0') when others;
3332:
3333: ----------------------------------------------------------------------------
3334: -- Output register
3335: ----------------------------------------------------------------------------
3336: p_read_data_reg : process(rst_n, clk_sys)
3337: begin
3338: if (rst_n = '0') then
3339: r_data <= (others => '0');
3340: elsif (rising_edge(clk_sys)) then
3341: if (cs = '1' and read = '1') then
3342: r_data <= r_data_comb and read_data_mask_n;
3343: end if;
3344: end if;
3345: end process;
3346:
3347: ----------------------------------------------------------------------------
3348: -- Read data mask - Byte enables
3349: ----------------------------------------------------------------------------
3350: read_data_mask_n <=
3351: be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &
3352: be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &
3353: be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &
3354: be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ;
3355:
3356: Control_registers_out <= Control_registers_out_i;
3357:
3358: -- <RELEASE_OFF>
3359: ----------------------------------------------------------------------------
3360: -- Functional coverage
3361: ----------------------------------------------------------------------------
3362: -- psl default clock is rising_edge(clk_sys);
3363: -- psl device_id_read_access_cov : cover
3364: -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1')))};
3365:
3366: -- psl version_read_access_cov : cover
3367: -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(2)='1') or (be(3)='1')))};
3368:
3369: -- psl mode_write_access_cov : cover
3370: -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};
3371:
3372: -- psl mode_read_access_cov : cover
3373: -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};
3374:
3375: -- psl settings_write_access_cov : cover
3376: -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};
3377:
3378: -- psl settings_read_access_cov : cover
3379: -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};
3380:
3381: -- psl status_read_access_cov : cover
3382: -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3383:
3384: -- psl command_write_access_cov : cover
3385: -- {((cs='1') and (write='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3386:
3387: -- psl int_stat_write_access_cov : cover
3388: -- {((cs='1') and (write='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};
3389:
3390: -- psl int_stat_read_access_cov : cover
3391: -- {((cs='1') and (read='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};
3392:
3393: -- psl int_ena_set_write_access_cov : cover
3394: -- {((cs='1') and (write='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};
3395:
3396: -- psl int_ena_set_read_access_cov : cover
3397: -- {((cs='1') and (read='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};
3398:
3399: -- psl int_ena_clr_write_access_cov : cover
3400: -- {((cs='1') and (write='1') and (reg_sel(6)='1') and ((be(0)='1') or (be(1)='1')))};
3401:
3402: -- psl int_mask_set_write_access_cov : cover
3403: -- {((cs='1') and (write='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};
3404:
3405: -- psl int_mask_set_read_access_cov : cover
3406: -- {((cs='1') and (read='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};
3407:
3408: -- psl int_mask_clr_write_access_cov : cover
3409: -- {((cs='1') and (write='1') and (reg_sel(8)='1') and ((be(0)='1') or (be(1)='1')))};
3410:
3411: -- psl btr_write_access_cov : cover
3412: -- {((cs='1') and (write='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3413:
3414: -- psl btr_read_access_cov : cover
3415: -- {((cs='1') and (read='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3416:
3417: -- psl btr_fd_write_access_cov : cover
3418: -- {((cs='1') and (write='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3419:
3420: -- psl btr_fd_read_access_cov : cover
3421: -- {((cs='1') and (read='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3422:
3423: -- psl ewl_write_access_cov : cover
3424: -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(0)='1')))};
3425:
3426: -- psl ewl_read_access_cov : cover
3427: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(0)='1')))};
3428:
3429: -- psl erp_write_access_cov : cover
3430: -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(1)='1')))};
3431:
3432: -- psl erp_read_access_cov : cover
3433: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(1)='1')))};
3434:
3435: -- psl fault_state_read_access_cov : cover
3436: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(2)='1') or (be(3)='1')))};
3437:
3438: -- psl rec_read_access_cov : cover
3439: -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(0)='1') or (be(1)='1')))};
3440:
3441: -- psl tec_read_access_cov : cover
3442: -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(2)='1') or (be(3)='1')))};
3443:
3444: -- psl err_norm_read_access_cov : cover
3445: -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(0)='1') or (be(1)='1')))};
3446:
3447: -- psl err_fd_read_access_cov : cover
3448: -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(2)='1') or (be(3)='1')))};
3449:
3450: -- psl ctr_pres_write_access_cov : cover
3451: -- {((cs='1') and (write='1') and (reg_sel(14)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3452:
3453: -- psl filter_a_mask_write_access_cov : cover
3454: -- {((cs='1') and (write='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3455:
3456: -- psl filter_a_mask_read_access_cov : cover
3457: -- {((cs='1') and (read='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3458:
3459: -- psl filter_a_val_write_access_cov : cover
3460: -- {((cs='1') and (write='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3461:
3462: -- psl filter_a_val_read_access_cov : cover
3463: -- {((cs='1') and (read='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3464:
3465: -- psl filter_b_mask_write_access_cov : cover
3466: -- {((cs='1') and (write='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3467:
3468: -- psl filter_b_mask_read_access_cov : cover
3469: -- {((cs='1') and (read='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3470:
3471: -- psl filter_b_val_write_access_cov : cover
3472: -- {((cs='1') and (write='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3473:
3474: -- psl filter_b_val_read_access_cov : cover
3475: -- {((cs='1') and (read='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3476:
3477: -- psl filter_c_mask_write_access_cov : cover
3478: -- {((cs='1') and (write='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3479:
3480: -- psl filter_c_mask_read_access_cov : cover
3481: -- {((cs='1') and (read='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3482:
3483: -- psl filter_c_val_write_access_cov : cover
3484: -- {((cs='1') and (write='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3485:
3486: -- psl filter_c_val_read_access_cov : cover
3487: -- {((cs='1') and (read='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3488:
3489: -- psl filter_ran_low_write_access_cov : cover
3490: -- {((cs='1') and (write='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3491:
3492: -- psl filter_ran_low_read_access_cov : cover
3493: -- {((cs='1') and (read='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3494:
3495: -- psl filter_ran_high_write_access_cov : cover
3496: -- {((cs='1') and (write='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3497:
3498: -- psl filter_ran_high_read_access_cov : cover
3499: -- {((cs='1') and (read='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3500:
3501: -- psl filter_control_write_access_cov : cover
3502: -- {((cs='1') and (write='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))};
3503:
3504: -- psl filter_control_read_access_cov : cover
3505: -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))};
3506:
3507: -- psl filter_status_read_access_cov : cover
3508: -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(2)='1') or (be(3)='1')))};
3509:
3510: -- psl rx_mem_info_read_access_cov : cover
3511: -- {((cs='1') and (read='1') and (reg_sel(24)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3512:
3513: -- psl rx_pointers_read_access_cov : cover
3514: -- {((cs='1') and (read='1') and (reg_sel(25)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3515:
3516: -- psl rx_status_read_access_cov : cover
3517: -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(0)='1') or (be(1)='1')))};
3518:
3519: -- psl rx_settings_write_access_cov : cover
3520: -- {((cs='1') and (write='1') and (reg_sel(26)='1') and ((be(2)='1')))};
3521:
3522: -- psl rx_settings_read_access_cov : cover
3523: -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(2)='1')))};
3524:
3525: -- psl rx_data_read_access_cov : cover
3526: -- {((cs='1') and (read='1') and (reg_sel(27)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3527:
3528: -- psl tx_status_read_access_cov : cover
3529: -- {((cs='1') and (read='1') and (reg_sel(28)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3530:
3531: -- psl tx_command_write_access_cov : cover
3532: -- {((cs='1') and (write='1') and (reg_sel(29)='1') and ((be(0)='1') or (be(1)='1')))};
3533:
3534: -- psl txtb_info_read_access_cov : cover
3535: -- {((cs='1') and (read='1') and (reg_sel(29)='1') and ((be(2)='1') or (be(3)='1')))};
3536:
3537: -- psl tx_priority_write_access_cov : cover
3538: -- {((cs='1') and (write='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3539:
3540: -- psl tx_priority_read_access_cov : cover
3541: -- {((cs='1') and (read='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3542:
3543: -- psl err_capt_read_access_cov : cover
3544: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(0)='1')))};
3545:
3546: -- psl retr_ctr_read_access_cov : cover
3547: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(1)='1')))};
3548:
3549: -- psl alc_read_access_cov : cover
3550: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(2)='1')))};
3551:
3552: -- psl ts_info_read_access_cov : cover
3553: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(3)='1')))};
3554:
3555: -- psl trv_delay_read_access_cov : cover
3556: -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(0)='1') or (be(1)='1')))};
3557:
3558: -- psl ssp_cfg_write_access_cov : cover
3559: -- {((cs='1') and (write='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))};
3560:
3561: -- psl ssp_cfg_read_access_cov : cover
3562: -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))};
3563:
3564: -- psl rx_fr_ctr_read_access_cov : cover
3565: -- {((cs='1') and (read='1') and (reg_sel(33)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3566:
3567: -- psl tx_fr_ctr_read_access_cov : cover
3568: -- {((cs='1') and (read='1') and (reg_sel(34)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3569:
3570: -- psl debug_register_read_access_cov : cover
3571: -- {((cs='1') and (read='1') and (reg_sel(35)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3572:
3573: -- psl yolo_reg_read_access_cov : cover
3574: -- {((cs='1') and (read='1') and (reg_sel(36)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3575:
3576: -- psl timestamp_low_read_access_cov : cover
3577: -- {((cs='1') and (read='1') and (reg_sel(37)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3578:
3579: -- psl timestamp_high_read_access_cov : cover
3580: -- {((cs='1') and (read='1') and (reg_sel(38)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
3581:
3582: -- <RELEASE_ON>
3583:
3584: end architecture rtl;