NVC code coverage report
Hierarchy
CTU_CAN_FD_TB
TB_TOP_CTU_CAN_FD
I_DUT
I_RST_SYNC
I_MR_TOP
G_TXTB_PORT_A_CS(0)
G_TXTB_PORT_A_CS(1)
G_TXTB_PORT_A_CS(2)
G_TXTB_PORT_A_CS(3)
G_TXTB_PORT_A_CS(4)
G_TXTB_PORT_A_CS(5)
G_TXTB_PORT_A_CS(6)
G_TXTB_PORT_A_CS(7)
I_CLK_GATE_CONTROL_REGS
G_TECH_ASIC
G_TECH_FPGA
I_CLK_GATE_TEST_REGS
G_TECH_ASIC
G_TECH_FPGA
I_CONTROL_REGISTERS_REG_MAP
I_ADDRESS_DECODER_CONTROL_REGISTERS
G_ADDR_DEC(0)
G_ADDR_DEC(1)
G_ADDR_DEC(2)
G_ADDR_DEC(3)
G_ADDR_DEC(4)
G_ADDR_DEC(5)
G_ADDR_DEC(6)
G_ADDR_DEC(7)
G_ADDR_DEC(8)
G_ADDR_DEC(9)
G_ADDR_DEC(10)
G_ADDR_DEC(11)
G_ADDR_DEC(12)
G_ADDR_DEC(13)
G_ADDR_DEC(14)
G_ADDR_DEC(15)
G_ADDR_DEC(16)
G_ADDR_DEC(17)
G_ADDR_DEC(18)
G_ADDR_DEC(19)
G_ADDR_DEC(20)
G_ADDR_DEC(21)
G_ADDR_DEC(22)
G_ADDR_DEC(23)
G_ADDR_DEC(24)
G_ADDR_DEC(25)
G_ADDR_DEC(26)
G_ADDR_DEC(27)
G_ADDR_DEC(28)
G_ADDR_DEC(29)
G_ADDR_DEC(30)
G_ADDR_DEC(31)
G_ADDR_DEC(32)
G_ADDR_DEC(33)
G_ADDR_DEC(34)
G_ADDR_DEC(35)
G_ADDR_DEC(36)
G_ADDR_DEC(37)
G_ADDR_DEC(38)
G_ADDR_DEC_REG_F
I_MODE_RST_REG
G_BIT(0)
I_MODE_BMM_REG
G_BIT(0)
I_MODE_STM_REG
G_BIT(0)
I_MODE_AFM_REG
G_BIT(0)
I_MODE_FDE_REG
G_BIT(0)
I_MODE_TTTM_REG
G_BIT(0)
I_MODE_ROM_REG
G_BIT(0)
I_MODE_ACF_REG
G_BIT(0)
I_MODE_TSTM_REG
G_BIT(0)
I_MODE_RXBAM_REG
G_BIT(0)
I_MODE_TXBBM_REG
G_BIT(0)
I_MODE_SAM_REG
G_BIT(0)
I_MODE_ERFM_REG
G_BIT(0)
I_SETTINGS_RTRLE_REG
G_BIT(0)
I_SETTINGS_RTRTH_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_SETTINGS_ILBP_REG
G_BIT(0)
I_SETTINGS_ENA_REG
G_BIT(0)
I_SETTINGS_NISOFD_REG
G_BIT(0)
I_SETTINGS_PEX_REG
G_BIT(0)
I_SETTINGS_TBFBO_REG
G_BIT(0)
I_SETTINGS_FDRF_REG
G_BIT(0)
I_SETTINGS_PCHKE_REG
G_BIT(0)
I_COMMAND_RXRPMV_REG
G_BIT(0)
I_COMMAND_RRB_REG
G_BIT(0)
I_COMMAND_CDO_REG
G_BIT(0)
I_COMMAND_ERCRST_REG
G_BIT(0)
I_COMMAND_RXFCRST_REG
G_BIT(0)
I_COMMAND_TXFCRST_REG
G_BIT(0)
I_COMMAND_CPEXS_REG
G_BIT(0)
I_COMMAND_CRXPE_REG
G_BIT(0)
I_COMMAND_CTXPE_REG
G_BIT(0)
I_COMMAND_CTXDPE_REG
G_BIT(0)
I_INT_STAT_RXI_REG
G_BIT(0)
I_INT_STAT_TXI_REG
G_BIT(0)
I_INT_STAT_EWLI_REG
G_BIT(0)
I_INT_STAT_DOI_REG
G_BIT(0)
I_INT_STAT_FCSI_REG
G_BIT(0)
I_INT_STAT_ALI_REG
G_BIT(0)
I_INT_STAT_BEI_REG
G_BIT(0)
I_INT_STAT_OFI_REG
G_BIT(0)
I_INT_STAT_RXFI_REG
G_BIT(0)
I_INT_STAT_BSI_REG
G_BIT(0)
I_INT_STAT_RBNEI_REG
G_BIT(0)
I_INT_STAT_TXBHCI_REG
G_BIT(0)
I_INT_ENA_SET_INT_ENA_SET_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_ENA_SET_INT_ENA_SET_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_INT_ENA_CLR_INT_ENA_CLR_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_ENA_CLR_INT_ENA_CLR_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_INT_MASK_SET_INT_MASK_SET_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_MASK_SET_INT_MASK_SET_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_INT_MASK_CLR_INT_MASK_CLR_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_MASK_CLR_INT_MASK_CLR_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_BTR_PROP_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
I_BTR_PH1_SLICE_1_REG
G_BIT(0)
I_BTR_PH1_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_PH2_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_PH2_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_BRP_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_BRP_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_SJW_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_FD_PROP_FD_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
I_BTR_FD_PH1_FD_SLICE_1_REG
G_BIT(0)
I_BTR_FD_PH1_FD_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_BTR_FD_PH2_FD_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_FD_PH2_FD_SLICE_2_REG
G_BIT(0)
G_BIT(1)
I_BTR_FD_BRP_FD_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_FD_BRP_FD_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_FD_SJW_FD_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_EWL_EW_LIMIT_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_ERP_ERP_LIMIT_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_CTR_PRES_CTPV_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_CTR_PRES_CTPV_SLICE_2_REG
G_BIT(0)
I_CTR_PRES_PTX_REG
G_BIT(0)
I_CTR_PRES_PRX_REG
G_BIT(0)
I_CTR_PRES_ENORM_REG
G_BIT(0)
I_CTR_PRES_EFD_REG
G_BIT(0)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_1_T
I_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_T
I_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_3_T
I_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_T
I_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_1_T
I_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_2_T
I_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_3_T
I_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_4_T
I_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_1_T
I_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_2_T
I_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_3_T
I_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_4_T
I_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_1_T
I_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_2_T
I_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_3_T
I_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_T
I_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_1_T
I_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_T
I_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_3_T
I_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_4_T
I_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_1_T
I_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_2_T
I_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_3_T
I_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_4_T
I_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_T
I_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_2_T
I_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_3_T
I_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_4_T
I_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_T
I_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_2_T
I_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_3_T
I_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_4_T
I_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_FILTER_CONTROL_FANB_REG
G_BIT(0)
I_FILTER_CONTROL_FANE_REG
G_BIT(0)
I_FILTER_CONTROL_FAFB_REG
G_BIT(0)
I_FILTER_CONTROL_FAFE_REG
G_BIT(0)
I_FILTER_CONTROL_FBNB_REG
G_BIT(0)
I_FILTER_CONTROL_FBNE_REG
G_BIT(0)
I_FILTER_CONTROL_FBFB_REG
G_BIT(0)
I_FILTER_CONTROL_FBFE_REG
G_BIT(0)
I_FILTER_CONTROL_FCNB_REG
G_BIT(0)
I_FILTER_CONTROL_FCNE_REG
G_BIT(0)
I_FILTER_CONTROL_FCFB_REG
G_BIT(0)
I_FILTER_CONTROL_FCFE_REG
G_BIT(0)
I_FILTER_CONTROL_FRNB_REG
G_BIT(0)
I_FILTER_CONTROL_FRNE_REG
G_BIT(0)
I_FILTER_CONTROL_FRFB_REG
G_BIT(0)
I_FILTER_CONTROL_FRFE_REG
G_BIT(0)
I_RX_SETTINGS_RTSOP_REG
G_BIT(0)
I_RX_DATA_ACCESS_SIGNALLER
I_TX_COMMAND_TXCE_REG
G_BIT(0)
I_TX_COMMAND_TXCR_REG
G_BIT(0)
I_TX_COMMAND_TXCA_REG
G_BIT(0)
I_TX_COMMAND_TXB1_REG
G_BIT(0)
I_TX_COMMAND_TXB2_REG
G_BIT(0)
G_TX_COMMAND_TXB3_T
I_TX_COMMAND_TXB3_REG
G_BIT(0)
G_TX_COMMAND_TXB4_T
I_TX_COMMAND_TXB4_REG
G_BIT(0)
G_TX_COMMAND_TXB5_T
I_TX_COMMAND_TXB5_REG
G_BIT(0)
G_TX_COMMAND_TXB6_T
I_TX_COMMAND_TXB6_REG
G_BIT(0)
G_TX_COMMAND_TXB7_T
I_TX_COMMAND_TXB7_REG
G_BIT(0)
G_TX_COMMAND_TXB8_T
I_TX_COMMAND_TXB8_REG
G_BIT(0)
I_TX_PRIORITY_TXT1P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_TX_PRIORITY_TXT2P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT3P_T
I_TX_PRIORITY_TXT3P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT4P_T
I_TX_PRIORITY_TXT4P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT5P_T
I_TX_PRIORITY_TXT5P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT6P_T
I_TX_PRIORITY_TXT6P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT7P_T
I_TX_PRIORITY_TXT7P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT8P_T
I_TX_PRIORITY_TXT8P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_SSP_CFG_SSP_OFFSET_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_SSP_CFG_SSP_SRC_REG
G_BIT(0)
G_BIT(1)
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_1_F
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_2_F
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_3_F
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_4_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_1_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_2_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_3_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_1_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_3_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_4_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_1_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_2_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_3_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_4_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_2_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_3_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_4_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_2_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_3_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_4_F
G_TX_COMMAND_TXB5_F
G_TX_COMMAND_TXB6_F
G_TX_COMMAND_TXB7_F
G_TX_COMMAND_TXB8_F
G_TX_PRIORITY_TXT5P_F
G_TX_PRIORITY_TXT6P_F
G_TX_PRIORITY_TXT7P_F
G_TX_PRIORITY_TXT8P_F
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_1_F
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_F
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_3_F
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_1_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_2_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_3_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_4_F
G_TX_COMMAND_TXB3_F
G_TX_COMMAND_TXB4_F
G_TX_PRIORITY_TXT3P_F
G_TX_PRIORITY_TXT4P_F
G_TEST_REGISTERS_TRUE
I_TEST_REGISTERS_REG_MAP
I_ADDRESS_DECODER_TEST_REGISTERS
G_ADDR_DEC(0)
G_ADDR_DEC(1)
G_ADDR_DEC(2)
G_ADDR_DEC(3)
G_ADDR_DEC_REG_F
I_TST_CONTROL_TMAENA_REG
G_BIT(0)
I_TST_CONTROL_TWRSTB_REG
G_BIT(0)
I_TST_DEST_TST_ADDR_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_DEST_TST_ADDR_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_DEST_TST_MTGT_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_TST_WDATA_TST_WDATA_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_WDATA_TST_WDATA_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_WDATA_TST_WDATA_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_WDATA_TST_WDATA_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_TXT_BUF_TEST_DATA_PADDING(0)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_TEST_DATA_PADDING(1)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_TEST_DATA_PADDING(2)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(3)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(4)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(5)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(6)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(7)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_PADDING_INDEX_FALSE
I_SOFT_RST_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_GLOBAL_RST_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
G_MT_2_TXT_BUFFS
G_MT_3_TXT_BUFFS
G_MT_4_TXT_BUFFS
G_MT_5_TXT_BUFFS
G_MT_6_TXT_BUFFS
G_MT_7_TXT_BUFFS
G_TXTB_FUNC_COV(0)
G_TXTB_FUNC_COV(1)
G_TXTB_FUNC_COV(2)
G_TXTB_FUNC_COV(3)
G_TXTB_FUNC_COV(4)
G_TXTB_FUNC_COV(5)
G_TXTB_FUNC_COV(6)
G_TXTB_FUNC_COV(7)
I_RXB_TOP
I_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_RXB_FSM
ASSERTIONS_BLOCK
I_RXB_POINTERS
I_CLK_GATE_RXB_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
I_RXB_RAM
I_DP_INF_RAM
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_WRITE
I_PARITY_CALCULATOR_READ
G_PARITY_FALSE
G_TXTB_PARITY_TRUE
I_TXTB_PORT_A_PARITY_CALCULATOR
G_TXT_BUF_COMP(0)
G_TXT_BUF_EVEN
I_TXTB_EVEN_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
G_PARITY_FALSE
I_TXTB_FSM
G_TXT_BUF_COMP(1)
G_TXT_BUF_ODD
I_TXTB_ODD_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
G_PARITY_FALSE
I_TXTB_FSM
G_TXT_BUF_COMP(2)
G_TXT_BUF_EVEN
I_TXTB_EVEN_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
I_TXTB_FSM
G_TXT_BUF_COMP(3)
G_TXT_BUF_ODD
I_TXTB_ODD_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
I_TXTB_FSM
G_TXT_BUF_COMP(4)
G_TXT_BUF_EVEN
I_TXTB_EVEN_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
I_TXTB_FSM
G_TXT_BUF_COMP(5)
G_TXT_BUF_ODD
I_TXTB_ODD_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
I_TXTB_FSM
G_TXT_BUF_COMP(6)
G_TXT_BUF_EVEN
I_TXTB_EVEN_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
I_TXTB_FSM
G_TXT_BUF_COMP(7)
G_TXT_BUF_ODD
I_TXTB_ODD_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_TRUE
I_PARITY_CALCULATOR_READ
I_TXTB_FSM
I_TXARB_TOP
I_TXARB_PRIORITY_DECODER
G_L0(0)
G_L0(1)
G_L0(2)
G_L0(3)
G_L0(4)
G_L0(5)
G_L0(6)
G_L0(7)
G_FILL_ZEROES
I_TXARB_FSM
G_TXTB_PRIORITY(0)
G_TXTB_PRIORITY_EVEN
G_TXTB_PRIORITY(1)
G_TXTB_PRIORITY_ODD
G_TXTB_PRIORITY(2)
G_TXTB_PRIORITY_EVEN
G_TXTB_PRIORITY(3)
G_TXTB_PRIORITY_ODD
G_TXTB_PRIORITY(4)
G_TXTB_PRIORITY_EVEN
G_TXTB_PRIORITY(5)
G_TXTB_PRIORITY_ODD
G_TXTB_PRIORITY(6)
G_TXTB_PRIORITY_EVEN
G_TXTB_PRIORITY(7)
G_TXTB_PRIORITY_ODD
I_FF_TOP
I_FF_BIT_FILTER_A
G_FILT_POS
G_FILT_NEG
I_FF_BIT_FILTER_B
G_FILT_POS
G_FILT_NEG
I_FF_BIT_FILTER_C
G_FILT_POS
G_FILT_NEG
I_FF_RANGE_FILTER
G_FILT_POS
G_FILT_NEG
G_FILT_SUP_TRUE
G_FILT_SUP_FALSE
I_IM_TOP
G_INT_MODULE(0)
I_IM_CHANNEL
G_INT_MODULE(1)
I_IM_CHANNEL
G_INT_MODULE(2)
I_IM_CHANNEL
G_INT_MODULE(3)
I_IM_CHANNEL
G_INT_MODULE(4)
I_IM_CHANNEL
G_INT_MODULE(5)
I_IM_CHANNEL
G_INT_MODULE(6)
I_IM_CHANNEL
G_INT_MODULE(7)
I_IM_CHANNEL
G_INT_MODULE(8)
I_IM_CHANNEL
G_INT_MODULE(9)
I_IM_CHANNEL
G_INT_MODULE(10)
I_IM_CHANNEL
G_INT_MODULE(11)
I_IM_CHANNEL
I_DFF_INT_OUTPUT_REG
I_MAC_TOP
I_MAC_PC_TOP
I_MAC_PC_FSM
I_DLC_DECODER_TX
I_DLC_DECODER_RX
I_DLC_DECODER_RX_INST_COMB
I_MAC_PC_CONTROL_COUNTER
I_MAC_PC_REINTEGRATION_COUNTER
I_MAC_PC_RETRANSMITT_COUNTER
I_MAC_PC_ERR_DETECTOR
I_MAC_PC_TX_SHIFT_REG
I_TX_SHIFT_REG
I_MAC_PC_RX_SHIFT_REG
I_RX_SHIFT_RES_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
G_RX_SHIFT_CMD(0)
G_RX_SHIFT_CMD(1)
G_RX_SHIFT_CMD(2)
G_RX_SHIFT_CMD(3)
I_SHIFT_REG_BYTE
G_BYTE_SHIFT_REG(0)
G_FIRST_BYTE
G_BYTE_SHIFT_REG(1)
G_NEXT_BYTES
G_BYTE_SHIFT_REG(2)
G_NEXT_BYTES
G_BYTE_SHIFT_REG(3)
G_NEXT_BYTES
I_MAC_OPERATION_CONTROL
I_MAC_FC_TOP
I_MAC_FC_FSM
I_MAC_FC_ERR_COUNTERS
I_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_MAC_FC_RULES
I_MAC_CRC_TOP
I_MAC_CRC_CALC_15
I_MAC_CRC_CALC_17_RX
I_MAC_CRC_CALC_21_RX
I_MAC_BIT_STUFFING
I_DFF_ENA_REG
I_DFF_FIXED_STUFF_REG
I_DFF_DATA_OUT_REG
I_DFF_HALT_REG
I_MAC_BIT_DESTUFFING
I_DFF_ENA_REG
I_DFF_FIXED_STUFF_REG
I_DFF_DESTUFFED_FLAG_REG
I_DFF_ERR_REG
I_DFF_PREV_VAL_REG
I_DFF_DATA_OUT_VAL_REG
G_BUS_TRAFFIC_CTRS
I_MAC_BUS_TRAFFIC_COUNTERS
I_TX_CTR_REG_RST
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_RX_CTR_REG_RST
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_MAC_TRIGGER_MUX
I_CRC_TRIG_TX_WBS_REG
I_CRC_DATA_RX_WBS_REG
G_NO_BUS_TRAFFIC_CTRS
I_BTL_TOP
I_BTL_CFG_CAPTURE
I_BTL_SYNCHRONISATION_CHECKER
I_BTL_SEGMENT_METER_NBT
I_BTL_COUNTERS_NBT
I_BTL_SEGMENT_METER_DBT
I_BTL_COUNTERS_DBT
I_BTL_SEGMENT_END_DETECTOR
G_SEGM_END_REQ_CAPTURE(1)
G_SEGM_END_REQ_CAPTURE(2)
I_BTL_FSM
I_BTL_TRIGGER_GENERATOR
I_BM_TOP
I_CAN_RX_SIG_SYNC
I_BM_TRV_DELAY_MEAS
I_TRV_DELAY_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_BM_DATA_EDGE_DETECTOR
I_SHIFT_REGS_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_TX_TRIGGER_REG
I_BM_SSP_GENERATOR
I_BM_TX_DATA_CACHE
I_BM_BIT_ERR_DETECTOR
I_BM_SAMPLE_MUX
G_TXTB_ASR(0)
G_TXTB_ASR(1)
G_TXTB_ASR(2)
G_TXTB_ASR(3)
G_TXTB_ASR(4)
G_TXTB_ASR(5)
G_TXTB_ASR(6)
G_TXTB_ASR(7)
G_TXTB_PARITY_FALSE
I_CTU_CAN_FD_VIP
I_RESET_AGENT
I_CLK_GEN_AGENT
I_MEM_BUS_AGENT
G_CS(0)
G_CS(1)
I_INTERRUPT_AGENT
I_TIMESTAMP_AGENT
I_TEST_PROBE_AGENT
I_TEST_CONTROLLER_AGENT
G_COMPLIANCE_TESTS
G_FEATURE_TEST_AGENT
I_FEATURE_TEST_AGENT
I_TEST_NODE
I_RST_SYNC
I_MR_TOP
G_TXTB_PORT_A_CS(0)
G_TXTB_PORT_A_CS(1)
G_TXTB_PORT_A_CS(2)
G_TXTB_PORT_A_CS(3)
I_CLK_GATE_CONTROL_REGS
G_TECH_ASIC
I_CLK_GATE_TEST_REGS
G_TECH_ASIC
I_CONTROL_REGISTERS_REG_MAP
I_ADDRESS_DECODER_CONTROL_REGISTERS
G_ADDR_DEC(0)
G_ADDR_DEC(1)
G_ADDR_DEC(2)
G_ADDR_DEC(3)
G_ADDR_DEC(4)
G_ADDR_DEC(5)
G_ADDR_DEC(6)
G_ADDR_DEC(7)
G_ADDR_DEC(8)
G_ADDR_DEC(9)
G_ADDR_DEC(10)
G_ADDR_DEC(11)
G_ADDR_DEC(12)
G_ADDR_DEC(13)
G_ADDR_DEC(14)
G_ADDR_DEC(15)
G_ADDR_DEC(16)
G_ADDR_DEC(17)
G_ADDR_DEC(18)
G_ADDR_DEC(19)
G_ADDR_DEC(20)
G_ADDR_DEC(21)
G_ADDR_DEC(22)
G_ADDR_DEC(23)
G_ADDR_DEC(24)
G_ADDR_DEC(25)
G_ADDR_DEC(26)
G_ADDR_DEC(27)
G_ADDR_DEC(28)
G_ADDR_DEC(29)
G_ADDR_DEC(30)
G_ADDR_DEC(31)
G_ADDR_DEC(32)
G_ADDR_DEC(33)
G_ADDR_DEC(34)
G_ADDR_DEC(35)
G_ADDR_DEC(36)
G_ADDR_DEC(37)
G_ADDR_DEC(38)
G_ADDR_DEC_REG_F
I_MODE_RST_REG
G_BIT(0)
I_MODE_BMM_REG
G_BIT(0)
I_MODE_STM_REG
G_BIT(0)
I_MODE_AFM_REG
G_BIT(0)
I_MODE_FDE_REG
G_BIT(0)
I_MODE_TTTM_REG
G_BIT(0)
I_MODE_ROM_REG
G_BIT(0)
I_MODE_ACF_REG
G_BIT(0)
I_MODE_TSTM_REG
G_BIT(0)
I_MODE_RXBAM_REG
G_BIT(0)
I_MODE_TXBBM_REG
G_BIT(0)
I_MODE_SAM_REG
G_BIT(0)
I_MODE_ERFM_REG
G_BIT(0)
I_SETTINGS_RTRLE_REG
G_BIT(0)
I_SETTINGS_RTRTH_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_SETTINGS_ILBP_REG
G_BIT(0)
I_SETTINGS_ENA_REG
G_BIT(0)
I_SETTINGS_NISOFD_REG
G_BIT(0)
I_SETTINGS_PEX_REG
G_BIT(0)
I_SETTINGS_TBFBO_REG
G_BIT(0)
I_SETTINGS_FDRF_REG
G_BIT(0)
I_SETTINGS_PCHKE_REG
G_BIT(0)
I_COMMAND_RXRPMV_REG
G_BIT(0)
I_COMMAND_RRB_REG
G_BIT(0)
I_COMMAND_CDO_REG
G_BIT(0)
I_COMMAND_ERCRST_REG
G_BIT(0)
I_COMMAND_RXFCRST_REG
G_BIT(0)
I_COMMAND_TXFCRST_REG
G_BIT(0)
I_COMMAND_CPEXS_REG
G_BIT(0)
I_COMMAND_CRXPE_REG
G_BIT(0)
I_COMMAND_CTXPE_REG
G_BIT(0)
I_COMMAND_CTXDPE_REG
G_BIT(0)
I_INT_STAT_RXI_REG
G_BIT(0)
I_INT_STAT_TXI_REG
G_BIT(0)
I_INT_STAT_EWLI_REG
G_BIT(0)
I_INT_STAT_DOI_REG
G_BIT(0)
I_INT_STAT_FCSI_REG
G_BIT(0)
I_INT_STAT_ALI_REG
G_BIT(0)
I_INT_STAT_BEI_REG
G_BIT(0)
I_INT_STAT_OFI_REG
G_BIT(0)
I_INT_STAT_RXFI_REG
G_BIT(0)
I_INT_STAT_BSI_REG
G_BIT(0)
I_INT_STAT_RBNEI_REG
G_BIT(0)
I_INT_STAT_TXBHCI_REG
G_BIT(0)
I_INT_ENA_SET_INT_ENA_SET_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_ENA_SET_INT_ENA_SET_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_INT_ENA_CLR_INT_ENA_CLR_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_ENA_CLR_INT_ENA_CLR_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_INT_MASK_SET_INT_MASK_SET_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_MASK_SET_INT_MASK_SET_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_INT_MASK_CLR_INT_MASK_CLR_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_INT_MASK_CLR_INT_MASK_CLR_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_BTR_PROP_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
I_BTR_PH1_SLICE_1_REG
G_BIT(0)
I_BTR_PH1_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_PH2_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_PH2_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_BRP_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_BRP_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_SJW_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_FD_PROP_FD_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
I_BTR_FD_PH1_FD_SLICE_1_REG
G_BIT(0)
I_BTR_FD_PH1_FD_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_BTR_FD_PH2_FD_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_FD_PH2_FD_SLICE_2_REG
G_BIT(0)
G_BIT(1)
I_BTR_FD_BRP_FD_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_BTR_FD_BRP_FD_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_BTR_FD_SJW_FD_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
I_EWL_EW_LIMIT_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_ERP_ERP_LIMIT_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_CTR_PRES_CTPV_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_CTR_PRES_CTPV_SLICE_2_REG
G_BIT(0)
I_CTR_PRES_PTX_REG
G_BIT(0)
I_CTR_PRES_PRX_REG
G_BIT(0)
I_CTR_PRES_ENORM_REG
G_BIT(0)
I_CTR_PRES_EFD_REG
G_BIT(0)
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_1_F
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_F
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_3_F
G_FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_1_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_2_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_3_F
G_FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_4_F
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_1_F
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_2_F
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_3_F
G_FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_4_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_1_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_2_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_3_F
G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_1_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_3_F
G_FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_4_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_1_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_2_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_3_F
G_FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_4_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_2_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_3_F
G_FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_4_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_2_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_3_F
G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_4_F
I_FILTER_CONTROL_FANB_REG
G_BIT(0)
I_FILTER_CONTROL_FANE_REG
G_BIT(0)
I_FILTER_CONTROL_FAFB_REG
G_BIT(0)
I_FILTER_CONTROL_FAFE_REG
G_BIT(0)
I_FILTER_CONTROL_FBNB_REG
G_BIT(0)
I_FILTER_CONTROL_FBNE_REG
G_BIT(0)
I_FILTER_CONTROL_FBFB_REG
G_BIT(0)
I_FILTER_CONTROL_FBFE_REG
G_BIT(0)
I_FILTER_CONTROL_FCNB_REG
G_BIT(0)
I_FILTER_CONTROL_FCNE_REG
G_BIT(0)
I_FILTER_CONTROL_FCFB_REG
G_BIT(0)
I_FILTER_CONTROL_FCFE_REG
G_BIT(0)
I_FILTER_CONTROL_FRNB_REG
G_BIT(0)
I_FILTER_CONTROL_FRNE_REG
G_BIT(0)
I_FILTER_CONTROL_FRFB_REG
G_BIT(0)
I_FILTER_CONTROL_FRFE_REG
G_BIT(0)
I_RX_SETTINGS_RTSOP_REG
G_BIT(0)
I_RX_DATA_ACCESS_SIGNALLER
I_TX_COMMAND_TXCE_REG
G_BIT(0)
I_TX_COMMAND_TXCR_REG
G_BIT(0)
I_TX_COMMAND_TXCA_REG
G_BIT(0)
I_TX_COMMAND_TXB1_REG
G_BIT(0)
I_TX_COMMAND_TXB2_REG
G_BIT(0)
G_TX_COMMAND_TXB3_T
I_TX_COMMAND_TXB3_REG
G_BIT(0)
G_TX_COMMAND_TXB4_T
I_TX_COMMAND_TXB4_REG
G_BIT(0)
G_TX_COMMAND_TXB5_F
G_TX_COMMAND_TXB6_F
G_TX_COMMAND_TXB7_F
G_TX_COMMAND_TXB8_F
I_TX_PRIORITY_TXT1P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
I_TX_PRIORITY_TXT2P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT3P_T
I_TX_PRIORITY_TXT3P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT4P_T
I_TX_PRIORITY_TXT4P_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_TX_PRIORITY_TXT5P_F
G_TX_PRIORITY_TXT6P_F
G_TX_PRIORITY_TXT7P_F
G_TX_PRIORITY_TXT8P_F
I_SSP_CFG_SSP_OFFSET_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_SSP_CFG_SSP_SRC_REG
G_BIT(0)
G_BIT(1)
G_TEST_REGISTERS_TRUE
I_TEST_REGISTERS_REG_MAP
I_ADDRESS_DECODER_TEST_REGISTERS
G_ADDR_DEC(0)
G_ADDR_DEC(1)
G_ADDR_DEC(2)
G_ADDR_DEC(3)
G_ADDR_DEC_REG_F
I_TST_CONTROL_TMAENA_REG
G_BIT(0)
I_TST_CONTROL_TWRSTB_REG
G_BIT(0)
I_TST_DEST_TST_ADDR_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_DEST_TST_ADDR_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_DEST_TST_MTGT_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
I_TST_WDATA_TST_WDATA_SLICE_1_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_WDATA_TST_WDATA_SLICE_2_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_WDATA_TST_WDATA_SLICE_3_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
I_TST_WDATA_TST_WDATA_SLICE_4_REG
G_BIT(0)
G_BIT(1)
G_BIT(2)
G_BIT(3)
G_BIT(4)
G_BIT(5)
G_BIT(6)
G_BIT(7)
G_TXT_BUF_TEST_DATA_PADDING(0)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_TEST_DATA_PADDING(1)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_TEST_DATA_PADDING(2)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_TEST_DATA_PADDING(3)
G_TXT_BUF_PADDING_INDEX_TRUE
G_TXT_BUF_TEST_DATA_PADDING(4)
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(5)
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(6)
G_TXT_BUF_PADDING_INDEX_FALSE
G_TXT_BUF_TEST_DATA_PADDING(7)
G_TXT_BUF_PADDING_INDEX_FALSE
I_SOFT_RST_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_GLOBAL_RST_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
G_MT_2_TXT_BUFFS
G_MT_3_TXT_BUFFS
G_TXTB_FUNC_COV(0)
G_TXTB_FUNC_COV(1)
G_TXTB_FUNC_COV(2)
G_TXTB_FUNC_COV(3)
I_RXB_TOP
I_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_RXB_FSM
ASSERTIONS_BLOCK
I_RXB_POINTERS
I_CLK_GATE_RXB_RAM_COMP
G_TECH_ASIC
I_RXB_RAM
I_DP_INF_RAM
G_RAM_RST_FALSE
G_SYNC
G_PARITY_FALSE
G_TXTB_PARITY_FALSE
G_TXT_BUF_COMP(0)
G_TXT_BUF_EVEN
I_TXTB_EVEN_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_FALSE
I_TXTB_FSM
G_TXT_BUF_COMP(1)
G_TXT_BUF_ODD
I_TXTB_ODD_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_FALSE
I_TXTB_FSM
G_TXT_BUF_COMP(2)
G_TXT_BUF_EVEN
I_TXTB_EVEN_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_FALSE
I_TXTB_FSM
G_TXT_BUF_COMP(3)
G_TXT_BUF_ODD
I_TXTB_ODD_TOP
I_CLK_GATE_TXTB_RAM_COMP
G_TECH_ASIC
I_TXTB_RAM
I_DP_INF_RAM_BE
G_BYTE(0)
G_BYTE(1)
G_BYTE(2)
G_BYTE(3)
G_RAM_RST_FALSE
G_SYNC
G_PARITY_FALSE
I_TXTB_FSM
I_TXARB_TOP
I_TXARB_PRIORITY_DECODER
G_L0(0)
G_L0(1)
G_L0(2)
G_L0(3)
G_FILL_ZEROES
I_TXARB_FSM
G_TXTB_PRIORITY(0)
G_TXTB_PRIORITY_EVEN
G_TXTB_PRIORITY(1)
G_TXTB_PRIORITY_ODD
G_TXTB_PRIORITY(2)
G_TXTB_PRIORITY_EVEN
G_TXTB_PRIORITY(3)
G_TXTB_PRIORITY_ODD
I_FF_TOP
I_FF_BIT_FILTER_A
G_FILT_NEG
I_FF_BIT_FILTER_B
G_FILT_NEG
I_FF_BIT_FILTER_C
G_FILT_NEG
I_FF_RANGE_FILTER
G_FILT_NEG
G_FILT_SUP_FALSE
I_IM_TOP
G_INT_MODULE(0)
I_IM_CHANNEL
G_INT_MODULE(1)
I_IM_CHANNEL
G_INT_MODULE(2)
I_IM_CHANNEL
G_INT_MODULE(3)
I_IM_CHANNEL
G_INT_MODULE(4)
I_IM_CHANNEL
G_INT_MODULE(5)
I_IM_CHANNEL
G_INT_MODULE(6)
I_IM_CHANNEL
G_INT_MODULE(7)
I_IM_CHANNEL
G_INT_MODULE(8)
I_IM_CHANNEL
G_INT_MODULE(9)
I_IM_CHANNEL
G_INT_MODULE(10)
I_IM_CHANNEL
G_INT_MODULE(11)
I_IM_CHANNEL
I_DFF_INT_OUTPUT_REG
I_MAC_TOP
I_MAC_PC_TOP
I_MAC_PC_FSM
I_DLC_DECODER_TX
I_DLC_DECODER_RX
I_DLC_DECODER_RX_INST_COMB
I_MAC_PC_CONTROL_COUNTER
I_MAC_PC_REINTEGRATION_COUNTER
I_MAC_PC_RETRANSMITT_COUNTER
I_MAC_PC_ERR_DETECTOR
I_MAC_PC_TX_SHIFT_REG
I_TX_SHIFT_REG
I_MAC_PC_RX_SHIFT_REG
I_RX_SHIFT_RES_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
G_RX_SHIFT_CMD(0)
G_RX_SHIFT_CMD(1)
G_RX_SHIFT_CMD(2)
G_RX_SHIFT_CMD(3)
I_SHIFT_REG_BYTE
G_BYTE_SHIFT_REG(0)
G_FIRST_BYTE
G_BYTE_SHIFT_REG(1)
G_NEXT_BYTES
G_BYTE_SHIFT_REG(2)
G_NEXT_BYTES
G_BYTE_SHIFT_REG(3)
G_NEXT_BYTES
I_MAC_OPERATION_CONTROL
I_MAC_FC_TOP
I_MAC_FC_FSM
I_MAC_FC_ERR_COUNTERS
I_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_MAC_FC_RULES
I_MAC_CRC_TOP
I_MAC_CRC_CALC_15
I_MAC_CRC_CALC_17_RX
I_MAC_CRC_CALC_21_RX
I_MAC_BIT_STUFFING
I_DFF_ENA_REG
I_DFF_FIXED_STUFF_REG
I_DFF_DATA_OUT_REG
I_DFF_HALT_REG
I_MAC_BIT_DESTUFFING
I_DFF_ENA_REG
I_DFF_FIXED_STUFF_REG
I_DFF_DESTUFFED_FLAG_REG
I_DFF_ERR_REG
I_DFF_PREV_VAL_REG
I_DFF_DATA_OUT_VAL_REG
G_BUS_TRAFFIC_CTRS
I_MAC_BUS_TRAFFIC_COUNTERS
I_TX_CTR_REG_RST
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_RX_CTR_REG_RST
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_MAC_TRIGGER_MUX
I_CRC_TRIG_TX_WBS_REG
I_CRC_DATA_RX_WBS_REG
I_BTL_TOP
I_BTL_CFG_CAPTURE
I_BTL_SYNCHRONISATION_CHECKER
I_BTL_SEGMENT_METER_NBT
I_BTL_COUNTERS_NBT
I_BTL_SEGMENT_METER_DBT
I_BTL_COUNTERS_DBT
I_BTL_SEGMENT_END_DETECTOR
G_SEGM_END_REQ_CAPTURE(1)
G_SEGM_END_REQ_CAPTURE(2)
I_BTL_FSM
I_BTL_TRIGGER_GENERATOR
I_BM_TOP
I_CAN_RX_SIG_SYNC
I_BM_TRV_DELAY_MEAS
I_TRV_DELAY_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_BM_DATA_EDGE_DETECTOR
I_SHIFT_REGS_RST_REG
I_RX_SHIFT_RES_REG
I_MUX2_RES_TST
I_TX_TRIGGER_REG
I_BM_SSP_GENERATOR
I_BM_TX_DATA_CACHE
I_BM_BIT_ERR_DETECTOR
I_BM_SAMPLE_MUX
G_TXTB_ASR(0)
G_TXTB_ASR(1)
G_TXTB_ASR(2)
G_TXTB_ASR(3)
I_TX_DELAY_DUT
I_SDV
I_TX_DELAY_TEST_NODE
I_SDV
I_REFERENCE_TEST_AGENT
G_FUNC_COV
I_FUNC_COV_AGENT
I_FUNC_COV_CAN_CORE
I_FUNC_COV_PRESCALER
I_FUNC_COV_PRESCALER_NBT
I_FUNC_COV_PRESCALER_DBT
I_FUNC_COV_BUS_SAMPLING
I_FUNC_COV_RX_BUFFER
I_FUNC_COV_TX_ARBITRATOR
G_EACH_BUF(0)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(1)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(2)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(3)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(4)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(5)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(6)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(7)
I_FUNC_COV_TX_ARBITRATOR_PER_BUF
G_EACH_BUF(0)
G_TXT_BUF_EVEN
I_FUNC_COV_TXT_BUFFER_EVEN
G_EACH_BUF(1)
G_TXT_BUF_ODD
I_FUNC_COV_TXT_BUFFER_ODD
G_EACH_BUF(2)
G_TXT_BUF_EVEN
I_FUNC_COV_TXT_BUFFER_EVEN
G_EACH_BUF(3)
G_TXT_BUF_ODD
I_FUNC_COV_TXT_BUFFER_ODD
G_EACH_BUF(4)
G_TXT_BUF_EVEN
I_FUNC_COV_TXT_BUFFER_EVEN
G_EACH_BUF(5)
G_TXT_BUF_ODD
I_FUNC_COV_TXT_BUFFER_ODD
G_EACH_BUF(6)
G_TXT_BUF_EVEN
I_FUNC_COV_TXT_BUFFER_EVEN
G_EACH_BUF(7)
G_TXT_BUF_ODD
I_FUNC_COV_TXT_BUFFER_ODD
G_CAN_AGENT
I_COMPLIANCE_AGENT
G_WATCHDOG
Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXTB_ASR(2)
File:
/__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd
Current Instance
Statement
Branch
Toggle
Expression
FSM state
Functional
Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXTB_ASR(2)
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
Details:
The limit of printed items was reached (5000). Total 260336 items are not displayed.
Statement
Branch
Toggle
Expression
FSM state
Functional
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