NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_ADDRESS_DECODER_TEST_REGISTERS	100.0 % (16/16)	100.0 % (10/10)	100.0 % (42/42)	100.0 % (2/2)	N.A.	N.A.	100.0 % (70/70)
I_TST_CONTROL_TMAENA_REG	100.0 % (6/6)	100.0 % (6/6)	100.0 % (18/18)	100.0 % (10/10)	N.A.	N.A.	100.0 % (40/40)
I_TST_CONTROL_TWRSTB_REG	100.0 % (5/5)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (8/8)	N.A.	N.A.	100.0 % (33/33)
I_TST_DEST_TST_ADDR_SLICE_1_REG	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
I_TST_DEST_TST_ADDR_SLICE_2_REG	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
I_TST_DEST_TST_MTGT_REG	100.0 % (18/18)	100.0 % (24/24)	100.0 % (36/36)	100.0 % (22/22)	N.A.	N.A.	100.0 % (100/100)
I_TST_WDATA_TST_WDATA_SLICE_1_REG	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
I_TST_WDATA_TST_WDATA_SLICE_2_REG	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
I_TST_WDATA_TST_WDATA_SLICE_3_REG	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
I_TST_WDATA_TST_WDATA_SLICE_4_REG	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.G_TEST_REGISTERS_TRUE.I_TEST_REGISTERS_REG_MAP	100.0 % (15/15)	100.0 % (13/13)	100.0 % (590/590)	100.0 % (16/16)	N.A.	100.0 % (7/7)	100.0 % (641/641)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 56353034
Threshold: 1

Signal assignment statement on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 219307
Threshold: 1

Signal assignment statement on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 56133727
Threshold: 1

Sequential statement on lines 311 to 320:

311:    with address(7 downto 2) select r_data_comb <= 
312:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
...
319:        test_registers_in.tst_rdata_tst_rdata when "000011", 
320:        (others => '0') when others;

Count: 55991709
Threshold: 1

Signal assignment statement on lines 312 to 314:

312:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
313:        test_registers_out_i.tst_control_twrstb & 
314:        test_registers_out_i.tst_control_tmaena when "000000",

Count: 138595
Threshold: 1

Signal assignment statement on lines 315 to 317:

315:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
316:        test_registers_out_i.tst_dest_tst_mtgt & 
317:        test_registers_out_i.tst_dest_tst_addr when "000001",

Count: 398165
Threshold: 1

Signal assignment statement on line 318:

318: test_registers_out_i.tst_wdata_tst_wdata when "000010",
Count: 9689414
Threshold: 1

Signal assignment statement on line 319:

319: test_registers_in.tst_rdata_tst_rdata when "000011",
Count: 149740
Threshold: 1

Signal assignment statement on line 320:

320: (others => '0') when others;
Count: 45615795
Threshold: 1

If statement on lines 327 to 333:

327:        if (rst_n = '0') then 
328:            r_data <= (others => '0'); 
...
332:            end if; 
333:        end if;

Count: 26829265
Threshold: 1

Signal assignment statement on line 328:

328: r_data <= (others => '0');
Count: 15862
Threshold: 1

If statement on lines 330 to 332:

330:            if (cs = '1' and read = '1') then 
331:                r_data <= r_data_comb and read_data_mask_n; 
332:            end if;

Count: 13400284
Threshold: 1

Signal assignment statement on line 331:

331: r_data <= r_data_comb and read_data_mask_n;
Count: 93774
Threshold: 1

Signal assignment statement on lines 340 to 343:

340:      be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &  
341:      be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &  
342:      be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &  
343:      be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ;

Count: 55725271
Threshold: 1

Signal assignment statement on line 345:

345: Test_registers_out <= Test_registers_out_i;
Count: 202431
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');

	Evaluated to	Count	Threshold
Bin	True	219307	1
Bin	False	56133727	1

"case" / "with" / "select" choice on line 314:

314: test_registers_out_i.tst_control_tmaena when "000000",

	Choice of	Count	Threshold
Bin	`"000000"`	138595	1

"case" / "with" / "select" choice on line 317:

317: test_registers_out_i.tst_dest_tst_addr when "000001",

	Choice of	Count	Threshold
Bin	`"000001"`	398165	1

"case" / "with" / "select" choice on line 318:

318: test_registers_out_i.tst_wdata_tst_wdata when "000010",

	Choice of	Count	Threshold
Bin	`"000010"`	9689414	1

"case" / "with" / "select" choice on line 319:

319: test_registers_in.tst_rdata_tst_rdata when "000011",

	Choice of	Count	Threshold
Bin	`"000011"`	149740	1

"case" / "with" / "select" choice on line 320:

320: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	45615795	1

"if" / "when" / "else" condition on line 327:

327: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	15862	1
Bin	False	26813403	1

"if" / "when" / "else" condition on line 329:

329: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	13400284	1
Bin	False	13413119	1

"if" / "when" / "else" condition on line 330:

330: if (cs = '1' and read = '1') then

	Evaluated to	Count	Threshold
Bin	True	93774	1
Bin	False	13306510	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

W_DATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

READ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

LOCK_1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOCK_2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

R_DATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1297	1
Bin	(31)	1	0	2898	1
Bin	(30)	0	1	1321	1
Bin	(30)	1	0	2922	1
Bin	(29)	0	1	1403	1
Bin	(29)	1	0	3004	1
Bin	(28)	0	1	1455	1
Bin	(28)	1	0	3056	1
Bin	(27)	0	1	1464	1
Bin	(27)	1	0	3065	1
Bin	(26)	0	1	1468	1
Bin	(26)	1	0	3069	1
Bin	(25)	0	1	1509	1
Bin	(25)	1	0	3110	1
Bin	(24)	0	1	1375	1
Bin	(24)	1	0	2976	1
Bin	(23)	0	1	1343	1
Bin	(23)	1	0	2944	1
Bin	(22)	0	1	1380	1
Bin	(22)	1	0	2981	1
Bin	(21)	0	1	1458	1
Bin	(21)	1	0	3059	1
Bin	(20)	0	1	1479	1
Bin	(20)	1	0	3080	1
Bin	(19)	0	1	1469	1
Bin	(19)	1	0	3070	1
Bin	(18)	0	1	1470	1
Bin	(18)	1	0	3071	1
Bin	(17)	0	1	1494	1
Bin	(17)	1	0	3095	1
Bin	(16)	0	1	1385	1
Bin	(16)	1	0	2986	1
Bin	(15)	0	1	1342	1
Bin	(15)	1	0	2943	1
Bin	(14)	0	1	1366	1
Bin	(14)	1	0	2967	1
Bin	(13)	0	1	1460	1
Bin	(13)	1	0	3061	1
Bin	(12)	0	1	1505	1
Bin	(12)	1	0	3106	1
Bin	(11)	0	1	1470	1
Bin	(11)	1	0	3071	1
Bin	(10)	0	1	1456	1
Bin	(10)	1	0	3057	1
Bin	(9)	0	1	1540	1
Bin	(9)	1	0	3141	1
Bin	(8)	0	1	1385	1
Bin	(8)	1	0	2986	1
Bin	(7)	0	1	1398	1
Bin	(7)	1	0	2999	1
Bin	(6)	0	1	1410	1
Bin	(6)	1	0	3011	1
Bin	(5)	0	1	1495	1
Bin	(5)	1	0	3096	1
Bin	(4)	0	1	1480	1
Bin	(4)	1	0	3081	1
Bin	(3)	0	1	1476	1
Bin	(3)	1	0	3077	1
Bin	(2)	0	1	1507	1
Bin	(2)	1	0	3108	1
Bin	(1)	0	1	1549	1
Bin	(1)	1	0	3150	1
Bin	(0)	0	1	1433	1
Bin	(0)	1	0	3034	1

Port:

TEST_REGISTERS_OUT

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32324	1
Bin	TST_CONTROL_TWRSTB	1	0	35216	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(11)	0	1	15	1
Bin	TST_DEST_TST_ADDR(11)	1	0	1616	1
Bin	TST_DEST_TST_ADDR(10)	0	1	25	1
Bin	TST_DEST_TST_ADDR(10)	1	0	1626	1
Bin	TST_DEST_TST_ADDR(9)	0	1	45	1
Bin	TST_DEST_TST_ADDR(9)	1	0	1646	1
Bin	TST_DEST_TST_ADDR(8)	0	1	85	1
Bin	TST_DEST_TST_ADDR(8)	1	0	1686	1
Bin	TST_DEST_TST_ADDR(7)	0	1	165	1
Bin	TST_DEST_TST_ADDR(7)	1	0	1766	1
Bin	TST_DEST_TST_ADDR(6)	0	1	355	1
Bin	TST_DEST_TST_ADDR(6)	1	0	1956	1
Bin	TST_DEST_TST_ADDR(5)	0	1	705	1
Bin	TST_DEST_TST_ADDR(5)	1	0	2306	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3615	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5216	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5035	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6636	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10345	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11946	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22457	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24058	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44877	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46478	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	375	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1976	1
Bin	TST_DEST_TST_MTGT(1)	0	1	517	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2118	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1479	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3080	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1508	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3109	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1591	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3192	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1642	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3243	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1637	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3238	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1645	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3246	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1692	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3293	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1558	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3159	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1525	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3126	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1560	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3161	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3255	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3255	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1640	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3241	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1672	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3273	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1556	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3157	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1518	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3119	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3130	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1616	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3217	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1671	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3272	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1638	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3239	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1709	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3310	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1561	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3162	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1564	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3165	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1568	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3169	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1667	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3268	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1663	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3264	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1642	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3243	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1675	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3276	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1719	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3320	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1604	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3205	1

Port:

TEST_REGISTERS_IN

	Element	From	To	Count	Threshold
Bin	TST_RDATA_TST_RDATA(31)	0	1	23972	1
Bin	TST_RDATA_TST_RDATA(31)	1	0	21066	1
Bin	TST_RDATA_TST_RDATA(30)	0	1	15049	1
Bin	TST_RDATA_TST_RDATA(30)	1	0	21162	1
Bin	TST_RDATA_TST_RDATA(29)	0	1	19510	1
Bin	TST_RDATA_TST_RDATA(29)	1	0	16604	1
Bin	TST_RDATA_TST_RDATA(28)	0	1	19954	1
Bin	TST_RDATA_TST_RDATA(28)	1	0	26067	1
Bin	TST_RDATA_TST_RDATA(27)	0	1	19841	1
Bin	TST_RDATA_TST_RDATA(27)	1	0	16935	1
Bin	TST_RDATA_TST_RDATA(26)	0	1	19833	1
Bin	TST_RDATA_TST_RDATA(26)	1	0	25946	1
Bin	TST_RDATA_TST_RDATA(25)	0	1	24479	1
Bin	TST_RDATA_TST_RDATA(25)	1	0	21573	1
Bin	TST_RDATA_TST_RDATA(24)	0	1	15192	1
Bin	TST_RDATA_TST_RDATA(24)	1	0	21305	1
Bin	TST_RDATA_TST_RDATA(23)	0	1	24304	1
Bin	TST_RDATA_TST_RDATA(23)	1	0	21398	1
Bin	TST_RDATA_TST_RDATA(22)	0	1	15397	1
Bin	TST_RDATA_TST_RDATA(22)	1	0	21510	1
Bin	TST_RDATA_TST_RDATA(21)	0	1	19868	1
Bin	TST_RDATA_TST_RDATA(21)	1	0	16962	1
Bin	TST_RDATA_TST_RDATA(20)	0	1	19941	1
Bin	TST_RDATA_TST_RDATA(20)	1	0	26054	1
Bin	TST_RDATA_TST_RDATA(19)	0	1	19868	1
Bin	TST_RDATA_TST_RDATA(19)	1	0	16962	1
Bin	TST_RDATA_TST_RDATA(18)	0	1	19858	1
Bin	TST_RDATA_TST_RDATA(18)	1	0	25971	1
Bin	TST_RDATA_TST_RDATA(17)	0	1	24354	1
Bin	TST_RDATA_TST_RDATA(17)	1	0	21448	1
Bin	TST_RDATA_TST_RDATA(16)	0	1	15073	1
Bin	TST_RDATA_TST_RDATA(16)	1	0	21186	1
Bin	TST_RDATA_TST_RDATA(15)	0	1	24182	1
Bin	TST_RDATA_TST_RDATA(15)	1	0	21276	1
Bin	TST_RDATA_TST_RDATA(14)	0	1	15247	1
Bin	TST_RDATA_TST_RDATA(14)	1	0	21360	1
Bin	TST_RDATA_TST_RDATA(13)	0	1	19700	1
Bin	TST_RDATA_TST_RDATA(13)	1	0	16794	1
Bin	TST_RDATA_TST_RDATA(12)	0	1	19883	1
Bin	TST_RDATA_TST_RDATA(12)	1	0	25996	1
Bin	TST_RDATA_TST_RDATA(11)	0	1	19769	1
Bin	TST_RDATA_TST_RDATA(11)	1	0	16863	1
Bin	TST_RDATA_TST_RDATA(10)	0	1	19708	1
Bin	TST_RDATA_TST_RDATA(10)	1	0	25821	1
Bin	TST_RDATA_TST_RDATA(9)	0	1	24435	1
Bin	TST_RDATA_TST_RDATA(9)	1	0	21529	1
Bin	TST_RDATA_TST_RDATA(8)	0	1	15098	1
Bin	TST_RDATA_TST_RDATA(8)	1	0	21211	1
Bin	TST_RDATA_TST_RDATA(7)	0	1	24352	1
Bin	TST_RDATA_TST_RDATA(7)	1	0	21446	1
Bin	TST_RDATA_TST_RDATA(6)	0	1	15389	1
Bin	TST_RDATA_TST_RDATA(6)	1	0	21502	1
Bin	TST_RDATA_TST_RDATA(5)	0	1	19757	1
Bin	TST_RDATA_TST_RDATA(5)	1	0	16851	1
Bin	TST_RDATA_TST_RDATA(4)	0	1	19852	1
Bin	TST_RDATA_TST_RDATA(4)	1	0	25965	1
Bin	TST_RDATA_TST_RDATA(3)	0	1	19797	1
Bin	TST_RDATA_TST_RDATA(3)	1	0	16891	1
Bin	TST_RDATA_TST_RDATA(2)	0	1	19796	1
Bin	TST_RDATA_TST_RDATA(2)	1	0	25909	1
Bin	TST_RDATA_TST_RDATA(1)	0	1	24433	1
Bin	TST_RDATA_TST_RDATA(1)	1	0	21527	1
Bin	TST_RDATA_TST_RDATA(0)	0	1	15201	1
Bin	TST_RDATA_TST_RDATA(0)	1	0	21314	1

Signal:

REG_SEL

	Element	From	To	Count	Threshold
Bin	(3)	0	1	93744	1
Bin	(3)	1	0	534019	1
Bin	(2)	0	1	41364	1
Bin	(2)	1	0	586399	1
Bin	(1)	0	1	135108	1
Bin	(1)	1	0	492655	1
Bin	(0)	0	1	42865	1
Bin	(0)	1	0	584898	1

Signal:

R_DATA_COMB

	Element	From	To	Count	Threshold
Bin	(31)	0	1	45711	1
Bin	(31)	1	0	47312	1
Bin	(30)	0	1	72270	1
Bin	(30)	1	0	73871	1
Bin	(29)	0	1	75086	1
Bin	(29)	1	0	76687	1
Bin	(28)	0	1	83474	1
Bin	(28)	1	0	85075	1
Bin	(27)	0	1	75105	1
Bin	(27)	1	0	76706	1
Bin	(26)	0	1	83080	1
Bin	(26)	1	0	84681	1
Bin	(25)	0	1	61960	1
Bin	(25)	1	0	63561	1
Bin	(24)	0	1	57172	1
Bin	(24)	1	0	58773	1
Bin	(23)	0	1	55464	1
Bin	(23)	1	0	57065	1
Bin	(22)	0	1	67069	1
Bin	(22)	1	0	68670	1
Bin	(21)	0	1	55862	1
Bin	(21)	1	0	57463	1
Bin	(20)	0	1	88605	1
Bin	(20)	1	0	90206	1
Bin	(19)	0	1	102084	1
Bin	(19)	1	0	103685	1
Bin	(18)	0	1	121609	1
Bin	(18)	1	0	123210	1
Bin	(17)	0	1	109758	1
Bin	(17)	1	0	111359	1
Bin	(16)	0	1	134233	1
Bin	(16)	1	0	135834	1
Bin	(15)	0	1	76757	1
Bin	(15)	1	0	78358	1
Bin	(14)	0	1	88903	1
Bin	(14)	1	0	90504	1
Bin	(13)	0	1	49168	1
Bin	(13)	1	0	50769	1
Bin	(12)	0	1	85268	1
Bin	(12)	1	0	86869	1
Bin	(11)	0	1	105229	1
Bin	(11)	1	0	106830	1
Bin	(10)	0	1	115940	1
Bin	(10)	1	0	117541	1
Bin	(9)	0	1	102689	1
Bin	(9)	1	0	104290	1
Bin	(8)	0	1	104062	1
Bin	(8)	1	0	105663	1
Bin	(7)	0	1	95076	1
Bin	(7)	1	0	96677	1
Bin	(6)	0	1	86597	1
Bin	(6)	1	0	88198	1
Bin	(5)	0	1	125519	1
Bin	(5)	1	0	127120	1
Bin	(4)	0	1	135715	1
Bin	(4)	1	0	137316	1
Bin	(3)	0	1	118458	1
Bin	(3)	1	0	120059	1
Bin	(2)	0	1	142677	1
Bin	(2)	1	0	144278	1
Bin	(1)	0	1	239371	1
Bin	(1)	1	0	240972	1
Bin	(0)	0	1	238340	1
Bin	(0)	1	0	239941	1

Signal:

READ_DATA_MASK_N

	Element	From	To	Count	Threshold
Bin	(31)	0	1	27823416	1
Bin	(31)	1	0	38419	1
Bin	(30)	0	1	27823416	1
Bin	(30)	1	0	38419	1
Bin	(29)	0	1	27823416	1
Bin	(29)	1	0	38419	1
Bin	(28)	0	1	27823416	1
Bin	(28)	1	0	38419	1
Bin	(27)	0	1	27823416	1
Bin	(27)	1	0	38419	1
Bin	(26)	0	1	27823416	1
Bin	(26)	1	0	38419	1
Bin	(25)	0	1	27823416	1
Bin	(25)	1	0	38419	1
Bin	(24)	0	1	27823416	1
Bin	(24)	1	0	38419	1
Bin	(23)	0	1	27823798	1
Bin	(23)	1	0	38037	1
Bin	(22)	0	1	27823798	1
Bin	(22)	1	0	38037	1
Bin	(21)	0	1	27823798	1
Bin	(21)	1	0	38037	1
Bin	(20)	0	1	27823798	1
Bin	(20)	1	0	38037	1
Bin	(19)	0	1	27823798	1
Bin	(19)	1	0	38037	1
Bin	(18)	0	1	27823798	1
Bin	(18)	1	0	38037	1
Bin	(17)	0	1	27823798	1
Bin	(17)	1	0	38037	1
Bin	(16)	0	1	27823798	1
Bin	(16)	1	0	38037	1
Bin	(15)	0	1	27725615	1
Bin	(15)	1	0	136220	1
Bin	(14)	0	1	27725615	1
Bin	(14)	1	0	136220	1
Bin	(13)	0	1	27725615	1
Bin	(13)	1	0	136220	1
Bin	(12)	0	1	27725615	1
Bin	(12)	1	0	136220	1
Bin	(11)	0	1	27725615	1
Bin	(11)	1	0	136220	1
Bin	(10)	0	1	27725615	1
Bin	(10)	1	0	136220	1
Bin	(9)	0	1	27725615	1
Bin	(9)	1	0	136220	1
Bin	(8)	0	1	27725615	1
Bin	(8)	1	0	136220	1
Bin	(7)	0	1	27726843	1
Bin	(7)	1	0	134992	1
Bin	(6)	0	1	27726843	1
Bin	(6)	1	0	134992	1
Bin	(5)	0	1	27726843	1
Bin	(5)	1	0	134992	1
Bin	(4)	0	1	27726843	1
Bin	(4)	1	0	134992	1
Bin	(3)	0	1	27726843	1
Bin	(3)	1	0	134992	1
Bin	(2)	0	1	27726843	1
Bin	(2)	1	0	134992	1
Bin	(1)	0	1	27726843	1
Bin	(1)	1	0	134992	1
Bin	(0)	0	1	27726843	1
Bin	(0)	1	0	134992	1

Signal:

TEST_REGISTERS_OUT_I

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32324	1
Bin	TST_CONTROL_TWRSTB	1	0	35216	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	50972	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	50972	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	50972	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	50972	1
Bin	TST_DEST_TST_ADDR(11)	0	1	2565	1
Bin	TST_DEST_TST_ADDR(11)	1	0	53277	1
Bin	TST_DEST_TST_ADDR(10)	0	1	5125	1
Bin	TST_DEST_TST_ADDR(10)	1	0	55837	1
Bin	TST_DEST_TST_ADDR(9)	0	1	10245	1
Bin	TST_DEST_TST_ADDR(9)	1	0	60957	1
Bin	TST_DEST_TST_ADDR(8)	0	1	20485	1
Bin	TST_DEST_TST_ADDR(8)	1	0	71197	1
Bin	TST_DEST_TST_ADDR(7)	0	1	165	1
Bin	TST_DEST_TST_ADDR(7)	1	0	1766	1
Bin	TST_DEST_TST_ADDR(6)	0	1	355	1
Bin	TST_DEST_TST_ADDR(6)	1	0	1956	1
Bin	TST_DEST_TST_ADDR(5)	0	1	705	1
Bin	TST_DEST_TST_ADDR(5)	1	0	2306	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3615	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5216	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5035	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6636	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10345	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11946	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22457	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24058	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44877	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46478	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	375	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1976	1
Bin	TST_DEST_TST_MTGT(1)	0	1	517	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2118	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1491	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3148	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1510	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3190	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1602	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3285	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1655	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3367	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1647	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3383	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1650	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3368	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1705	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3420	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1562	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3279	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1538	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3269	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1566	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3291	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1650	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3385	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1668	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3388	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1671	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3396	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1646	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3354	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1684	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3381	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1558	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3242	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3198	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1532	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3224	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1626	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3300	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1683	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3363	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1652	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3326	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1640	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3328	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1721	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3426	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1562	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3264	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1577	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3227	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1570	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3235	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1679	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3325	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1673	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3324	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3296	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1679	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3331	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1730	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3385	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1606	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3257	1

Signal:

WRITE_EN

	Element	From	To	Count	Threshold
Bin	(3)	0	1	219307	1
Bin	(3)	1	0	220908	1
Bin	(2)	0	1	219307	1
Bin	(2)	1	0	220908	1
Bin	(1)	0	1	219307	1
Bin	(1)	1	0	220908	1
Bin	(0)	0	1	219307	1
Bin	(0)	1	0	220908	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 116:

 write = '1' and cs = '1' 
 <---LHS--->     <-RHS-->

	LHS	RHS	Count	Threshold
Bin	False	True	406855	1
Bin	True	False	1097081	1
Bin	True	True	219307	1

"=" expression on line 116:

write = '1'

	Evaluated to	Count	Threshold
Bin	False	55036646	1
Bin	True	1316388	1

"=" expression on line 116:

cs = '1'

	Evaluated to	Count	Threshold
Bin	False	55726872	1
Bin	True	626162	1

"=" expression on line 327:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	26813403	1
Bin	True	15862	1

"and" expression on line 330:

 cs = '1' and read = '1' 
 <-LHS-->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	2650507	1
Bin	True	False	219307	1
Bin	True	True	93774	1

"=" expression on line 330:

cs = '1'

	Evaluated to	Count	Threshold
Bin	False	13087203	1
Bin	True	313081	1

"=" expression on line 330:

read = '1'

	Evaluated to	Count	Threshold
Bin	False	10656003	1
Bin	True	2744281	1

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 352 to 353:

352:    -- psl tst_control_write_access_cov : cover 
353:    -- {((cs='1') and (write='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 42855
Threshold: 1

PSL cover point on lines 355 to 356:

355:    -- psl tst_control_read_access_cov : cover 
356:    -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point on lines 358 to 359:

358:    -- psl tst_dest_write_access_cov : cover 
359:    -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 135098
Threshold: 1

PSL cover point on lines 361 to 362:

361:    -- psl tst_dest_read_access_cov : cover 
362:    -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point on lines 364 to 365:

364:    -- psl tst_wdata_write_access_cov : cover 
365:    -- {((cs='1') and (write='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 41354
Threshold: 1

PSL cover point on lines 367 to 368:

367:    -- psl tst_wdata_read_access_cov : cover 
368:    -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point on lines 370 to 371:

370:    -- psl tst_rdata_read_access_cov : cover 
371:    -- {((cs='1') and (read='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 93744
Threshold: 1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.G_TEST_REGISTERS_TRUE.I_TEST_REGISTERS_REG_MAP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/mr_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on line 116:

Signal assignment statement on line 116:

Signal assignment statement on line 116:

Sequential statement on lines 311 to 320:

Signal assignment statement on lines 312 to 314:

Signal assignment statement on lines 315 to 317:

Signal assignment statement on line 318:

Signal assignment statement on line 319:

Signal assignment statement on line 320:

If statement on lines 327 to 333:

Signal assignment statement on line 328:

If statement on lines 330 to 332:

Signal assignment statement on line 331:

Signal assignment statement on lines 340 to 343:

Signal assignment statement on line 345:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 116:

"case" / "with" / "select" choice on line 314:

"case" / "with" / "select" choice on line 317:

"case" / "with" / "select" choice on line 318:

"case" / "with" / "select" choice on line 319:

"case" / "with" / "select" choice on line 320:

"if" / "when" / "else" condition on line 327:

"if" / "when" / "else" condition on line 329:

"if" / "when" / "else" condition on line 330:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 116:

"=" expression on line 116:

"=" expression on line 116:

"=" expression on line 327:

"and" expression on line 330:

"=" expression on line 330:

"=" expression on line 330:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 352 to 353:

PSL cover point on lines 355 to 356:

PSL cover point on lines 358 to 359:

PSL cover point on lines 361 to 362:

PSL cover point on lines 364 to 365:

PSL cover point on lines 367 to 368:

PSL cover point on lines 370 to 371: