NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_fc_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP.I_MAC_FC_RULES	100.0 % (18/18)	100.0 % (16/16)	100.0 % (34/34)	98.4 % (65/66)	N.A.	N.A.	99.2 % (133/134)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP.I_MAC_FC_RULES

100.0 % (18/18)

100.0 % (16/16)

100.0 % (34/34)

98.4 % (65/66)

N.A.

99.2 % (133/134)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 164 to 166:

164:    inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1') 
165:                     else 
166:                 '0';

Count: 358456
Threshold: 1

Signal assignment statement on line 164:

164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')
Count: 53360
Threshold: 1

Signal assignment statement on line 166:

166: '0';
Count: 305096
Threshold: 1

If statement on lines 178 to 184:

178:    inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else 
179:                   '1' when (act_err_ovr_flag = '1' and err_detected = '1') else 
...
183:                   '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else 
184:                   '0';

Count: 445763
Threshold: 1

Signal assignment statement on line 178:

178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else
Count: 8006
Threshold: 1

Signal assignment statement on line 179:

179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else
Count: 1519
Threshold: 1

Signal assignment statement on line 180:

180: '1' when (is_transmitter = '1' and
Count: 71389
Threshold: 1

Signal assignment statement on line 183:

183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else
Count: 398
Threshold: 1

Signal assignment statement on line 184:

184: '0';
Count: 364451
Threshold: 1

If statement on lines 189 to 191:

189:    dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1') 
190:                   else 
191:               '0';

Count: 56937
Threshold: 1

Signal assignment statement on line 189:

189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1')
Count: 26067
Threshold: 1

Signal assignment statement on line 191:

191: '0';
Count: 30870
Threshold: 1

If statement on lines 197 to 199:

197:    inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED) 
198:                   else 
199:               '0';

Count: 111625
Threshold: 1

Signal assignment statement on line 197:

197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED)
Count: 45943
Threshold: 1

Signal assignment statement on line 199:

199: '0';
Count: 65682
Threshold: 1

If statement on lines 200 to 202:

200:    inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED) 
201:                     else 
202:                 '0';

Count: 167463
Threshold: 1

Signal assignment statement on line 200:

200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)
Count: 81279
Threshold: 1

Signal assignment statement on line 202:

202: '0';
Count: 86184
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 164:

164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')

	Evaluated to	Count	Threshold
Bin	True	53360	1
Bin	False	305096	1

"if" / "when" / "else" condition on line 178:

178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else

	Evaluated to	Count	Threshold
Bin	True	8006	1
Bin	False	437757	1

"if" / "when" / "else" condition on line 179:

179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else

	Evaluated to	Count	Threshold
Bin	True	1519	1
Bin	False	436238	1

"if" / "when" / "else" condition on lines 180 to 182:

180:                   '1' when (is_transmitter = '1' and 
181:                             err_detected = '1' and 
182:                             err_ctrs_unchanged = '0') else

	Evaluated to	Count	Threshold
Bin	True	71389	1
Bin	False	364849	1

"if" / "when" / "else" condition on line 183:

183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else

	Evaluated to	Count	Threshold
Bin	True	398	1
Bin	False	364451	1

"if" / "when" / "else" condition on line 189:

189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	26067	1
Bin	False	30870	1

"if" / "when" / "else" condition on line 197:

197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED)

	Evaluated to	Count	Threshold
Bin	True	45943	1
Bin	False	65682	1

"if" / "when" / "else" condition on line 200:

200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)

	Evaluated to	Count	Threshold
Bin	True	81279	1
Bin	False	86184	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TRANSMITTER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_RECEIVER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DETECTED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_CTRS_UNCHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRIMARY_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ACT_ERR_OVR_FLAG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DELIM_LATE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DECREMENT_REC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_AFTER_ACK_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

INC_ONE

	From	To	Count	Threshold
Bin	0	1	45943	1
Bin	1	0	47544	1

Port:

INC_EIGHT

	From	To	Count	Threshold
Bin	0	1	81279	1
Bin	1	0	82880	1

Port:

DEC_ONE

	From	To	Count	Threshold
Bin	0	1	26067	1
Bin	1	0	27668	1

Signal:

INC_ONE_I

	From	To	Count	Threshold
Bin	0	1	53360	1
Bin	1	0	54961	1

Signal:

INC_EIGHT_I

	From	To	Count	Threshold
Bin	0	1	81279	1
Bin	1	0	82880	1

Uncovered expressions:

"and" expression on line 200:

 inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED 
 <------LHS------>     <----------RHS----------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	True	False	0	1

Excluded expressions:

Covered expressions:

"and" expression on line 164:

 err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1' 
 <--------------------LHS-------------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	100837	1
Bin	True	False	71389	1
Bin	True	True	53360	1

"and" expression on line 164:

 err_detected = '1' and act_err_ovr_flag = '0' 
 <------LHS------->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	209368	1
Bin	True	False	1519	1
Bin	True	True	124749	1

"=" expression on line 164:

err_detected = '1'

	Evaluated to	Count	Threshold
Bin	False	232188	1
Bin	True	126268	1

"=" expression on line 164:

act_err_ovr_flag = '0'

	Evaluated to	Count	Threshold
Bin	False	24339	1
Bin	True	334117	1

"=" expression on line 164:

is_receiver = '1'

	Evaluated to	Count	Threshold
Bin	False	204259	1
Bin	True	154197	1

"and" expression on line 178:

 primary_err = '1' and is_receiver = '1' 
 <------LHS------>     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	162363	1
Bin	True	False	14743	1
Bin	True	True	8006	1

"=" expression on line 178:

primary_err = '1'

	Evaluated to	Count	Threshold
Bin	False	423014	1
Bin	True	22749	1

"=" expression on line 178:

is_receiver = '1'

	Evaluated to	Count	Threshold
Bin	False	275394	1
Bin	True	170369	1

"and" expression on line 179:

 act_err_ovr_flag = '1' and err_detected = '1' 
 <--------LHS--------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	125238	1
Bin	True	False	21219	1
Bin	True	True	1519	1

"=" expression on line 179:

act_err_ovr_flag = '1'

	Evaluated to	Count	Threshold
Bin	False	415019	1
Bin	True	22738	1

"=" expression on line 179:

err_detected = '1'

	Evaluated to	Count	Threshold
Bin	False	311000	1
Bin	True	126757	1

"and" expression on lines 180 to 182:

 is_transmitter = '1' and err_detected = '1' and err_ctrs_unchanged = '0' 
 <-------------------LHS------------------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	361959	1
Bin	True	False	489	1
Bin	True	True	71389	1

"and" expression on lines 180 to 181:

 is_transmitter = '1' and err_detected = '1' 
 <-------LHS-------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	53360	1
Bin	True	False	147209	1
Bin	True	True	71878	1

"=" expression on line 180:

is_transmitter = '1'

	Evaluated to	Count	Threshold
Bin	False	217151	1
Bin	True	219087	1

"=" expression on line 181:

err_detected = '1'

	Evaluated to	Count	Threshold
Bin	False	311000	1
Bin	True	125238	1

"=" expression on line 182:

err_ctrs_unchanged = '0'

	Evaluated to	Count	Threshold
Bin	False	2890	1
Bin	True	433348	1

"or" expression on line 183:

 err_delim_late = '1' or bit_err_after_ack_err = '1' 
 <-------LHS-------->    <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	364451	1
Bin	False	True	8	1
Bin	True	False	390	1

"=" expression on line 183:

err_delim_late = '1'

	Evaluated to	Count	Threshold
Bin	False	364459	1
Bin	True	390	1

"=" expression on line 183:

bit_err_after_ack_err = '1'

	Evaluated to	Count	Threshold
Bin	False	364841	1
Bin	True	8	1

"or" expression on line 189:

 decrement_rec = '1' or tran_valid = '1' 
 <-------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	30870	1
Bin	False	True	11115	1
Bin	True	False	14952	1

"=" expression on line 189:

decrement_rec = '1'

	Evaluated to	Count	Threshold
Bin	False	41985	1
Bin	True	14952	1

"=" expression on line 189:

tran_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	45822	1
Bin	True	11115	1

"and" expression on line 197:

 inc_one_i = '1' and mr_mode_rom = ROM_DISABLED 
 <-----LHS----->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	47595	1
Bin	True	False	7417	1
Bin	True	True	45943	1

"=" expression on line 197:

inc_one_i = '1'

	Evaluated to	Count	Threshold
Bin	False	58265	1
Bin	True	53360	1

"=" expression on line 197:

mr_mode_rom = ROM_DISABLED

	Evaluated to	Count	Threshold
Bin	False	18087	1
Bin	True	93538	1

"and" expression on line 200:

 inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED 
 <------LHS------>     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	82931	1
Bin	True	True	81279	1

"=" expression on line 200:

inc_eight_i = '1'

	Evaluated to	Count	Threshold
Bin	False	86184	1
Bin	True	81279	1

"=" expression on line 200:

mr_mode_rom = ROM_DISABLED

	Evaluated to	Count	Threshold
Bin	False	3253	1
Bin	True	164210	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP.I_MAC_FC_RULES

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_fc_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 164 to 166:

Signal assignment statement on line 164:

Signal assignment statement on line 166:

If statement on lines 178 to 184:

Signal assignment statement on line 178:

Signal assignment statement on line 179:

Signal assignment statement on line 180:

Signal assignment statement on line 183:

Signal assignment statement on line 184:

If statement on lines 189 to 191:

Signal assignment statement on line 189:

Signal assignment statement on line 191:

If statement on lines 197 to 199:

Signal assignment statement on line 197:

Signal assignment statement on line 199:

If statement on lines 200 to 202:

Signal assignment statement on line 200:

Signal assignment statement on line 202:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 164:

"if" / "when" / "else" condition on line 178:

"if" / "when" / "else" condition on line 179:

"if" / "when" / "else" condition on lines 180 to 182:

"if" / "when" / "else" condition on line 183:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on line 197:

"if" / "when" / "else" condition on line 200:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Uncovered expressions:

"and" expression on line 200:

Excluded expressions:

Covered expressions:

"and" expression on line 164:

"and" expression on line 164:

"=" expression on line 164:

"=" expression on line 164:

"=" expression on line 164:

"and" expression on line 178:

"=" expression on line 178:

"=" expression on line 178:

"and" expression on line 179:

"=" expression on line 179:

"=" expression on line 179:

"and" expression on lines 180 to 182:

"and" expression on lines 180 to 181:

"=" expression on line 180:

"=" expression on line 181:

"=" expression on line 182:

"or" expression on line 183:

"=" expression on line 183:

"=" expression on line 183: