NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_MAC_CRC_CALC_15	100.0 % (15/15)	100.0 % (14/14)	100.0 % (108/108)	100.0 % (21/21)	N.A.	N.A.	100.0 % (158/158)
I_MAC_CRC_CALC_17_RX	100.0 % (15/15)	100.0 % (14/14)	100.0 % (120/120)	100.0 % (21/21)	N.A.	N.A.	100.0 % (170/170)
I_MAC_CRC_CALC_21_RX	100.0 % (15/15)	100.0 % (14/14)	100.0 % (144/144)	100.0 % (21/21)	N.A.	N.A.	100.0 % (194/194)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_MAC_CRC_CALC_15

100.0 % (15/15)

100.0 % (14/14)

100.0 % (108/108)

100.0 % (21/21)

N.A.

100.0 % (158/158)

I_MAC_CRC_CALC_17_RX

100.0 % (15/15)

100.0 % (14/14)

100.0 % (120/120)

100.0 % (21/21)

N.A.

100.0 % (170/170)

I_MAC_CRC_CALC_21_RX

100.0 % (15/15)

100.0 % (14/14)

100.0 % (144/144)

100.0 % (21/21)

N.A.

100.0 % (194/194)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP	100.0 % (26/26)	100.0 % (20/20)	100.0 % (152/152)	100.0 % (30/30)	N.A.	N.A.	100.0 % (228/228)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP

100.0 % (26/26)

100.0 % (20/20)

100.0 % (152/152)

100.0 % (30/30)

N.A.

100.0 % (228/228)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 210 to 212:

210:    init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD) 
211:                            else 
212:                        '0';

Count: 3462
Threshold: 1

Signal assignment statement on line 210:

210: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)
Count: 1731
Threshold: 1

Signal assignment statement on line 212:

212: '0';
Count: 1731
Threshold: 1

If statement on lines 214 to 216:

214:    init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD) 
215:                            else 
216:                        '0';

Count: 3462
Threshold: 1

Signal assignment statement on line 214:

214: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)
Count: 1731
Threshold: 1

Signal assignment statement on line 216:

216: '0';
Count: 1731
Threshold: 1

If statement on lines 222 to 224:

222:    crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1') 
223:                                     else 
224:                         data_tx_wbs;

Count: 4259102
Threshold: 1

Signal assignment statement on line 222:

222: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')
Count: 2173291
Threshold: 1

Signal assignment statement on line 224:

224: data_tx_wbs;
Count: 2085811
Threshold: 1

If statement on lines 226 to 228:

226:    crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1') 
227:                                     else 
228:                         trig_tx_wbs;

Count: 45685252
Threshold: 1

Signal assignment statement on line 226:

226: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')
Count: 33450208
Threshold: 1

Signal assignment statement on line 228:

228: trig_tx_wbs;
Count: 12235044
Threshold: 1

If statement on lines 234 to 236:

234:    crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1') 
235:                                  else 
236:                      data_tx_nbs;

Count: 4265353
Threshold: 1

Signal assignment statement on line 234:

234: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')
Count: 2170931
Threshold: 1

Signal assignment statement on line 236:

236: data_tx_nbs;
Count: 2094422
Threshold: 1

If statement on lines 238 to 240:

238:    crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1') 
239:                                  else 
240:                      trig_tx_nbs;

Count: 43728480
Threshold: 1

Signal assignment statement on line 238:

238: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')
Count: 32038961
Threshold: 1

Signal assignment statement on line 240:

240: trig_tx_nbs;
Count: 11689519
Threshold: 1

If statement on lines 249 to 253:

249:    crc_ena_15   <= '1' when (crc_enable = '1') 
250:                        else 
251:                    '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT) 
252:                        else 
253:                    '0';

Count: 3107016
Threshold: 1

Signal assignment statement on line 249:

249: crc_ena_15 <= '1' when (crc_enable = '1')
Count: 2465348
Threshold: 1

Signal assignment statement on line 251:

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)
Count: 744
Threshold: 1

Signal assignment statement on line 253:

253: '0';
Count: 640924
Threshold: 1

If statement on lines 255 to 259:

255:    crc_ena_17_21  <= '1' when (crc_enable = '1') 
256:                          else 
257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT) 
258:                          else 
259:                      '0';

Count: 3134492
Threshold: 1

Signal assignment statement on line 255:

255: crc_ena_17_21 <= '1' when (crc_enable = '1')
Count: 2448419
Threshold: 1

Signal assignment statement on line 257:

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

Count: 36790
Threshold: 1

Signal assignment statement on line 259:

259: '0';
Count: 649283
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 210:

210: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	True	1731	1
Bin	False	1731	1

"if" / "when" / "else" condition on line 214:

214: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)

	Evaluated to	Count	Threshold
Bin	True	1731	1
Bin	False	1731	1

"if" / "when" / "else" condition on line 222:

222: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	2173291	1
Bin	False	2085811	1

"if" / "when" / "else" condition on line 226:

226: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	33450208	1
Bin	False	12235044	1

"if" / "when" / "else" condition on line 234:

234: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	2170931	1
Bin	False	2094422	1

"if" / "when" / "else" condition on line 238:

238: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')

	Evaluated to	Count	Threshold
Bin	True	32038961	1
Bin	False	11689519	1

"if" / "when" / "else" condition on line 249:

249: crc_ena_15 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	2465348	1
Bin	False	641668	1

"if" / "when" / "else" condition on line 251:

251: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	True	744	1
Bin	False	640924	1

"if" / "when" / "else" condition on line 255:

255: crc_ena_17_21 <= '1' when (crc_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	2448419	1
Bin	False	686073	1

"if" / "when" / "else" condition on line 257:

257:                      '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)

	Evaluated to	Count	Threshold
Bin	True	36790	1
Bin	False	649283	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_NISOFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_TX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_RX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_RX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_TX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_TX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_RX_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG_RX_NBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_SPEC_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_CALC_FROM_RX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CRC_15

	Element	From	To	Count	Threshold
Bin	(14)	0	1	1464603	1
Bin	(14)	1	0	1466201	1
Bin	(13)	0	1	1414055	1
Bin	(13)	1	0	1415654	1
Bin	(12)	0	1	1426975	1
Bin	(12)	1	0	1428575	1
Bin	(11)	0	1	1440706	1
Bin	(11)	1	0	1442303	1
Bin	(10)	0	1	1457147	1
Bin	(10)	1	0	1458746	1
Bin	(9)	0	1	1452500	1
Bin	(9)	1	0	1454099	1
Bin	(8)	0	1	1468253	1
Bin	(8)	1	0	1469850	1
Bin	(7)	0	1	1492277	1
Bin	(7)	1	0	1493877	1
Bin	(6)	0	1	1438993	1
Bin	(6)	1	0	1440591	1
Bin	(5)	0	1	1451287	1
Bin	(5)	1	0	1452883	1
Bin	(4)	0	1	1465089	1
Bin	(4)	1	0	1466687	1
Bin	(3)	0	1	1462665	1
Bin	(3)	1	0	1464264	1
Bin	(2)	0	1	1454912	1
Bin	(2)	1	0	1456508	1
Bin	(1)	0	1	1468642	1
Bin	(1)	1	0	1470239	1
Bin	(0)	0	1	1481303	1
Bin	(0)	1	0	1482900	1

Port:

CRC_17

	Element	From	To	Count	Threshold
Bin	(16)	0	1	1741970	1
Bin	(16)	1	0	1743562	1
Bin	(15)	0	1	1764187	1
Bin	(15)	1	0	1765784	1
Bin	(14)	0	1	1780164	1
Bin	(14)	1	0	1781764	1
Bin	(13)	0	1	1765799	1
Bin	(13)	1	0	1767396	1
Bin	(12)	0	1	1705977	1
Bin	(12)	1	0	1707575	1
Bin	(11)	0	1	1721037	1
Bin	(11)	1	0	1722635	1
Bin	(10)	0	1	1670589	1
Bin	(10)	1	0	1672188	1
Bin	(9)	0	1	1684025	1
Bin	(9)	1	0	1685624	1
Bin	(8)	0	1	1696838	1
Bin	(8)	1	0	1698438	1
Bin	(7)	0	1	1711115	1
Bin	(7)	1	0	1712714	1
Bin	(6)	0	1	1725313	1
Bin	(6)	1	0	1726913	1
Bin	(5)	0	1	1725755	1
Bin	(5)	1	0	1727353	1
Bin	(4)	0	1	1738877	1
Bin	(4)	1	0	1740474	1
Bin	(3)	0	1	1759160	1
Bin	(3)	1	0	1760759	1
Bin	(2)	0	1	1733187	1
Bin	(2)	1	0	1734787	1
Bin	(1)	0	1	1749134	1
Bin	(1)	1	0	1750732	1
Bin	(0)	0	1	1770346	1
Bin	(0)	1	0	1771943	1

Port:

CRC_21

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1750548	1
Bin	(20)	1	0	1752139	1
Bin	(19)	0	1	1703965	1
Bin	(19)	1	0	1705564	1
Bin	(18)	0	1	1719889	1
Bin	(18)	1	0	1721489	1
Bin	(17)	0	1	1733300	1
Bin	(17)	1	0	1734899	1
Bin	(16)	0	1	1746057	1
Bin	(16)	1	0	1747657	1
Bin	(15)	0	1	1761040	1
Bin	(15)	1	0	1762637	1
Bin	(14)	0	1	1773792	1
Bin	(14)	1	0	1775388	1
Bin	(13)	0	1	1788103	1
Bin	(13)	1	0	1789698	1
Bin	(12)	0	1	1735619	1
Bin	(12)	1	0	1737217	1
Bin	(11)	0	1	1750649	1
Bin	(11)	1	0	1752247	1
Bin	(10)	0	1	1735803	1
Bin	(10)	1	0	1737400	1
Bin	(9)	0	1	1750856	1
Bin	(9)	1	0	1752454	1
Bin	(8)	0	1	1764927	1
Bin	(8)	1	0	1766523	1
Bin	(7)	0	1	1779762	1
Bin	(7)	1	0	1781362	1
Bin	(6)	0	1	1715511	1
Bin	(6)	1	0	1717109	1
Bin	(5)	0	1	1729494	1
Bin	(5)	1	0	1731092	1
Bin	(4)	0	1	1743073	1
Bin	(4)	1	0	1744671	1
Bin	(3)	0	1	1769789	1
Bin	(3)	1	0	1771385	1
Bin	(2)	0	1	1767065	1
Bin	(2)	1	0	1768664	1
Bin	(1)	0	1	1779026	1
Bin	(1)	1	0	1780626	1
Bin	(0)	0	1	1792348	1
Bin	(0)	1	0	1793943	1

Signal:

INIT_VECT_MSB_17

	From	To	Count	Threshold
Bin	0	1	1731	1
Bin	1	0	1731	1

Signal:

INIT_VECT_MSB_21

	From	To	Count	Threshold
Bin	0	1	1731	1
Bin	1	0	1731	1

Signal:

CRC_17_21_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1395828	1
Bin	1	0	1394227	1

Signal:

CRC_17_21_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11428240	1
Bin	1	0	11429841	1

Signal:

CRC_15_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1397117	1
Bin	1	0	1395516	1

Signal:

CRC_15_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10687858	1
Bin	1	0	10689458	1

Signal:

CRC_ENA_15

	From	To	Count	Threshold
Bin	0	1	55951	1
Bin	1	0	57552	1

Signal:

CRC_ENA_17_21

	From	To	Count	Threshold
Bin	0	1	61938	1
Bin	1	0	63539	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 210:

mr_settings_nisofd = ISO_FD

	Evaluated to	Count	Threshold
Bin	False	1731	1
Bin	True	1731	1

"=" expression on line 214:

mr_settings_nisofd = ISO_FD

	Evaluated to	Count	Threshold
Bin	False	1731	1
Bin	True	1731	1

"=" expression on line 222:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	2085811	1
Bin	True	2173291	1

"=" expression on line 226:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	12235044	1
Bin	True	33450208	1

"=" expression on line 234:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	2094422	1
Bin	True	2170931	1

"=" expression on line 238:

crc_calc_from_rx = '1'

	Evaluated to	Count	Threshold
Bin	False	11689519	1
Bin	True	32038961	1

"=" expression on line 249:

crc_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	641668	1
Bin	True	2465348	1

"and" expression on line 251:

 crc_spec_enable = '1' and crc_15_data_in = DOMINANT 
 <--------LHS-------->     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	223725	1
Bin	True	False	113871	1
Bin	True	True	744	1

"=" expression on line 251:

crc_spec_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	527053	1
Bin	True	114615	1

"=" expression on line 251:

crc_15_data_in = DOMINANT

	Evaluated to	Count	Threshold
Bin	False	417199	1
Bin	True	224469	1

"=" expression on line 255:

crc_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	686073	1
Bin	True	2448419	1

"and" expression on line 257:

 crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT 
 <--------LHS-------->     <-----------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	227291	1
Bin	True	False	113871	1
Bin	True	True	36790	1

"=" expression on line 257:

crc_spec_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	535412	1
Bin	True	150661	1

"=" expression on line 257:

crc_17_21_data_in = DOMINANT

	Evaluated to	Count	Threshold
Bin	False	421992	1
Bin	True	264081	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 210 to 212:

Signal assignment statement on line 210:

Signal assignment statement on line 212:

If statement on lines 214 to 216:

Signal assignment statement on line 214:

Signal assignment statement on line 216:

If statement on lines 222 to 224:

Signal assignment statement on line 222:

Signal assignment statement on line 224:

If statement on lines 226 to 228:

Signal assignment statement on line 226:

Signal assignment statement on line 228:

If statement on lines 234 to 236:

Signal assignment statement on line 234:

Signal assignment statement on line 236:

If statement on lines 238 to 240:

Signal assignment statement on line 238:

Signal assignment statement on line 240:

If statement on lines 249 to 253:

Signal assignment statement on line 249:

Signal assignment statement on line 251:

Signal assignment statement on line 253:

If statement on lines 255 to 259:

Signal assignment statement on line 255:

Signal assignment statement on line 257:

Signal assignment statement on line 259:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 210:

"if" / "when" / "else" condition on line 214:

"if" / "when" / "else" condition on line 222:

"if" / "when" / "else" condition on line 226:

"if" / "when" / "else" condition on line 234:

"if" / "when" / "else" condition on line 238:

"if" / "when" / "else" condition on line 249:

"if" / "when" / "else" condition on line 251:

"if" / "when" / "else" condition on line 255:

"if" / "when" / "else" condition on line 257:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 210: