NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/txt_buffer/txtb_ram.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_PARITY_CALCULATOR_READ	100.0 % (4/4)	N.A.	100.0 % (66/66)	N.A.	N.A.	N.A.	100.0 % (70/70)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_PARITY_CALCULATOR_READ

100.0 % (4/4)

N.A.

100.0 % (66/66)

N.A.

100.0 % (70/70)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(7).G_TXT_BUF_ODD.I_TXTB_ODD_TOP.I_TXTB_RAM.G_PARITY_TRUE	100.0 % (10/10)	100.0 % (12/12)	N.A.	100.0 % (13/13)	N.A.	N.A.	100.0 % (35/35)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(7).G_TXT_BUF_ODD.I_TXTB_ODD_TOP.I_TXTB_RAM.G_PARITY_TRUE

100.0 % (10/10)

100.0 % (12/12)

N.A.

100.0 % (13/13)

N.A.

100.0 % (35/35)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 225 to 231:

225:            if (rst_n = '0') then 
226:                parity_word <= (others => '0'); 
...
230:                end if; 
231:            end if;

Count: 674802
Threshold: 1

Signal assignment statement on line 226:

226: parity_word <= (others => '0');
Count: 428676
Threshold: 1

If statement on lines 228 to 230:

228:                if (txtb_port_a_write = '1') then 
229:                    parity_word(to_integer(unsigned(txtb_port_a_address))) <= txtb_port_a_parity; 
230:                end if;

Count: 122537
Threshold: 1

Signal assignment statement on line 229:

229:                    parity_word(to_integer(unsigned(txtb_port_a_address))) <= txtb_port_a_parity;

Count: 1145
Threshold: 1

If statement on lines 254 to 258:

254:            if (rst_n = '0') then 
255:                parity_read_exp <= '0'; 
256:            elsif (rising_edge(clk_sys)) then 
257:                parity_read_exp <= parity_word(to_integer(unsigned(txtb_port_b_address))); 
258:            end if;

Count: 674802
Threshold: 1

Signal assignment statement on line 255:

255: parity_read_exp <= '0';
Count: 428676
Threshold: 1

Signal assignment statement on line 257:

257: parity_read_exp <= parity_word(to_integer(unsigned(txtb_port_b_address)));
Count: 122537
Threshold: 1

If statement on lines 261 to 263:

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1') 
262:                               else 
263:                           '0';

Count: 3889
Threshold: 1

Signal assignment statement on line 261:

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1')

Count: 450
Threshold: 1

Signal assignment statement on line 263:

263: '0';
Count: 3439
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 225:

225: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	428676	1
Bin	False	246126	1

"if" / "when" / "else" condition on line 227:

227: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	122537	1
Bin	False	123589	1

"if" / "when" / "else" condition on line 228:

228: if (txtb_port_a_write = '1') then

	Evaluated to	Count	Threshold
Bin	True	1145	1
Bin	False	121392	1

"if" / "when" / "else" condition on line 254:

254: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	428676	1
Bin	False	246126	1

"if" / "when" / "else" condition on line 256:

256: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	122537	1
Bin	False	123589	1

"if" / "when" / "else" condition on line 261:

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1')

	Evaluated to	Count	Threshold
Bin	True	450	1
Bin	False	3439	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 225:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	246126	1
Bin	True	428676	1

"=" expression on line 228:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	121392	1
Bin	True	1145	1

"=" expression on line 254:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	246126	1
Bin	True	428676	1

"and" expression on line 261:

 (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1') 
  <---------------LHS--------------->       <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	455	1
Bin	True	False	1644	1
Bin	True	True	450	1

"/=" expression on line 261:

parity_read_real /= parity_read_exp

	Evaluated to	Count	Threshold
Bin	False	1795	1
Bin	True	2094	1

"=" expression on line 261:

mr_settings_pchke = '1'

	Evaluated to	Count	Threshold
Bin	False	2984	1
Bin	True	905	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(7).G_TXT_BUF_ODD.I_TXTB_ODD_TOP.I_TXTB_RAM.G_PARITY_TRUE

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/txt_buffer/txtb_ram.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 225 to 231:

Signal assignment statement on line 226:

If statement on lines 228 to 230:

Signal assignment statement on line 229:

If statement on lines 254 to 258:

Signal assignment statement on line 255:

Signal assignment statement on line 257:

If statement on lines 261 to 263:

Signal assignment statement on line 261:

Signal assignment statement on line 263:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 225:

"if" / "when" / "else" condition on line 227:

"if" / "when" / "else" condition on line 228:

"if" / "when" / "else" condition on line 254:

"if" / "when" / "else" condition on line 256:

"if" / "when" / "else" condition on line 261:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 225:

"=" expression on line 228:

"=" expression on line 254:

"and" expression on line 261:

"/=" expression on line 261:

"=" expression on line 261:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: