NVC code coverage report

Signal assignment statement on line 208:

208:    txtb_port_b_data_out <= txtb_port_b_data_out_i; 
Count: 5792
Threshold: 1

---

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0'; 
Count: 1602
Threshold: 1

---

Signal assignment statement on line 277:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
Count: 92
Threshold: 1

---

Signal assignment statement on line 280:

280:               '0'; 
Count: 1510
Threshold: 1

---

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 10341269
Threshold: 1

---

Signal assignment statement on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
Count: 10326076
Threshold: 1

---

Signal assignment statement on line 285:

285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 15193
Threshold: 1

---

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb; 
Count: 96121
Threshold: 1

---

Signal assignment statement on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
Count: 95070
Threshold: 1

---

Signal assignment statement on line 289:

289:                           mr_tst_control_twrstb; 
Count: 1051
Threshold: 1

---

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata; 
Count: 682126
Threshold: 1

---

Signal assignment statement on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
Count: 672878
Threshold: 1

---

Signal assignment statement on line 293:

293:                          mr_tst_wdata_tst_wdata; 
Count: 9248
Threshold: 1

---

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 85841
Threshold: 1

---

Signal assignment statement on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
Count: 84554
Threshold: 1

---

Signal assignment statement on line 298:

298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 1287
Threshold: 1

---

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0'); 
Count: 6141
Threshold: 1

---

Signal assignment statement on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
Count: 597
Threshold: 1

---

Signal assignment statement on line 302:

302:                                     (others => '0'); 
Count: 5544
Threshold: 1

"if" / "when" / "else" condition on lines 277 to 278:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 

	Evaluated to	Count	Threshold
Bin	True	92	1
Bin	False	1510	1

---

"if" / "when" / "else" condition on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	10326076	1
Bin	False	15193	1

---

"if" / "when" / "else" condition on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	95070	1
Bin	False	1051	1

---

"if" / "when" / "else" condition on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	672878	1
Bin	False	9248	1

---

"if" / "when" / "else" condition on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	84554	1
Bin	False	1287	1

---

"if" / "when" / "else" condition on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 

	Evaluated to	Count	Threshold
Bin	True	597	1
Bin	False	5544	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_ADDR

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_MTGT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_WDATA_TST_WDATA

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_BE

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

Port:

 MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	109	1
Bin	(31)	1	0	274	1
Bin	(30)	0	1	120	1
Bin	(30)	1	0	285	1
Bin	(29)	0	1	123	1
Bin	(29)	1	0	288	1
Bin	(28)	0	1	133	1
Bin	(28)	1	0	298	1
Bin	(27)	0	1	140	1
Bin	(27)	1	0	305	1
Bin	(26)	0	1	138	1
Bin	(26)	1	0	303	1
Bin	(25)	0	1	139	1
Bin	(25)	1	0	304	1
Bin	(24)	0	1	144	1
Bin	(24)	1	0	309	1
Bin	(23)	0	1	137	1
Bin	(23)	1	0	302	1
Bin	(22)	0	1	149	1
Bin	(22)	1	0	314	1
Bin	(21)	0	1	144	1
Bin	(21)	1	0	309	1
Bin	(20)	0	1	142	1
Bin	(20)	1	0	307	1
Bin	(19)	0	1	149	1
Bin	(19)	1	0	314	1
Bin	(18)	0	1	136	1
Bin	(18)	1	0	301	1
Bin	(17)	0	1	138	1
Bin	(17)	1	0	303	1
Bin	(16)	0	1	128	1
Bin	(16)	1	0	293	1
Bin	(15)	0	1	122	1
Bin	(15)	1	0	287	1
Bin	(14)	0	1	141	1
Bin	(14)	1	0	306	1
Bin	(13)	0	1	128	1
Bin	(13)	1	0	293	1
Bin	(12)	0	1	127	1
Bin	(12)	1	0	292	1
Bin	(11)	0	1	137	1
Bin	(11)	1	0	302	1
Bin	(10)	0	1	132	1
Bin	(10)	1	0	297	1
Bin	(9)	0	1	143	1
Bin	(9)	1	0	308	1
Bin	(8)	0	1	136	1
Bin	(8)	1	0	301	1
Bin	(7)	0	1	136	1
Bin	(7)	1	0	301	1
Bin	(6)	0	1	137	1
Bin	(6)	1	0	302	1
Bin	(5)	0	1	133	1
Bin	(5)	1	0	298	1
Bin	(4)	0	1	132	1
Bin	(4)	1	0	297	1
Bin	(3)	0	1	134	1
Bin	(3)	1	0	299	1
Bin	(2)	0	1	133	1
Bin	(2)	1	0	298	1
Bin	(1)	0	1	140	1
Bin	(1)	1	0	305	1
Bin	(0)	0	1	139	1
Bin	(0)	1	0	304	1

---

Port:

 TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	270	1
Bin	(31)	1	0	425	1
Bin	(30)	0	1	223	1
Bin	(30)	1	0	378	1
Bin	(29)	0	1	247	1
Bin	(29)	1	0	402	1
Bin	(28)	0	1	706	1
Bin	(28)	1	0	854	1
Bin	(27)	0	1	637	1
Bin	(27)	1	0	787	1
Bin	(26)	0	1	744	1
Bin	(26)	1	0	895	1
Bin	(25)	0	1	820	1
Bin	(25)	1	0	971	1
Bin	(24)	0	1	800	1
Bin	(24)	1	0	949	1
Bin	(23)	0	1	717	1
Bin	(23)	1	0	869	1
Bin	(22)	0	1	887	1
Bin	(22)	1	0	1037	1
Bin	(21)	0	1	885	1
Bin	(21)	1	0	1036	1
Bin	(20)	0	1	861	1
Bin	(20)	1	0	1013	1
Bin	(19)	0	1	916	1
Bin	(19)	1	0	1065	1
Bin	(18)	0	1	798	1
Bin	(18)	1	0	947	1
Bin	(17)	0	1	700	1
Bin	(17)	1	0	852	1
Bin	(16)	0	1	584	1
Bin	(16)	1	0	735	1
Bin	(15)	0	1	687	1
Bin	(15)	1	0	841	1
Bin	(14)	0	1	627	1
Bin	(14)	1	0	781	1
Bin	(13)	0	1	495	1
Bin	(13)	1	0	646	1
Bin	(12)	0	1	650	1
Bin	(12)	1	0	803	1
Bin	(11)	0	1	873	1
Bin	(11)	1	0	1026	1
Bin	(10)	0	1	686	1
Bin	(10)	1	0	838	1
Bin	(9)	0	1	1079	1
Bin	(9)	1	0	1225	1
Bin	(8)	0	1	749	1
Bin	(8)	1	0	901	1
Bin	(7)	0	1	1173	1
Bin	(7)	1	0	1315	1
Bin	(6)	0	1	1000	1
Bin	(6)	1	0	1149	1
Bin	(5)	0	1	1020	1
Bin	(5)	1	0	1167	1
Bin	(4)	0	1	619	1
Bin	(4)	1	0	771	1
Bin	(3)	0	1	815	1
Bin	(3)	1	0	962	1
Bin	(2)	0	1	921	1
Bin	(2)	1	0	1068	1
Bin	(1)	0	1	1103	1
Bin	(1)	1	0	1247	1
Bin	(0)	0	1	1082	1
Bin	(0)	1	0	1229	1

---

Port:

 PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	508	1
Bin	1	0	673	1

---

Signal:

 TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101611	1
Bin	(4)	1	0	5033297	1
Bin	(3)	0	1	128540	1
Bin	(3)	1	0	5006362	1
Bin	(2)	0	1	109221	1
Bin	(2)	1	0	5025821	1
Bin	(1)	0	1	4895640	1
Bin	(1)	1	0	239710	1
Bin	(0)	0	1	3845768	1
Bin	(0)	1	0	1290176	1

---

Signal:

 TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11469	1
Bin	1	0	11673	1

---

Signal:

 TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	15034	1
Bin	(31)	1	0	318959	1
Bin	(30)	0	1	16359	1
Bin	(30)	1	0	317638	1
Bin	(29)	0	1	14996	1
Bin	(29)	1	0	319009	1
Bin	(28)	0	1	21945	1
Bin	(28)	1	0	312086	1
Bin	(27)	0	1	20704	1
Bin	(27)	1	0	313317	1
Bin	(26)	0	1	19575	1
Bin	(26)	1	0	314444	1
Bin	(25)	0	1	21852	1
Bin	(25)	1	0	312163	1
Bin	(24)	0	1	21143	1
Bin	(24)	1	0	312872	1
Bin	(23)	0	1	20617	1
Bin	(23)	1	0	313382	1
Bin	(22)	0	1	21410	1
Bin	(22)	1	0	312611	1
Bin	(21)	0	1	20791	1
Bin	(21)	1	0	313226	1
Bin	(20)	0	1	20851	1
Bin	(20)	1	0	313168	1
Bin	(19)	0	1	36591	1
Bin	(19)	1	0	297444	1
Bin	(18)	0	1	41483	1
Bin	(18)	1	0	292545	1
Bin	(17)	0	1	39018	1
Bin	(17)	1	0	294997	1
Bin	(16)	0	1	83039	1
Bin	(16)	1	0	250963	1
Bin	(15)	0	1	18913	1
Bin	(15)	1	0	315096	1
Bin	(14)	0	1	20342	1
Bin	(14)	1	0	313677	1
Bin	(13)	0	1	19111	1
Bin	(13)	1	0	314892	1
Bin	(12)	0	1	19180	1
Bin	(12)	1	0	314845	1
Bin	(11)	0	1	41635	1
Bin	(11)	1	0	292378	1
Bin	(10)	0	1	40318	1
Bin	(10)	1	0	293697	1
Bin	(9)	0	1	47144	1
Bin	(9)	1	0	286879	1
Bin	(8)	0	1	50283	1
Bin	(8)	1	0	283742	1
Bin	(7)	0	1	43970	1
Bin	(7)	1	0	290055	1
Bin	(6)	0	1	44637	1
Bin	(6)	1	0	289392	1
Bin	(5)	0	1	45445	1
Bin	(5)	1	0	288574	1
Bin	(4)	0	1	50550	1
Bin	(4)	1	0	283465	1
Bin	(3)	0	1	52298	1
Bin	(3)	1	0	281720	1
Bin	(2)	0	1	56480	1
Bin	(2)	1	0	277544	1
Bin	(1)	0	1	94170	1
Bin	(1)	1	0	239850	1
Bin	(0)	0	1	82875	1
Bin	(0)	1	0	251176	1

---

Signal:

 TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3351	1
Bin	(4)	1	0	3516	1
Bin	(3)	0	1	115	1
Bin	(3)	1	0	280	1
Bin	(2)	0	1	5330	1
Bin	(2)	1	0	5495	1
Bin	(1)	0	1	3972	1
Bin	(1)	1	0	3972	1
Bin	(0)	0	1	11240	1
Bin	(0)	1	0	11405	1

---

Signal:

 TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	270	1
Bin	(31)	1	0	425	1
Bin	(30)	0	1	223	1
Bin	(30)	1	0	378	1
Bin	(29)	0	1	247	1
Bin	(29)	1	0	402	1
Bin	(28)	0	1	706	1
Bin	(28)	1	0	854	1
Bin	(27)	0	1	637	1
Bin	(27)	1	0	787	1
Bin	(26)	0	1	744	1
Bin	(26)	1	0	895	1
Bin	(25)	0	1	820	1
Bin	(25)	1	0	971	1
Bin	(24)	0	1	800	1
Bin	(24)	1	0	949	1
Bin	(23)	0	1	717	1
Bin	(23)	1	0	869	1
Bin	(22)	0	1	887	1
Bin	(22)	1	0	1037	1
Bin	(21)	0	1	885	1
Bin	(21)	1	0	1036	1
Bin	(20)	0	1	861	1
Bin	(20)	1	0	1013	1
Bin	(19)	0	1	916	1
Bin	(19)	1	0	1065	1
Bin	(18)	0	1	798	1
Bin	(18)	1	0	947	1
Bin	(17)	0	1	700	1
Bin	(17)	1	0	852	1
Bin	(16)	0	1	584	1
Bin	(16)	1	0	735	1
Bin	(15)	0	1	687	1
Bin	(15)	1	0	841	1
Bin	(14)	0	1	627	1
Bin	(14)	1	0	781	1
Bin	(13)	0	1	495	1
Bin	(13)	1	0	646	1
Bin	(12)	0	1	650	1
Bin	(12)	1	0	803	1
Bin	(11)	0	1	873	1
Bin	(11)	1	0	1026	1
Bin	(10)	0	1	686	1
Bin	(10)	1	0	838	1
Bin	(9)	0	1	1079	1
Bin	(9)	1	0	1225	1
Bin	(8)	0	1	749	1
Bin	(8)	1	0	901	1
Bin	(7)	0	1	1173	1
Bin	(7)	1	0	1315	1
Bin	(6)	0	1	1000	1
Bin	(6)	1	0	1149	1
Bin	(5)	0	1	1020	1
Bin	(5)	1	0	1167	1
Bin	(4)	0	1	619	1
Bin	(4)	1	0	771	1
Bin	(3)	0	1	815	1
Bin	(3)	1	0	962	1
Bin	(2)	0	1	921	1
Bin	(2)	1	0	1068	1
Bin	(1)	0	1	1103	1
Bin	(1)	1	0	1247	1
Bin	(0)	0	1	1082	1
Bin	(0)	1	0	1229	1

---

Signal:

 TST_ENA

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	257	1

---

Signal:

 PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	25	1
Bin	(20)	1	0	705	1
Bin	(19)	0	1	1	1
Bin	(19)	1	0	729	1
Bin	(18)	0	1	2	1
Bin	(18)	1	0	728	1
Bin	(17)	0	1	4	1
Bin	(17)	1	0	726	1
Bin	(16)	0	1	4	1
Bin	(16)	1	0	726	1
Bin	(15)	0	1	18	1
Bin	(15)	1	0	712	1
Bin	(14)	0	1	9	1
Bin	(14)	1	0	721	1
Bin	(13)	0	1	23	1
Bin	(13)	1	0	707	1
Bin	(12)	0	1	26	1
Bin	(12)	1	0	704	1
Bin	(11)	0	1	48	1
Bin	(11)	1	0	682	1
Bin	(10)	0	1	30	1
Bin	(10)	1	0	700	1
Bin	(9)	0	1	49	1
Bin	(9)	1	0	681	1
Bin	(8)	0	1	34	1
Bin	(8)	1	0	696	1
Bin	(7)	0	1	32	1
Bin	(7)	1	0	698	1
Bin	(6)	0	1	47	1
Bin	(6)	1	0	683	1
Bin	(5)	0	1	67	1
Bin	(5)	1	0	663	1
Bin	(4)	0	1	171	1
Bin	(4)	1	0	559	1
Bin	(3)	0	1	321	1
Bin	(3)	1	0	409	1
Bin	(2)	0	1	405	1
Bin	(2)	1	0	325	1
Bin	(1)	0	1	246	1
Bin	(1)	1	0	484	1
Bin	(0)	0	1	270	1
Bin	(0)	1	0	460	1

---

Signal:

 PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	1446	1
Bin	1	0	1301	1

---

Signal:

 PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	1461	1
Bin	1	0	1626	1

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1	Copy to Clipboard

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold
Bin	True	False	579	1
Bin	True	True	92	1

---

"=" expression on line 277:

 mr_tst_control_tmaena = '1' 

	Evaluated to	Count	Threshold
Bin	False	931	1
Bin	True	671	1

---

"=" expression on line 283:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	15193	1
Bin	True	10326076	1

---

"=" expression on line 287:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1051	1
Bin	True	95070	1

---

"=" expression on line 291:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	9248	1
Bin	True	672878	1

---

"=" expression on line 296:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1287	1
Bin	True	84554	1

---

"=" expression on line 300:

 tst_ena = '1' 

	Evaluated to	Count	Threshold
Bin	False	5544	1
Bin	True	597	1