NVC code coverage report

Signal assignment statement on line 208:

208:    txtb_port_b_data_out <= txtb_port_b_data_out_i; 
Count: 4450
Threshold: 1

---

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0'; 
Count: 1602
Threshold: 1

---

Signal assignment statement on line 277:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
Count: 88
Threshold: 1

---

Signal assignment statement on line 280:

280:               '0'; 
Count: 1514
Threshold: 1

---

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 10341261
Threshold: 1

---

Signal assignment statement on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
Count: 10326101
Threshold: 1

---

Signal assignment statement on line 285:

285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 15160
Threshold: 1

---

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb; 
Count: 96189
Threshold: 1

---

Signal assignment statement on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
Count: 95152
Threshold: 1

---

Signal assignment statement on line 289:

289:                           mr_tst_control_twrstb; 
Count: 1037
Threshold: 1

---

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata; 
Count: 682118
Threshold: 1

---

Signal assignment statement on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
Count: 672897
Threshold: 1

---

Signal assignment statement on line 293:

293:                          mr_tst_wdata_tst_wdata; 
Count: 9221
Threshold: 1

---

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 85833
Threshold: 1

---

Signal assignment statement on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
Count: 84555
Threshold: 1

---

Signal assignment statement on line 298:

298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 1278
Threshold: 1

---

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0'); 
Count: 4791
Threshold: 1

---

Signal assignment statement on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
Count: 588
Threshold: 1

---

Signal assignment statement on line 302:

302:                                     (others => '0'); 
Count: 4203
Threshold: 1

"if" / "when" / "else" condition on lines 277 to 278:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 

	Evaluated to	Count	Threshold
Bin	True	88	1
Bin	False	1514	1

---

"if" / "when" / "else" condition on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	10326101	1
Bin	False	15160	1

---

"if" / "when" / "else" condition on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	95152	1
Bin	False	1037	1

---

"if" / "when" / "else" condition on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	672897	1
Bin	False	9221	1

---

"if" / "when" / "else" condition on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	84555	1
Bin	False	1278	1

---

"if" / "when" / "else" condition on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 

	Evaluated to	Count	Threshold
Bin	True	588	1
Bin	False	4203	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_ADDR

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_MTGT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_WDATA_TST_WDATA

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_BE

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

Port:

 MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	121	1
Bin	(31)	1	0	286	1
Bin	(30)	0	1	111	1
Bin	(30)	1	0	276	1
Bin	(29)	0	1	123	1
Bin	(29)	1	0	288	1
Bin	(28)	0	1	146	1
Bin	(28)	1	0	311	1
Bin	(27)	0	1	127	1
Bin	(27)	1	0	292	1
Bin	(26)	0	1	146	1
Bin	(26)	1	0	311	1
Bin	(25)	0	1	127	1
Bin	(25)	1	0	292	1
Bin	(24)	0	1	117	1
Bin	(24)	1	0	282	1
Bin	(23)	0	1	129	1
Bin	(23)	1	0	294	1
Bin	(22)	0	1	129	1
Bin	(22)	1	0	294	1
Bin	(21)	0	1	136	1
Bin	(21)	1	0	301	1
Bin	(20)	0	1	140	1
Bin	(20)	1	0	305	1
Bin	(19)	0	1	130	1
Bin	(19)	1	0	295	1
Bin	(18)	0	1	134	1
Bin	(18)	1	0	299	1
Bin	(17)	0	1	127	1
Bin	(17)	1	0	292	1
Bin	(16)	0	1	128	1
Bin	(16)	1	0	293	1
Bin	(15)	0	1	124	1
Bin	(15)	1	0	289	1
Bin	(14)	0	1	123	1
Bin	(14)	1	0	288	1
Bin	(13)	0	1	130	1
Bin	(13)	1	0	295	1
Bin	(12)	0	1	127	1
Bin	(12)	1	0	292	1
Bin	(11)	0	1	119	1
Bin	(11)	1	0	284	1
Bin	(10)	0	1	134	1
Bin	(10)	1	0	299	1
Bin	(9)	0	1	133	1
Bin	(9)	1	0	298	1
Bin	(8)	0	1	127	1
Bin	(8)	1	0	292	1
Bin	(7)	0	1	135	1
Bin	(7)	1	0	300	1
Bin	(6)	0	1	133	1
Bin	(6)	1	0	298	1
Bin	(5)	0	1	131	1
Bin	(5)	1	0	296	1
Bin	(4)	0	1	131	1
Bin	(4)	1	0	296	1
Bin	(3)	0	1	138	1
Bin	(3)	1	0	303	1
Bin	(2)	0	1	139	1
Bin	(2)	1	0	304	1
Bin	(1)	0	1	128	1
Bin	(1)	1	0	293	1
Bin	(0)	0	1	130	1
Bin	(0)	1	0	295	1

---

Port:

 TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	226	1
Bin	(31)	1	0	381	1
Bin	(30)	0	1	317	1
Bin	(30)	1	0	472	1
Bin	(29)	0	1	201	1
Bin	(29)	1	0	356	1
Bin	(28)	0	1	776	1
Bin	(28)	1	0	925	1
Bin	(27)	0	1	444	1
Bin	(27)	1	0	594	1
Bin	(26)	0	1	475	1
Bin	(26)	1	0	625	1
Bin	(25)	0	1	720	1
Bin	(25)	1	0	872	1
Bin	(24)	0	1	687	1
Bin	(24)	1	0	838	1
Bin	(23)	0	1	678	1
Bin	(23)	1	0	827	1
Bin	(22)	0	1	481	1
Bin	(22)	1	0	631	1
Bin	(21)	0	1	717	1
Bin	(21)	1	0	867	1
Bin	(20)	0	1	719	1
Bin	(20)	1	0	870	1
Bin	(19)	0	1	697	1
Bin	(19)	1	0	846	1
Bin	(18)	0	1	635	1
Bin	(18)	1	0	784	1
Bin	(17)	0	1	585	1
Bin	(17)	1	0	737	1
Bin	(16)	0	1	344	1
Bin	(16)	1	0	498	1
Bin	(15)	0	1	639	1
Bin	(15)	1	0	792	1
Bin	(14)	0	1	476	1
Bin	(14)	1	0	630	1
Bin	(13)	0	1	442	1
Bin	(13)	1	0	596	1
Bin	(12)	0	1	452	1
Bin	(12)	1	0	606	1
Bin	(11)	0	1	651	1
Bin	(11)	1	0	804	1
Bin	(10)	0	1	435	1
Bin	(10)	1	0	588	1
Bin	(9)	0	1	713	1
Bin	(9)	1	0	863	1
Bin	(8)	0	1	690	1
Bin	(8)	1	0	844	1
Bin	(7)	0	1	741	1
Bin	(7)	1	0	883	1
Bin	(6)	0	1	999	1
Bin	(6)	1	0	1148	1
Bin	(5)	0	1	742	1
Bin	(5)	1	0	894	1
Bin	(4)	0	1	586	1
Bin	(4)	1	0	741	1
Bin	(3)	0	1	528	1
Bin	(3)	1	0	675	1
Bin	(2)	0	1	687	1
Bin	(2)	1	0	836	1
Bin	(1)	0	1	1035	1
Bin	(1)	1	0	1182	1
Bin	(0)	0	1	822	1
Bin	(0)	1	0	967	1

---

Port:

 PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	511	1
Bin	1	0	676	1

---

Signal:

 TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101611	1
Bin	(4)	1	0	5033309	1
Bin	(3)	0	1	128540	1
Bin	(3)	1	0	5006374	1
Bin	(2)	0	1	109221	1
Bin	(2)	1	0	5025833	1
Bin	(1)	0	1	4895639	1
Bin	(1)	1	0	239713	1
Bin	(0)	0	1	3845775	1
Bin	(0)	1	0	1290181	1

---

Signal:

 TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11505	1
Bin	1	0	11707	1

---

Signal:

 TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	15035	1
Bin	(31)	1	0	318972	1
Bin	(30)	0	1	16369	1
Bin	(30)	1	0	317646	1
Bin	(29)	0	1	14999	1
Bin	(29)	1	0	319014	1
Bin	(28)	0	1	21931	1
Bin	(28)	1	0	312092	1
Bin	(27)	0	1	20706	1
Bin	(27)	1	0	313313	1
Bin	(26)	0	1	19572	1
Bin	(26)	1	0	314451	1
Bin	(25)	0	1	21856	1
Bin	(25)	1	0	312149	1
Bin	(24)	0	1	21151	1
Bin	(24)	1	0	312860	1
Bin	(23)	0	1	20616	1
Bin	(23)	1	0	313387	1
Bin	(22)	0	1	21414	1
Bin	(22)	1	0	312613	1
Bin	(21)	0	1	20775	1
Bin	(21)	1	0	313230	1
Bin	(20)	0	1	20847	1
Bin	(20)	1	0	313166	1
Bin	(19)	0	1	35120	1
Bin	(19)	1	0	298912	1
Bin	(18)	0	1	42959	1
Bin	(18)	1	0	291060	1
Bin	(17)	0	1	40494	1
Bin	(17)	1	0	293526	1
Bin	(16)	0	1	83044	1
Bin	(16)	1	0	250970	1
Bin	(15)	0	1	18911	1
Bin	(15)	1	0	315092	1
Bin	(14)	0	1	20344	1
Bin	(14)	1	0	313669	1
Bin	(13)	0	1	19125	1
Bin	(13)	1	0	314894	1
Bin	(12)	0	1	19181	1
Bin	(12)	1	0	314846	1
Bin	(11)	0	1	41640	1
Bin	(11)	1	0	292371	1
Bin	(10)	0	1	40315	1
Bin	(10)	1	0	293696	1
Bin	(9)	0	1	47147	1
Bin	(9)	1	0	286886	1
Bin	(8)	0	1	50276	1
Bin	(8)	1	0	283727	1
Bin	(7)	0	1	43974	1
Bin	(7)	1	0	290063	1
Bin	(6)	0	1	44632	1
Bin	(6)	1	0	289387	1
Bin	(5)	0	1	45436	1
Bin	(5)	1	0	288579	1
Bin	(4)	0	1	50556	1
Bin	(4)	1	0	283463	1
Bin	(3)	0	1	52285	1
Bin	(3)	1	0	281744	1
Bin	(2)	0	1	56481	1
Bin	(2)	1	0	277543	1
Bin	(1)	0	1	94179	1
Bin	(1)	1	0	239847	1
Bin	(0)	0	1	82882	1
Bin	(0)	1	0	251168	1

---

Signal:

 TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3351	1
Bin	(4)	1	0	3516	1
Bin	(3)	0	1	115	1
Bin	(3)	1	0	280	1
Bin	(2)	0	1	5330	1
Bin	(2)	1	0	5495	1
Bin	(1)	0	1	3969	1
Bin	(1)	1	0	3969	1
Bin	(0)	0	1	11238	1
Bin	(0)	1	0	11403	1

---

Signal:

 TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	226	1
Bin	(31)	1	0	381	1
Bin	(30)	0	1	317	1
Bin	(30)	1	0	472	1
Bin	(29)	0	1	201	1
Bin	(29)	1	0	356	1
Bin	(28)	0	1	776	1
Bin	(28)	1	0	925	1
Bin	(27)	0	1	444	1
Bin	(27)	1	0	594	1
Bin	(26)	0	1	475	1
Bin	(26)	1	0	625	1
Bin	(25)	0	1	720	1
Bin	(25)	1	0	872	1
Bin	(24)	0	1	687	1
Bin	(24)	1	0	838	1
Bin	(23)	0	1	678	1
Bin	(23)	1	0	827	1
Bin	(22)	0	1	481	1
Bin	(22)	1	0	631	1
Bin	(21)	0	1	717	1
Bin	(21)	1	0	867	1
Bin	(20)	0	1	719	1
Bin	(20)	1	0	870	1
Bin	(19)	0	1	697	1
Bin	(19)	1	0	846	1
Bin	(18)	0	1	635	1
Bin	(18)	1	0	784	1
Bin	(17)	0	1	585	1
Bin	(17)	1	0	737	1
Bin	(16)	0	1	344	1
Bin	(16)	1	0	498	1
Bin	(15)	0	1	639	1
Bin	(15)	1	0	792	1
Bin	(14)	0	1	476	1
Bin	(14)	1	0	630	1
Bin	(13)	0	1	442	1
Bin	(13)	1	0	596	1
Bin	(12)	0	1	452	1
Bin	(12)	1	0	606	1
Bin	(11)	0	1	651	1
Bin	(11)	1	0	804	1
Bin	(10)	0	1	435	1
Bin	(10)	1	0	588	1
Bin	(9)	0	1	713	1
Bin	(9)	1	0	863	1
Bin	(8)	0	1	690	1
Bin	(8)	1	0	844	1
Bin	(7)	0	1	741	1
Bin	(7)	1	0	883	1
Bin	(6)	0	1	999	1
Bin	(6)	1	0	1148	1
Bin	(5)	0	1	742	1
Bin	(5)	1	0	894	1
Bin	(4)	0	1	586	1
Bin	(4)	1	0	741	1
Bin	(3)	0	1	528	1
Bin	(3)	1	0	675	1
Bin	(2)	0	1	687	1
Bin	(2)	1	0	836	1
Bin	(1)	0	1	1035	1
Bin	(1)	1	0	1182	1
Bin	(0)	0	1	822	1
Bin	(0)	1	0	967	1

---

Signal:

 TST_ENA

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	253	1

---

Signal:

 PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	27	1
Bin	(20)	1	0	677	1
Bin	(19)	0	1	1	1
Bin	(19)	1	0	703	1
Bin	(18)	0	1	2	1
Bin	(18)	1	0	702	1
Bin	(17)	0	1	3	1
Bin	(17)	1	0	701	1
Bin	(16)	0	1	4	1
Bin	(16)	1	0	700	1
Bin	(15)	0	1	5	1
Bin	(15)	1	0	699	1
Bin	(14)	0	1	6	1
Bin	(14)	1	0	698	1
Bin	(13)	0	1	7	1
Bin	(13)	1	0	697	1
Bin	(12)	0	1	8	1
Bin	(12)	1	0	696	1
Bin	(11)	0	1	24	1
Bin	(11)	1	0	680	1
Bin	(10)	0	1	26	1
Bin	(10)	1	0	678	1
Bin	(9)	0	1	17	1
Bin	(9)	1	0	687	1
Bin	(8)	0	1	30	1
Bin	(8)	1	0	674	1
Bin	(7)	0	1	41	1
Bin	(7)	1	0	663	1
Bin	(6)	0	1	44	1
Bin	(6)	1	0	660	1
Bin	(5)	0	1	88	1
Bin	(5)	1	0	616	1
Bin	(4)	0	1	157	1
Bin	(4)	1	0	547	1
Bin	(3)	0	1	295	1
Bin	(3)	1	0	409	1
Bin	(2)	0	1	375	1
Bin	(2)	1	0	329	1
Bin	(1)	0	1	206	1
Bin	(1)	1	0	498	1
Bin	(0)	0	1	269	1
Bin	(0)	1	0	435	1

---

Signal:

 PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	1213	1
Bin	1	0	1070	1

---

Signal:

 PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	943	1
Bin	1	0	1108	1

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1	Copy to Clipboard

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold
Bin	True	False	583	1
Bin	True	True	88	1

---

"=" expression on line 277:

 mr_tst_control_tmaena = '1' 

	Evaluated to	Count	Threshold
Bin	False	931	1
Bin	True	671	1

---

"=" expression on line 283:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	15160	1
Bin	True	10326101	1

---

"=" expression on line 287:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1037	1
Bin	True	95152	1

---

"=" expression on line 291:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	9221	1
Bin	True	672897	1

---

"=" expression on line 296:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1278	1
Bin	True	84555	1

---

"=" expression on line 300:

 tst_ena = '1' 

	Evaluated to	Count	Threshold
Bin	False	4203	1
Bin	True	588	1