NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_TRV_DELAY_RST_REG	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_TRV_DELAY_RST_REG

100.0 % (6/6)

100.0 % (28/28)

100.0 % (2/2)

N.A.

100.0 % (42/42)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_TRV_DELAY_MEAS	100.0 % (36/36)	100.0 % (31/31)	100.0 % (162/162)	100.0 % (30/30)	N.A.	N.A.	100.0 % (259/259)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_TRV_DELAY_MEAS

100.0 % (36/36)

100.0 % (31/31)

100.0 % (162/162)

100.0 % (30/30)

N.A.

100.0 % (259/259)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 247 to 250:

247:    trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else 
248:                           '1' when (edge_tx_valid = '1') else 
249:                           '0' when (edge_rx_valid = '1') else 
250:                           trv_meas_progress_q;

Count: 4200975
Threshold: 1

Signal assignment statement on line 247:

247: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else
Count: 4049359
Threshold: 1

Signal assignment statement on line 248:

248: '1' when (edge_tx_valid = '1') else
Count: 26820
Threshold: 1

Signal assignment statement on line 249:

249: '0' when (edge_rx_valid = '1') else
Count: 42775
Threshold: 1

Signal assignment statement on line 250:

250: trv_meas_progress_q;
Count: 82021
Threshold: 1

If statement on lines 257 to 263:

257:        if (rst_n = '0') then 
258:            trv_meas_progress_q     <= '0'; 
...
262:            trv_meas_progress_del   <= trv_meas_progress_q; 
263:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 258:

258: trv_meas_progress_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 259:

259: trv_meas_progress_del <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 261:

261: trv_meas_progress_q <= trv_meas_progress_d;
Count: 547174334
Threshold: 1

Signal assignment statement on line 262:

262: trv_meas_progress_del <= trv_meas_progress_q;
Count: 547174334
Threshold: 1

If statement on lines 269 to 271:

269:    trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1') 
270:                               else 
271:                           '1';

Count: 1357091
Threshold: 1

Signal assignment statement on line 269:

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')
Count: 13410
Threshold: 1

Signal assignment statement on line 271:

271: '1';
Count: 1343681
Threshold: 1

Signal assignment statement on line 296:

296: trv_delay_ctr_add <= std_logic_vector(unsigned(trv_delay_ctr_q) + 1);
Count: 42449
Threshold: 1

If statement on lines 299 to 301:

299:    trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT) 
300:                                     else 
301:                      trv_delay_ctr_add;

Count: 84898
Threshold: 1

Signal assignment statement on line 299:

299: trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT)
Count: 32
Threshold: 1

Signal assignment statement on line 301:

301: trv_delay_ctr_add;
Count: 84866
Threshold: 1

If statement on lines 308 to 318:

308:        if (trv_delay_ctr_rst_q_scan = '0') then 
309:            trv_delay_ctr_q(0) <= '1'; 
...
317:            end if; 
318:        end if;

Count: 1096808140
Threshold: 1

Signal assignment statement on line 309:

309: trv_delay_ctr_q(0) <= '1';
Count: 2475870
Threshold: 1

Signal assignment statement on line 310:

310: trv_delay_ctr_q(G_TRV_CTR_WIDTH - 1 downto 1) <= (others => '0');
Count: 2475870
Threshold: 1

If statement on lines 315 to 317:

315:            if (trv_meas_progress_q = '1') then 
316:                trv_delay_ctr_q <= trv_delay_ctr_d; 
317:            end if;

Count: 547154441
Threshold: 1

Signal assignment statement on line 316:

316: trv_delay_ctr_q <= trv_delay_ctr_d;
Count: 26163
Threshold: 1

Signal assignment statement on lines 325 to 326:

325:    trv_delay_sum <= std_logic_vector(('0' & unsigned(trv_delay_ctr_q)) + 
326:                                      ('0' & unsigned(mr_ssp_cfg_ssp_offset)));

Count: 50525
Threshold: 1

Sequential statement on lines 333 to 336:

333:    with mr_ssp_cfg_ssp_src select ssp_delay <= 
334:                  trv_delay_sum when SSP_SRC_MEAS_N_OFFSET, 
335:    '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET, 
336:                (others => '0') when others;

Count: 57432
Threshold: 1

Signal assignment statement on line 334:

334: trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,
Count: 35548
Threshold: 1

Signal assignment statement on line 335:

335: '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET,
Count: 2831
Threshold: 1

Signal assignment statement on line 336:

336: (others => '0') when others;
Count: 19053
Threshold: 1

If statement on lines 345 to 354:

345:        if (rst_n = '0') then 
346:            ssp_delay_shadowed <= (others => '0'); 
...
353:            end if; 
354:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 346:

346: ssp_delay_shadowed <= (others => '0');
Count: 2422674
Threshold: 1

Signal assignment statement on line 347:

347: trv_delay_shadowed <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 350 to 353:

350:            if (ssp_shadow_ce = '1') then 
351:                ssp_delay_shadowed <= ssp_delay; 
352:                trv_delay_shadowed <= trv_delay_ctr_q; 
353:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 351:

351: ssp_delay_shadowed <= ssp_delay;
Count: 13410
Threshold: 1

Signal assignment statement on line 352:

352: trv_delay_shadowed <= trv_delay_ctr_q;
Count: 13410
Threshold: 1

If statement on lines 362 to 364:

362:    ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0') 
363:                         else 
364:                     '0';

Count: 58442
Threshold: 1

Signal assignment statement on line 362:

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')
Count: 13410
Threshold: 1

Signal assignment statement on line 364:

364: '0';
Count: 45032
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 247:

247: trv_meas_progress_d <= '0' when (tran_delay_meas = '0') else

	Evaluated to	Count	Threshold
Bin	True	4049359	1
Bin	False	151616	1

"if" / "when" / "else" condition on line 248:

248: '1' when (edge_tx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	26820	1
Bin	False	124796	1

"if" / "when" / "else" condition on line 249:

249: '0' when (edge_rx_valid = '1') else

	Evaluated to	Count	Threshold
Bin	True	42775	1
Bin	False	82021	1

"if" / "when" / "else" condition on line 257:

257: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 260:

260: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 269:

269: trv_delay_ctr_rst_d <= '0' when (tran_delay_meas = '1' and edge_tx_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	13410	1
Bin	False	1343681	1

"if" / "when" / "else" condition on line 299:

299: trv_delay_ctr_d <= C_TRV_DEL_SAT when (trv_delay_ctr_q = C_TRV_DEL_SAT)

	Evaluated to	Count	Threshold
Bin	True	32	1
Bin	False	84866	1

"if" / "when" / "else" condition on line 308:

308: if (trv_delay_ctr_rst_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2475870	1
Bin	False	1094332270	1

"if" / "when" / "else" condition on line 312:

312: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547154441	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 315:

315: if (trv_meas_progress_q = '1') then

	Evaluated to	Count	Threshold
Bin	True	26163	1
Bin	False	547128278	1

"case" / "with" / "select" choice on line 334:

334: trv_delay_sum when SSP_SRC_MEAS_N_OFFSET,

	Choice of	Count	Threshold
Bin	`SSP_SRC_MEAS_N_OFFSET`	35548	1

"case" / "with" / "select" choice on line 335:

335: '0' & mr_ssp_cfg_ssp_offset when SSP_SRC_OFFSET,

	Choice of	Count	Threshold
Bin	`SSP_SRC_OFFSET`	2831	1

"case" / "with" / "select" choice on line 336:

336: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	19053	1

"if" / "when" / "else" condition on line 345:

345: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 349:

349: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 350:

350: if (ssp_shadow_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	13410	1
Bin	False	547160924	1

"if" / "when" / "else" condition on line 362:

362: ssp_shadow_ce <= '1' when (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0')

	Evaluated to	Count	Threshold
Bin	True	13410	1
Bin	False	45032	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

EDGE_TX_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

EDGE_RX_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_DELAY_MEAS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_OFFSET

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_SSP_CFG_SSP_SRC

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

TRV_DELAY_SHADOWED

	Element	From	To	Count	Threshold
Bin	(7)	0	1	23	1
Bin	(7)	1	0	1624	1
Bin	(6)	0	1	38	1
Bin	(6)	1	0	1639	1
Bin	(5)	0	1	69	1
Bin	(5)	1	0	1670	1
Bin	(4)	0	1	86	1
Bin	(4)	1	0	1687	1
Bin	(3)	0	1	77	1
Bin	(3)	1	0	1678	1
Bin	(2)	0	1	85	1
Bin	(2)	1	0	1686	1
Bin	(1)	0	1	2178	1
Bin	(1)	1	0	3779	1
Bin	(0)	0	1	67	1
Bin	(0)	1	0	1668	1

Port:

SSP_DELAY_SHADOWED

	Element	From	To	Count	Threshold
Bin	(8)	0	1	15	1
Bin	(8)	1	0	1616	1
Bin	(7)	0	1	32	1
Bin	(7)	1	0	1633	1
Bin	(6)	0	1	44	1
Bin	(6)	1	0	1645	1
Bin	(5)	0	1	66	1
Bin	(5)	1	0	1667	1
Bin	(4)	0	1	60	1
Bin	(4)	1	0	1661	1
Bin	(3)	0	1	268	1
Bin	(3)	1	0	1869	1
Bin	(2)	0	1	942	1
Bin	(2)	1	0	2543	1
Bin	(1)	0	1	240	1
Bin	(1)	1	0	1841	1
Bin	(0)	0	1	918	1
Bin	(0)	1	0	2519	1

Signal:

TRV_MEAS_PROGRESS_D

	From	To	Count	Threshold
Bin	0	1	13410	1
Bin	1	0	15011	1

Signal:

TRV_MEAS_PROGRESS_Q

	From	To	Count	Threshold
Bin	0	1	13410	1
Bin	1	0	15011	1

Signal:

TRV_MEAS_PROGRESS_DEL

	From	To	Count	Threshold
Bin	0	1	13410	1
Bin	1	0	15011	1

Signal:

TRV_DELAY_CTR_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	66	1
Bin	(7)	1	0	1634	1
Bin	(6)	0	1	154	1
Bin	(6)	1	0	1712	1
Bin	(5)	0	1	384	1
Bin	(5)	1	0	1904	1
Bin	(4)	0	1	804	1
Bin	(4)	1	0	2303	1
Bin	(3)	0	1	1594	1
Bin	(3)	1	0	3100	1
Bin	(2)	0	1	3205	1
Bin	(2)	1	0	4707	1
Bin	(1)	0	1	19631	1
Bin	(1)	1	0	21158	1
Bin	(0)	0	1	21262	1
Bin	(0)	1	0	19586	1

Signal:

TRV_DELAY_CTR_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	33	1
Bin	(7)	1	0	1634	1
Bin	(6)	0	1	78	1
Bin	(6)	1	0	1679	1
Bin	(5)	0	1	197	1
Bin	(5)	1	0	1798	1
Bin	(4)	0	1	406	1
Bin	(4)	1	0	2007	1
Bin	(3)	0	1	809	1
Bin	(3)	1	0	2410	1
Bin	(2)	0	1	1624	1
Bin	(2)	1	0	3225	1
Bin	(1)	0	1	4764	1
Bin	(1)	1	0	3163	1
Bin	(0)	0	1	19586	1
Bin	(0)	1	0	21187	1

Signal:

TRV_DELAY_CTR_ADD

	Element	From	To	Count	Threshold
Bin	(7)	0	1	33	1
Bin	(7)	1	0	1634	1
Bin	(6)	0	1	78	1
Bin	(6)	1	0	1679	1
Bin	(5)	0	1	197	1
Bin	(5)	1	0	1798	1
Bin	(4)	0	1	406	1
Bin	(4)	1	0	2007	1
Bin	(3)	0	1	809	1
Bin	(3)	1	0	2410	1
Bin	(2)	0	1	1624	1
Bin	(2)	1	0	3225	1
Bin	(1)	0	1	4764	1
Bin	(1)	1	0	3163	1
Bin	(0)	0	1	19586	1
Bin	(0)	1	0	21187	1

Signal:

TRV_DELAY_CTR_RST_D

	From	To	Count	Threshold
Bin	0	1	15011	1
Bin	1	0	13410	1

Signal:

TRV_DELAY_CTR_RST_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	21493	1
Bin	1	0	21482	1

Signal:

SSP_SHADOW_CE

	From	To	Count	Threshold
Bin	0	1	13410	1
Bin	1	0	15011	1

Signal:

SSP_DELAY

	Element	From	To	Count	Threshold
Bin	(8)	0	1	20	1
Bin	(8)	1	0	3222	1
Bin	(7)	0	1	56	1
Bin	(7)	1	0	3258	1
Bin	(6)	0	1	96	1
Bin	(6)	1	0	3298	1
Bin	(5)	0	1	207	1
Bin	(5)	1	0	3409	1
Bin	(4)	0	1	359	1
Bin	(4)	1	0	3561	1
Bin	(3)	0	1	4902	1
Bin	(3)	1	0	4914	1
Bin	(2)	0	1	4028	1
Bin	(2)	1	0	7230	1
Bin	(1)	0	1	7054	1
Bin	(1)	1	0	7066	1
Bin	(0)	0	1	15739	1
Bin	(0)	1	0	15751	1

Signal:

TRV_DELAY_SUM

	Element	From	To	Count	Threshold
Bin	(8)	0	1	29	1
Bin	(8)	1	0	1630	1
Bin	(7)	0	1	72	1
Bin	(7)	1	0	1673	1
Bin	(6)	0	1	136	1
Bin	(6)	1	0	1737	1
Bin	(5)	0	1	270	1
Bin	(5)	1	0	1871	1
Bin	(4)	0	1	485	1
Bin	(4)	1	0	2086	1
Bin	(3)	0	1	5137	1
Bin	(3)	1	0	3548	1
Bin	(2)	0	1	4490	1
Bin	(2)	1	0	6091	1
Bin	(1)	0	1	14760	1
Bin	(1)	1	0	13171	1
Bin	(0)	0	1	23584	1
Bin	(0)	1	0	21983	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 247:

tran_delay_meas = '0'

	Evaluated to	Count	Threshold
Bin	False	151616	1
Bin	True	4049359	1

"=" expression on line 248:

edge_tx_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	124796	1
Bin	True	26820	1

"=" expression on line 249:

edge_rx_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	82021	1
Bin	True	42775	1

"=" expression on line 257:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"and" expression on line 269:

 tran_delay_meas = '1' and edge_tx_valid = '1' 
 <--------LHS-------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	625099	1
Bin	True	False	51045	1
Bin	True	True	13410	1

"=" expression on line 269:

tran_delay_meas = '1'

	Evaluated to	Count	Threshold
Bin	False	1292636	1
Bin	True	64455	1

"=" expression on line 269:

edge_tx_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	718582	1
Bin	True	638509	1

"=" expression on line 308:

trv_delay_ctr_rst_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094332270	1
Bin	True	2475870	1

"=" expression on line 315:

trv_meas_progress_q = '1'

	Evaluated to	Count	Threshold
Bin	False	547128278	1
Bin	True	26163	1

"=" expression on line 345:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 350:

ssp_shadow_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	547160924	1
Bin	True	13410	1

"and" expression on line 362:

 (trv_meas_progress_del = '1') and (trv_meas_progress_q = '0') 
  <-----------LHS----------->       <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	16612	1
Bin	True	False	13409	1
Bin	True	True	13410	1

"=" expression on line 362:

trv_meas_progress_del = '1'

	Evaluated to	Count	Threshold
Bin	False	31623	1
Bin	True	26819	1

"=" expression on line 362:

trv_meas_progress_q = '0'

	Evaluated to	Count	Threshold
Bin	False	28420	1
Bin	True	30022	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_TRV_DELAY_MEAS

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 247 to 250:

Signal assignment statement on line 247:

Signal assignment statement on line 248:

Signal assignment statement on line 249:

Signal assignment statement on line 250:

If statement on lines 257 to 263:

Signal assignment statement on line 258:

Signal assignment statement on line 259:

Signal assignment statement on line 261:

Signal assignment statement on line 262:

If statement on lines 269 to 271:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 296:

If statement on lines 299 to 301:

Signal assignment statement on line 299:

Signal assignment statement on line 301:

If statement on lines 308 to 318:

Signal assignment statement on line 309:

Signal assignment statement on line 310:

If statement on lines 315 to 317:

Signal assignment statement on line 316:

Signal assignment statement on lines 325 to 326:

Sequential statement on lines 333 to 336:

Signal assignment statement on line 334:

Signal assignment statement on line 335:

Signal assignment statement on line 336:

If statement on lines 345 to 354:

Signal assignment statement on line 346:

Signal assignment statement on line 347:

If statement on lines 350 to 353:

Signal assignment statement on line 351:

Signal assignment statement on line 352:

If statement on lines 362 to 364:

Signal assignment statement on line 362:

Signal assignment statement on line 364:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 247:

"if" / "when" / "else" condition on line 248:

"if" / "when" / "else" condition on line 249:

"if" / "when" / "else" condition on line 257:

"if" / "when" / "else" condition on line 260:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on line 299:

"if" / "when" / "else" condition on line 308:

"if" / "when" / "else" condition on line 312:

"if" / "when" / "else" condition on line 315:

"case" / "with" / "select" choice on line 334:

"case" / "with" / "select" choice on line 335:

"case" / "with" / "select" choice on line 336:

"if" / "when" / "else" condition on line 345:

"if" / "when" / "else" condition on line 349:

"if" / "when" / "else" condition on line 350:

"if" / "when" / "else" condition on line 362:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal: