NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_crc_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP.I_MAC_CRC_CALC_21_RX	100.0 % (15/15)	100.0 % (14/14)	100.0 % (144/144)	100.0 % (21/21)	N.A.	N.A.	100.0 % (194/194)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP.I_MAC_CRC_CALC_21_RX

100.0 % (15/15)

100.0 % (14/14)

100.0 % (144/144)

100.0 % (21/21)

N.A.

100.0 % (194/194)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

150: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
Count: 6294343
Threshold: 1

If statement on lines 154 to 162:

154:        if (load_init_vect = '1') then 
155:            crc_d <= (others => '0'); 
...
161:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0'); 
162:        end if;

Count: 13492714
Threshold: 1

Signal assignment statement on line 155:

155: crc_d <= (others => '0');
Count: 211720
Threshold: 1

Signal assignment statement on line 156:

156: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
Count: 211720
Threshold: 1

Signal assignment statement on lines 158 to 159:

158:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor 
159:                      G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);

Count: 6601840
Threshold: 1

Signal assignment statement on line 161:

161: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
Count: 6679154
Threshold: 1

If statement on lines 165 to 167:

165:    crc_ce <= '1' when (load_init_vect = '1') else 
166:              '1' when (enable = '1' and trig = '1') else 
167:              '0';

Count: 23105038
Threshold: 1

Signal assignment statement on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else
Count: 113844
Threshold: 1

Signal assignment statement on line 166:

166: '1' when (enable = '1' and trig = '1') else
Count: 6942082
Threshold: 1

Signal assignment statement on line 167:

167: '0';
Count: 16049112
Threshold: 1

If statement on lines 174 to 180:

174:        if (rst_n = '0') then 
175:            crc_q             <= (others => '0'); 
...
179:            end if; 
180:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 175:

175: crc_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 177 to 179:

177:            if (crc_ce = '1') then 
178:                crc_q <= crc_d; 
179:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 178:

178: crc_q <= crc_d;
Count: 7015375
Threshold: 1

Signal assignment statement on line 184:

184: crc <= crc_q;
Count: 6972147
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	True	211720	1
Bin	False	13280994	1

"if" / "when" / "else" condition on line 157:

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	True	6601840	1
Bin	False	6679154	1

"if" / "when" / "else" condition on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	True	113844	1
Bin	False	22991194	1

"if" / "when" / "else" condition on line 166:

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	True	6942082	1
Bin	False	16049112	1

"if" / "when" / "else" condition on line 174:

174: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 176:

176: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 177:

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	7015375	1
Bin	False	540158959	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INIT_VECT_MSB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CRC

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1750548	1
Bin	(20)	1	0	1752139	1
Bin	(19)	0	1	1703965	1
Bin	(19)	1	0	1705564	1
Bin	(18)	0	1	1719889	1
Bin	(18)	1	0	1721489	1
Bin	(17)	0	1	1733300	1
Bin	(17)	1	0	1734899	1
Bin	(16)	0	1	1746057	1
Bin	(16)	1	0	1747657	1
Bin	(15)	0	1	1761040	1
Bin	(15)	1	0	1762637	1
Bin	(14)	0	1	1773792	1
Bin	(14)	1	0	1775388	1
Bin	(13)	0	1	1788103	1
Bin	(13)	1	0	1789698	1
Bin	(12)	0	1	1735619	1
Bin	(12)	1	0	1737217	1
Bin	(11)	0	1	1750649	1
Bin	(11)	1	0	1752247	1
Bin	(10)	0	1	1735803	1
Bin	(10)	1	0	1737400	1
Bin	(9)	0	1	1750856	1
Bin	(9)	1	0	1752454	1
Bin	(8)	0	1	1764927	1
Bin	(8)	1	0	1766523	1
Bin	(7)	0	1	1779762	1
Bin	(7)	1	0	1781362	1
Bin	(6)	0	1	1715511	1
Bin	(6)	1	0	1717109	1
Bin	(5)	0	1	1729494	1
Bin	(5)	1	0	1731092	1
Bin	(4)	0	1	1743073	1
Bin	(4)	1	0	1744671	1
Bin	(3)	0	1	1769789	1
Bin	(3)	1	0	1771385	1
Bin	(2)	0	1	1767065	1
Bin	(2)	1	0	1768664	1
Bin	(1)	0	1	1779026	1
Bin	(1)	1	0	1780626	1
Bin	(0)	0	1	1792348	1
Bin	(0)	1	0	1793943	1

Signal:

CRC_Q

	Element	From	To	Count	Threshold
Bin	(20)	0	1	3547937	1
Bin	(20)	1	0	3422609	1
Bin	(19)	0	1	1703965	1
Bin	(19)	1	0	1713123	1
Bin	(18)	0	1	1719889	1
Bin	(18)	1	0	1728778	1
Bin	(17)	0	1	1733300	1
Bin	(17)	1	0	1743597	1
Bin	(16)	0	1	1746057	1
Bin	(16)	1	0	1756342	1
Bin	(15)	0	1	1761040	1
Bin	(15)	1	0	1770965	1
Bin	(14)	0	1	1773792	1
Bin	(14)	1	0	1783837	1
Bin	(13)	0	1	1788103	1
Bin	(13)	1	0	1798552	1
Bin	(12)	0	1	1735619	1
Bin	(12)	1	0	1745624	1
Bin	(11)	0	1	1750649	1
Bin	(11)	1	0	1759872	1
Bin	(10)	0	1	1735803	1
Bin	(10)	1	0	1746146	1
Bin	(9)	0	1	1750856	1
Bin	(9)	1	0	1760039	1
Bin	(8)	0	1	1764927	1
Bin	(8)	1	0	1774155	1
Bin	(7)	0	1	1779762	1
Bin	(7)	1	0	1789705	1
Bin	(6)	0	1	1715511	1
Bin	(6)	1	0	1724849	1
Bin	(5)	0	1	1729494	1
Bin	(5)	1	0	1739480	1
Bin	(4)	0	1	1743073	1
Bin	(4)	1	0	1751876	1
Bin	(3)	0	1	1769789	1
Bin	(3)	1	0	1778629	1
Bin	(2)	0	1	1767065	1
Bin	(2)	1	0	1776271	1
Bin	(1)	0	1	1779026	1
Bin	(1)	1	0	1788129	1
Bin	(0)	0	1	1792348	1
Bin	(0)	1	0	1801236	1

Signal:

CRC_NXT

	From	To	Count	Threshold
Bin	0	1	3146366	1
Bin	1	0	3144775	1

Signal:

CRC_D

	Element	From	To	Count	Threshold
Bin	(20)	0	1	6766499	1
Bin	(20)	1	0	6618826	1
Bin	(19)	0	1	1719892	1
Bin	(19)	1	0	1802221	1
Bin	(18)	0	1	1733303	1
Bin	(18)	1	0	1812717	1
Bin	(17)	0	1	1746058	1
Bin	(17)	1	0	1821240	1
Bin	(16)	0	1	1761044	1
Bin	(16)	1	0	1845976	1
Bin	(15)	0	1	1773793	1
Bin	(15)	1	0	1855121	1
Bin	(14)	0	1	1788106	1
Bin	(14)	1	0	1873977	1
Bin	(13)	0	1	4869426	1
Bin	(13)	1	0	4958963	1
Bin	(12)	0	1	1750651	1
Bin	(12)	1	0	1835705	1
Bin	(11)	0	1	4869759	1
Bin	(11)	1	0	4964728	1
Bin	(10)	0	1	1750857	1
Bin	(10)	1	0	1828997	1
Bin	(9)	0	1	1764929	1
Bin	(9)	1	0	1848152	1
Bin	(8)	0	1	1779765	1
Bin	(8)	1	0	1864852	1
Bin	(7)	0	1	4848611	1
Bin	(7)	1	0	4933985	1
Bin	(6)	0	1	1729494	1
Bin	(6)	1	0	1806796	1
Bin	(5)	0	1	1743073	1
Bin	(5)	1	0	1817747	1
Bin	(4)	0	1	4903347	1
Bin	(4)	1	0	4994898	1
Bin	(3)	0	1	4898623	1
Bin	(3)	1	0	4983343	1
Bin	(2)	0	1	1779029	1
Bin	(2)	1	0	1856447	1
Bin	(1)	0	1	1792352	1
Bin	(1)	1	0	1870280	1
Bin	(0)	0	1	3147269	1
Bin	(0)	1	0	3237440	1

Signal:

CRC_CE

	From	To	Count	Threshold
Bin	0	1	7055926	1
Bin	1	0	7057527	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

 data_in xor crc_q(G_CRC_WIDTH - 1) 
 <-LHS->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1552805	1
Bin	'0'	'1'	1550761	1
Bin	'1'	'0'	1595605	1
Bin	'1'	'1'	1591970	1

"=" expression on line 154:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	13280994	1
Bin	True	211720	1

"=" expression on line 157:

crc_nxt = '1'

	Evaluated to	Count	Threshold
Bin	False	6679154	1
Bin	True	6601840	1

"=" expression on line 165:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	22991194	1
Bin	True	113844	1

"and" expression on line 166:

 enable = '1' and trig = '1' 
 <---LHS---->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	4491007	1
Bin	True	False	6945233	1
Bin	True	True	6942082	1

"=" expression on line 166:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	9103879	1
Bin	True	13887315	1

"=" expression on line 166:

trig = '1'

	Evaluated to	Count	Threshold
Bin	False	11558105	1
Bin	True	11433089	1

"=" expression on line 174:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 177:

crc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	540158959	1
Bin	True	7015375	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_CRC_TOP.I_MAC_CRC_CALC_21_RX

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_crc_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

If statement on lines 154 to 162:

Signal assignment statement on line 155:

Signal assignment statement on line 156:

Signal assignment statement on lines 158 to 159:

Signal assignment statement on line 161:

If statement on lines 165 to 167:

Signal assignment statement on line 165:

Signal assignment statement on line 166:

Signal assignment statement on line 167:

If statement on lines 174 to 180:

Signal assignment statement on line 175:

If statement on lines 177 to 179:

Signal assignment statement on line 178:

Signal assignment statement on line 184:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

"if" / "when" / "else" condition on line 157:

"if" / "when" / "else" condition on line 165:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 176:

"if" / "when" / "else" condition on line 177:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

"=" expression on line 154:

"=" expression on line 157:

"=" expression on line 165:

"and" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 174:

"=" expression on line 177:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: