NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/frame_filters/ff_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_FF_TOP.G_FILT_SUP_TRUE	100.0 % (11/11)	100.0 % (10/10)	N.A.	100.0 % (30/30)	N.A.	N.A.	100.0 % (51/51)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_FF_TOP.G_FILT_SUP_TRUE

100.0 % (11/11)

100.0 % (10/10)

N.A.

100.0 % (30/30)

N.A.

100.0 % (51/51)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 358 to 360:

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED and rec_is_rtr = RTR_FRAME) 
359:                              else 
360:                          '0';

Count: 31190
Threshold: 1

Signal assignment statement on line 358:

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED and rec_is_rtr = RTR_FRAME)

Count: 4
Threshold: 1

Signal assignment statement on line 360:

360: '0';
Count: 31186
Threshold: 1

If statement on lines 362 to 369:

362:        filter_result <= '1' when (rec_ivld = '0') else 
363:                         '0' when (drop_rtr_frame = '1') else 
...
368:                             else 
369:                         '0';

Count: 48014
Threshold: 1

Signal assignment statement on line 362:

362: filter_result <= '1' when (rec_ivld = '0') else
Count: 23935
Threshold: 1

Signal assignment statement on line 363:

363: '0' when (drop_rtr_frame = '1') else
Count: 4
Threshold: 1

Signal assignment statement on line 364:

364: '1' when (int_filter_a_valid = '1' or
Count: 19881
Threshold: 1

Signal assignment statement on line 369:

369: '0';
Count: 4194
Threshold: 1

If statement on lines 371 to 373:

371:        ident_valid_d <=  filter_result when (mr_mode_afm = '1') 
372:                                        else 
373:                                    '1';

Count: 8508
Threshold: 1

Signal assignment statement on line 371:

371: ident_valid_d <= filter_result when (mr_mode_afm = '1')
Count: 5808
Threshold: 1

Signal assignment statement on line 373:

373: '1';
Count: 2700
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 358:

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED and rec_is_rtr = RTR_FRAME)

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	31186	1

"if" / "when" / "else" condition on line 362:

362: filter_result <= '1' when (rec_ivld = '0') else

	Evaluated to	Count	Threshold
Bin	True	23935	1
Bin	False	24079	1

"if" / "when" / "else" condition on line 363:

363: '0' when (drop_rtr_frame = '1') else

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	24075	1

"if" / "when" / "else" condition on lines 364 to 367:

364:                         '1' when (int_filter_a_valid = '1' or 
365:                                   int_filter_b_valid = '1' or 
366:                                   int_filter_c_valid = '1' or 
367:                                   int_filter_ran_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	19881	1
Bin	False	4194	1

"if" / "when" / "else" condition on line 371:

371: ident_valid_d <= filter_result when (mr_mode_afm = '1')

	Evaluated to	Count	Threshold
Bin	True	5808	1
Bin	False	2700	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 358:

 mr_settings_fdrf = DROP_RF_ENABLED and rec_is_rtr = RTR_FRAME 
 <--------------LHS--------------->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	14601	1
Bin	True	False	4	1
Bin	True	True	4	1

"=" expression on line 358:

mr_settings_fdrf = DROP_RF_ENABLED

	Evaluated to	Count	Threshold
Bin	False	31182	1
Bin	True	8	1

"=" expression on line 358:

rec_is_rtr = RTR_FRAME

	Evaluated to	Count	Threshold
Bin	False	16585	1
Bin	True	14605	1

"=" expression on line 362:

rec_ivld = '0'

	Evaluated to	Count	Threshold
Bin	False	24079	1
Bin	True	23935	1

"=" expression on line 363:

drop_rtr_frame = '1'

	Evaluated to	Count	Threshold
Bin	False	24075	1
Bin	True	4	1

"or" expression on lines 364 to 367:

 int_filter_a_valid = '1' or int_filter_b_valid = '1' or int_filter_c_valid = '1' or int_filter_ran_valid = '1' 
 <-------------------------------------LHS-------------------------------------->    <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	4194	1
Bin	False	True	3	1
Bin	True	False	19713	1

"or" expression on lines 364 to 366:

 int_filter_a_valid = '1' or int_filter_b_valid = '1' or int_filter_c_valid = '1' 
 <-----------------------LHS------------------------>    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	4197	1
Bin	False	True	159	1
Bin	True	False	19554	1

"or" expression on lines 364 to 365:

 int_filter_a_valid = '1' or int_filter_b_valid = '1' 
 <---------LHS---------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	4356	1
Bin	False	True	150	1
Bin	True	False	19404	1

"=" expression on line 364:

int_filter_a_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	4506	1
Bin	True	19569	1

"=" expression on line 365:

int_filter_b_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	23760	1
Bin	True	315	1

"=" expression on line 366:

int_filter_c_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	23751	1
Bin	True	324	1

"=" expression on line 367:

int_filter_ran_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	23907	1
Bin	True	168	1

"=" expression on line 371:

mr_mode_afm = '1'

	Evaluated to	Count	Threshold
Bin	False	2700	1
Bin	True	5808	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_FF_TOP.G_FILT_SUP_TRUE

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/frame_filters/ff_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 358 to 360:

Signal assignment statement on line 358:

Signal assignment statement on line 360:

If statement on lines 362 to 369:

Signal assignment statement on line 362:

Signal assignment statement on line 363:

Signal assignment statement on line 364:

Signal assignment statement on line 369:

If statement on lines 371 to 373:

Signal assignment statement on line 371:

Signal assignment statement on line 373:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 358:

"if" / "when" / "else" condition on line 362:

"if" / "when" / "else" condition on line 363:

"if" / "when" / "else" condition on lines 364 to 367:

"if" / "when" / "else" condition on line 371:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 358:

"=" expression on line 358:

"=" expression on line 358:

"=" expression on line 362:

"=" expression on line 363:

"or" expression on lines 364 to 367:

"or" expression on lines 364 to 366:

"or" expression on lines 364 to 365:

"=" expression on line 364:

"=" expression on line 365:

"=" expression on line 366:

"=" expression on line 367:

"=" expression on line 371:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: