NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(1).G_TXT_BUF_ODD.I_TXTB_ODD_TOP.I_TXTB_RAM

File:  /__w/CTU-CAN-FD/CTU-CAN-FD/src/txt_buffer/txtb_odd_top.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
I_DP_INF_RAM_BE 100.0 % (19/19) 100.0 % (14/14) 100.0 % (1578/1578) 90.0 % (27/30) N.A. N.A. 99.8 % (1638/1641)
G_PARITY_TRUE 100.0 % (14/14) 100.0 % (12/12) 100.0 % (66/66) 100.0 % (13/13) N.A. N.A. 100.0 % (105/105)
G_PARITY_FALSE 100.0 % (4/4) N.A. N.A. N.A. N.A. N.A. 100.0 % (4/4)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(1).G_TXT_BUF_ODD.I_TXTB_ODD_TOP.I_TXTB_RAM 100.0 % (19/19) 100.0 % (12/12) 100.0 % (516/516) 93.3 % (14/15) N.A. N.A. 99.8 % (561/562)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

208:    txtb_port_b_data_out <= txtb_port_b_data_out_i
Count: 105288
Threshold: 1

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0'; 

Count: 6708
Threshold: 1

Signal assignment statement on line 277:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
Count: 283
Threshold: 1

Signal assignment statement on line 280:

280:               '0'
Count: 6425
Threshold: 1

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0); 

Count: 55820726
Threshold: 1

Signal assignment statement on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
Count: 55763165
Threshold: 1

Signal assignment statement on line 285:

285:                             mr_tst_dest_tst_addr(4 downto 0)
Count: 57561
Threshold: 1

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb; 

Count: 360175
Threshold: 1

Signal assignment statement on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
Count: 354674
Threshold: 1

Signal assignment statement on line 289:

289:                           mr_tst_control_twrstb
Count: 5501
Threshold: 1

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata; 

Count: 2207774
Threshold: 1

Signal assignment statement on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
Count: 2171053
Threshold: 1

Signal assignment statement on line 293:

293:                          mr_tst_wdata_tst_wdata
Count: 36721
Threshold: 1

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0); 

Count: 360238
Threshold: 1

Signal assignment statement on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
Count: 355058
Threshold: 1

Signal assignment statement on line 298:

298:                             mr_tst_dest_tst_addr(4 downto 0)
Count: 5180
Threshold: 1

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0'); 

Count: 107455
Threshold: 1

Signal assignment statement on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
Count: 2626
Threshold: 1

Signal assignment statement on line 302:

302:                                     (others => '0')
Count: 104829
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 277 to 278:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 

Evaluated toCountThreshold
BinTrue2831
BinFalse64251

"if" / "when" / "else" condition on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0'
Evaluated toCountThreshold
BinTrue557631651
BinFalse575611

"if" / "when" / "else" condition on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0'
Evaluated toCountThreshold
BinTrue3546741
BinFalse55011

"if" / "when" / "else" condition on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0'
Evaluated toCountThreshold
BinTrue21710531
BinFalse367211

"if" / "when" / "else" condition on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0'
Evaluated toCountThreshold
BinTrue3550581
BinFalse51801

"if" / "when" / "else" condition on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1'
Evaluated toCountThreshold
BinTrue26261
BinFalse1048291

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RST_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 MR_SETTINGS_PCHKE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 MR_TST_CONTROL_TMAENA
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 MR_TST_CONTROL_TWRSTB
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 MR_TST_DEST_TST_ADDR
ElementFromToCountThresholdExcluded due to
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 MR_TST_DEST_TST_MTGT
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 MR_TST_WDATA_TST_WDATA
ElementFromToCountThresholdExcluded due to
Bin(31)0101Exclude file
Bin(31)1001Exclude file
Bin(30)0101Exclude file
Bin(30)1001Exclude file
Bin(29)0101Exclude file
Bin(29)1001Exclude file
Bin(28)0101Exclude file
Bin(28)1001Exclude file
Bin(27)0101Exclude file
Bin(27)1001Exclude file
Bin(26)0101Exclude file
Bin(26)1001Exclude file
Bin(25)0101Exclude file
Bin(25)1001Exclude file
Bin(24)0101Exclude file
Bin(24)1001Exclude file
Bin(23)0101Exclude file
Bin(23)1001Exclude file
Bin(22)0101Exclude file
Bin(22)1001Exclude file
Bin(21)0101Exclude file
Bin(21)1001Exclude file
Bin(20)0101Exclude file
Bin(20)1001Exclude file
Bin(19)0101Exclude file
Bin(19)1001Exclude file
Bin(18)0101Exclude file
Bin(18)1001Exclude file
Bin(17)0101Exclude file
Bin(17)1001Exclude file
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 TXTB_PORT_A_ADDRESS
ElementFromToCountThresholdExcluded due to
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 TXTB_PORT_A_DATA_IN
ElementFromToCountThresholdExcluded due to
Bin(31)0101Exclude file
Bin(31)1001Exclude file
Bin(30)0101Exclude file
Bin(30)1001Exclude file
Bin(29)0101Exclude file
Bin(29)1001Exclude file
Bin(28)0101Exclude file
Bin(28)1001Exclude file
Bin(27)0101Exclude file
Bin(27)1001Exclude file
Bin(26)0101Exclude file
Bin(26)1001Exclude file
Bin(25)0101Exclude file
Bin(25)1001Exclude file
Bin(24)0101Exclude file
Bin(24)1001Exclude file
Bin(23)0101Exclude file
Bin(23)1001Exclude file
Bin(22)0101Exclude file
Bin(22)1001Exclude file
Bin(21)0101Exclude file
Bin(21)1001Exclude file
Bin(20)0101Exclude file
Bin(20)1001Exclude file
Bin(19)0101Exclude file
Bin(19)1001Exclude file
Bin(18)0101Exclude file
Bin(18)1001Exclude file
Bin(17)0101Exclude file
Bin(17)1001Exclude file
Bin(16)0101Exclude file
Bin(16)1001Exclude file
Bin(15)0101Exclude file
Bin(15)1001Exclude file
Bin(14)0101Exclude file
Bin(14)1001Exclude file
Bin(13)0101Exclude file
Bin(13)1001Exclude file
Bin(12)0101Exclude file
Bin(12)1001Exclude file
Bin(11)0101Exclude file
Bin(11)1001Exclude file
Bin(10)0101Exclude file
Bin(10)1001Exclude file
Bin(9)0101Exclude file
Bin(9)1001Exclude file
Bin(8)0101Exclude file
Bin(8)1001Exclude file
Bin(7)0101Exclude file
Bin(7)1001Exclude file
Bin(6)0101Exclude file
Bin(6)1001Exclude file
Bin(5)0101Exclude file
Bin(5)1001Exclude file
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 TXTB_PORT_A_PARITY
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 TXTB_PORT_A_WRITE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 TXTB_PORT_A_BE
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 TXTB_PORT_B_ADDRESS
ElementFromToCountThresholdExcluded due to
Bin(4)0101Exclude file
Bin(4)1001Exclude file
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Covered toggles:

Port:

 MR_TST_RDATA_TST_RDATA
ElementFromToCountThreshold
Bin(31)015871
Bin(31)1021881
Bin(30)016011
Bin(30)1022021
Bin(29)015911
Bin(29)1021921
Bin(28)016321
Bin(28)1022331
Bin(27)016381
Bin(27)1022391
Bin(26)016191
Bin(26)1022201
Bin(25)016271
Bin(25)1022281
Bin(24)016171
Bin(24)1022181
Bin(23)016441
Bin(23)1022451
Bin(22)016341
Bin(22)1022351
Bin(21)016491
Bin(21)1022501
Bin(20)016381
Bin(20)1022391
Bin(19)016431
Bin(19)1022441
Bin(18)016371
Bin(18)1022381
Bin(17)016221
Bin(17)1022231
Bin(16)015841
Bin(16)1021851
Bin(15)016171
Bin(15)1022181
Bin(14)015991
Bin(14)1022001
Bin(13)016041
Bin(13)1022051
Bin(12)016111
Bin(12)1022121
Bin(11)016081
Bin(11)1022091
Bin(10)016071
Bin(10)1022081
Bin(9)016281
Bin(9)1022291
Bin(8)016011
Bin(8)1022021
Bin(7)016311
Bin(7)1022321
Bin(6)016331
Bin(6)1022341
Bin(5)016131
Bin(5)1022141
Bin(4)016241
Bin(4)1022251
Bin(3)016241
Bin(3)1022251
Bin(2)016281
Bin(2)1022291
Bin(1)016211
Bin(1)1022221
Bin(0)016181
Bin(0)1022191

Port:

 TXTB_PORT_B_DATA_OUT
ElementFromToCountThreshold
Bin(31)0158831
Bin(31)1074341
Bin(30)0161411
Bin(30)1076921
Bin(29)0161071
Bin(29)1076581
Bin(28)01175441
Bin(28)10190601
Bin(27)01143981
Bin(27)10159081
Bin(26)01179941
Bin(26)10195051
Bin(25)01150631
Bin(25)10165751
Bin(24)01180621
Bin(24)10195721
Bin(23)01153291
Bin(23)10168411
Bin(22)01178271
Bin(22)10193281
Bin(21)01158721
Bin(21)10173781
Bin(20)01178001
Bin(20)10193151
Bin(19)01155381
Bin(19)10170391
Bin(18)01178971
Bin(18)10194091
Bin(17)0199701
Bin(17)10115031
Bin(16)01101521
Bin(16)10116851
Bin(15)01102291
Bin(15)10117621
Bin(14)01100751
Bin(14)10116071
Bin(13)01101451
Bin(13)10116781
Bin(12)01103481
Bin(12)10118821
Bin(11)01102551
Bin(11)10117871
Bin(10)01112901
Bin(10)10127611
Bin(9)01192241
Bin(9)10206341
Bin(8)01110891
Bin(8)10126221
Bin(7)01248931
Bin(7)10261241
Bin(6)01161131
Bin(6)10175081
Bin(5)01134411
Bin(5)10149641
Bin(4)01117851
Bin(4)10133141
Bin(3)01201661
Bin(3)10216181
Bin(2)01207481
Bin(2)10221601
Bin(1)01201351
Bin(1)10215831
Bin(0)01276321
Bin(0)10289271

Port:

 PARITY_MISMATCH
FromToCountThreshold
Bin0117531
Bin1033541

Signal:

 TXTB_PORT_A_ADDRESS_I
ElementFromToCountThreshold
Bin(4)013277821
Bin(4)10275098341
Bin(3)015791521
Bin(3)10272584201
Bin(2)014396021
Bin(2)10273984381
Bin(1)01270702361
Bin(1)107687461
Bin(0)01176870031
Bin(0)10101539081

Signal:

 TXTB_PORT_A_WRITE_I
FromToCountThreshold
Bin011287631
Bin101304921

Signal:

 TXTB_PORT_A_DATA_I
ElementFromToCountThreshold
Bin(31)01611861
Bin(31)1010204721
Bin(30)01648171
Bin(30)1010168571
Bin(29)01630391
Bin(29)1010186391
Bin(28)01891701
Bin(28)109925281
Bin(27)01819751
Bin(27)109997231
Bin(26)01761091
Bin(26)1010055611
Bin(25)01851061
Bin(25)109965721
Bin(24)01789481
Bin(24)1010027281
Bin(23)01702751
Bin(23)1010114371
Bin(22)011060461
Bin(22)109756281
Bin(21)01750611
Bin(21)1010066271
Bin(20)01813831
Bin(20)1010002931
Bin(19)011105541
Bin(19)109711351
Bin(18)011269321
Bin(18)109547611
Bin(17)011174531
Bin(17)109642671
Bin(16)011864541
Bin(16)108952311
Bin(15)01736131
Bin(15)1010080591
Bin(14)01856531
Bin(14)109960111
Bin(13)01775341
Bin(13)1010041261
Bin(12)01782141
Bin(12)1010034821
Bin(11)011008421
Bin(11)109808401
Bin(10)011179331
Bin(10)109637311
Bin(9)011694531
Bin(9)109122551
Bin(8)011515421
Bin(8)109301341
Bin(7)011270901
Bin(7)109546321
Bin(6)011132521
Bin(6)109684781
Bin(5)011064611
Bin(5)109752331
Bin(4)011616531
Bin(4)109200571
Bin(3)011333251
Bin(3)109483641
Bin(2)011592151
Bin(2)109224801
Bin(1)012283831
Bin(1)108533351
Bin(0)011921511
Bin(0)108896441

Signal:

 TXTB_PORT_B_ADDRESS_I
ElementFromToCountThreshold
Bin(4)01276551
Bin(4)10292561
Bin(3)0141731
Bin(3)1057741
Bin(2)01475621
Bin(2)10491631
Bin(1)01393121
Bin(1)10393151
Bin(0)011053101
Bin(0)101069081

Signal:

 TXTB_PORT_B_DATA_OUT_I
ElementFromToCountThreshold
Bin(31)0158831
Bin(31)1074341
Bin(30)0161411
Bin(30)1076921
Bin(29)0161071
Bin(29)1076581
Bin(28)01175441
Bin(28)10190601
Bin(27)01143981
Bin(27)10159081
Bin(26)01179941
Bin(26)10195051
Bin(25)01150631
Bin(25)10165751
Bin(24)01180621
Bin(24)10195721
Bin(23)01153291
Bin(23)10168411
Bin(22)01178271
Bin(22)10193281
Bin(21)01158721
Bin(21)10173781
Bin(20)01178001
Bin(20)10193151
Bin(19)01155381
Bin(19)10170391
Bin(18)01178971
Bin(18)10194091
Bin(17)0199701
Bin(17)10115031
Bin(16)01101521
Bin(16)10116851
Bin(15)01102291
Bin(15)10117621
Bin(14)01100751
Bin(14)10116071
Bin(13)01101451
Bin(13)10116781
Bin(12)01103481
Bin(12)10118821
Bin(11)01102551
Bin(11)10117871
Bin(10)01112901
Bin(10)10127611
Bin(9)01192241
Bin(9)10206341
Bin(8)01110891
Bin(8)10126221
Bin(7)01248931
Bin(7)10261241
Bin(6)01161131
Bin(6)10175081
Bin(5)01134411
Bin(5)10149641
Bin(4)01117851
Bin(4)10133141
Bin(3)01201661
Bin(3)10216181
Bin(2)01207481
Bin(2)10221601
Bin(1)01201351
Bin(1)10215831
Bin(0)01276321
Bin(0)10289271

Signal:

 TST_ENA
FromToCountThreshold
Bin012831
Bin1018841

Signal:

 PARITY_WORD
ElementFromToCountThreshold
Bin(20)011571
Bin(20)1047651
Bin(19)0141
Bin(19)1049181
Bin(18)01121
Bin(18)1049101
Bin(17)01181
Bin(17)1049041
Bin(16)01191
Bin(16)1049031
Bin(15)01251
Bin(15)1048971
Bin(14)01321
Bin(14)1048901
Bin(13)01461
Bin(13)1048761
Bin(12)01391
Bin(12)1048831
Bin(11)012151
Bin(11)1047071
Bin(10)012241
Bin(10)1046981
Bin(9)011491
Bin(9)1047731
Bin(8)013291
Bin(8)1045931
Bin(7)014401
Bin(7)1044821
Bin(6)013251
Bin(6)1045971
Bin(5)017611
Bin(5)1041611
Bin(4)0111611
Bin(4)1037611
Bin(3)0121121
Bin(3)1028101
Bin(2)0125001
Bin(2)1024221
Bin(1)0114951
Bin(1)1034271
Bin(0)0116041
Bin(0)1033181

Signal:

 PARITY_READ_REAL
FromToCountThreshold
Bin0172811
Bin1076441

Signal:

 PARITY_READ_EXP
FromToCountThreshold
Bin0178361
Bin1094371

Uncovered expressions:

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

LHSRHSCountThresholdExclude Command
BinFalseTrue01

Excluded expressions:

Covered expressions:

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

LHSRHSCountThreshold
BinTrueFalse15681
BinTrueTrue2831

"=" expression on line 277:

 mr_tst_control_tmaena = '1' 
Evaluated toCountThreshold
BinFalse48571
BinTrue18511

"=" expression on line 283:

 tst_ena = '0' 
Evaluated toCountThreshold
BinFalse575611
BinTrue557631651

"=" expression on line 287:

 tst_ena = '0' 
Evaluated toCountThreshold
BinFalse55011
BinTrue3546741

"=" expression on line 291:

 tst_ena = '0' 
Evaluated toCountThreshold
BinFalse367211
BinTrue21710531

"=" expression on line 296:

 tst_ena = '0' 
Evaluated toCountThreshold
BinFalse51801
BinTrue3550581

"=" expression on line 300:

 tst_ena = '1' 
Evaluated toCountThreshold
BinFalse1048291
BinTrue26261

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: