NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RX_SHIFT_REG

File:  /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
I_RX_SHIFT_RES_REG 100.0 % (6/6) 100.0 % (6/6) 100.0 % (28/28) 100.0 % (2/2) N.A. N.A. 100.0 % (42/42)
G_RX_SHIFT_CMD(0) 100.0 % (3/3) 100.0 % (2/2) N.A. 100.0 % (7/7) N.A. N.A. 100.0 % (12/12)
G_RX_SHIFT_CMD(1) 100.0 % (3/3) 100.0 % (2/2) N.A. 85.7 % (6/7) N.A. N.A. 91.6 % (11/12)
G_RX_SHIFT_CMD(2) 100.0 % (3/3) 100.0 % (2/2) N.A. 85.7 % (6/7) N.A. N.A. 91.6 % (11/12)
G_RX_SHIFT_CMD(3) 100.0 % (3/3) 100.0 % (2/2) N.A. 85.7 % (6/7) N.A. N.A. 91.6 % (11/12)
I_SHIFT_REG_BYTE 100.0 % (30/30) 100.0 % (30/30) 100.0 % (156/156) 100.0 % (22/22) N.A. N.A. 100.0 % (238/238)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RX_SHIFT_REG 100.0 % (45/45) 100.0 % (54/54) 100.0 % (324/324) 100.0 % (43/43) N.A. N.A. 100.0 % (466/466)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 222 to 224:

222:    rst_n_i_d <= '0' when (rx_clear = '1' or rst_n = '0') 
223:                     else 
224:                 '1'; 
Count: 161288
Threshold: 1

Signal assignment statement on line 222:

222:    rst_n_i_d <= '0' when (rx_clear = '1' or rst_n = '0') 
Count: 79037
Threshold: 1

Signal assignment statement on line 224:

224:                 '1'; 
Count: 82251
Threshold: 1

Signal assignment statement on line 260:

260:    rec_dlc_d <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
Count: 5030634
Threshold: 1

Signal assignment statement on lines 262 to 263:

262:    rx_shift_in_sel_demuxed <= rx_shift_in_sel & rx_shift_in_sel & 
263:                               rx_shift_in_sel; 
Count: 76512
Threshold: 1

If statement on lines 289 to 301:

289:        if (rst_n_i_q_scan = '0') then 
290:            rec_ident <= (others => '0'); 
...
300:            end if; 
301:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 290:

290:            rec_ident <= (others => '0'); 
Count: 2603493
Threshold: 1

If statement on lines 292 to 295:

292:            if (rx_store_base_id = '1') then 
293:                rec_ident(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) <= 
294:                    rx_shift_reg_q(9 downto 0) & rx_data_nbs; 
295:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on lines 293 to 294:

293:                rec_ident(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) <= 
294:                    rx_shift_reg_q(9 downto 0) & rx_data_nbs; 
Count: 53363
Threshold: 1

If statement on lines 297 to 300:

297:            if (rx_store_ext_id = '1') then 
298:                rec_ident(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L) <= 
299:                    rx_shift_reg_q(16 downto 0) & rx_data_nbs; 
300:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on lines 298 to 299:

298:                rec_ident(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L) <= 
299:                    rx_shift_reg_q(16 downto 0) & rx_data_nbs; 
Count: 17041
Threshold: 1

If statement on lines 309 to 315:

309:        if (rst_n_i_q_scan = '0') then 
310:            rec_ident_type <= '0'; 
...
314:            end if; 
315:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 310:

310:            rec_ident_type <= '0'; 
Count: 2603493
Threshold: 1

If statement on lines 312 to 314:

312:            if (rx_store_ide = '1') then 
313:                rec_ident_type <= rx_data_nbs; 
314:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on line 313:

313:                rec_ident_type <= rx_data_nbs; 
Count: 53024
Threshold: 1

If statement on lines 323 to 329:

323:        if (rst_n_i_q_scan = '0') then 
324:            rec_is_rtr_i <= '0'; 
...
328:            end if; 
329:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 324:

324:            rec_is_rtr_i <= '0'; 
Count: 2603493
Threshold: 1

If statement on lines 326 to 328:

326:            if (rx_store_rtr = '1') then 
327:                rec_is_rtr_i <= rx_data_nbs; 
328:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on line 327:

327:                rec_is_rtr_i <= rx_data_nbs; 
Count: 70134
Threshold: 1

If statement on lines 333 to 335:

333:    rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) 
334:                               else 
335:                  NO_RTR_FRAME; 
Count: 107248
Threshold: 1

Signal assignment statement on line 333:

333:    rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) 
Count: 77198
Threshold: 1

Signal assignment statement on line 335:

335:                  NO_RTR_FRAME; 
Count: 30050
Threshold: 1

If statement on lines 342 to 348:

342:        if (rst_n_i_q_scan = '0') then 
343:            rec_frame_type_i <= '0'; 
...
347:            end if; 
348:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 343:

343:            rec_frame_type_i <= '0'; 
Count: 2603493
Threshold: 1

If statement on lines 345 to 347:

345:            if (rx_store_edl = '1') then 
346:                rec_frame_type_i <= rx_data_nbs; 
347:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on line 346:

346:                rec_frame_type_i <= rx_data_nbs; 
Count: 51046
Threshold: 1

Signal assignment statement on line 351:

351:    rec_frame_type <= rec_frame_type_i; 
Count: 60094
Threshold: 1

If statement on lines 359 to 365:

359:        if (rst_n_i_q_scan = '0') then 
360:            rec_esi <= '0'; 
...
364:            end if; 
365:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 360:

360:            rec_esi <= '0'; 
Count: 2603493
Threshold: 1

If statement on lines 362 to 364:

362:            if (rx_store_esi = '1') then 
363:                rec_esi <= rx_data_nbs; 
364:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on line 363:

363:                rec_esi <= rx_data_nbs; 
Count: 28084
Threshold: 1

If statement on lines 373 to 379:

373:        if (rst_n_i_q_scan = '0') then 
374:            rec_brs <= '0'; 
...
378:            end if; 
379:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 374:

374:            rec_brs <= '0'; 
Count: 2603493
Threshold: 1

If statement on lines 376 to 378:

376:            if (rx_store_brs = '1') then 
377:                rec_brs <= rx_data_nbs; 
378:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on line 377:

377:                rec_brs <= rx_data_nbs; 
Count: 28132
Threshold: 1

If statement on lines 387 to 393:

387:        if (rst_n_i_q_scan = '0') then 
388:            rec_dlc <= (others => '0'); 
...
392:            end if; 
393:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 388:

388:            rec_dlc <= (others => '0'); 
Count: 2603493
Threshold: 1

If statement on lines 390 to 392:

390:            if (rx_store_dlc = '1') then 
391:                rec_dlc <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
392:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on line 391:

391:                rec_dlc <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
Count: 49952
Threshold: 1

If statement on lines 401 to 407:

401:        if (rst_n_i_q_scan = '0') then 
402:            rx_stuff_count <= (others => '0'); 
...
406:            end if; 
407:        end if; 
Count: 1096893222
Threshold: 1

Signal assignment statement on line 402:

402:            rx_stuff_count <= (others => '0'); 
Count: 2603493
Threshold: 1

If statement on lines 404 to 406:

404:            if (rx_store_stuff_count = '1') then 
405:                rx_stuff_count <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
406:            end if; 
Count: 547111900
Threshold: 1

Signal assignment statement on line 405:

405:                rx_stuff_count <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
Count: 12785
Threshold: 1

Signal assignment statement on line 415:

415:    rx_crc <= rx_shift_reg_q(20 downto 0); 
Count: 4859041
Threshold: 1

Signal assignment statement on line 424:

424:    store_data_word <= rx_shift_reg_q; 
Count: 5855823
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 222:

222:    rst_n_i_d <= '0' when (rx_clear = '1' or rst_n = '0') 
Evaluated toCountThreshold
BinTrue790371
BinFalse822511

"if" / "when" / "else" condition on line 289:

289:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 291:

291:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 292:

292:            if (rx_store_base_id = '1') then 
Evaluated toCountThreshold
BinTrue533631
BinFalse5470585371

"if" / "when" / "else" condition on line 297:

297:            if (rx_store_ext_id = '1') then 
Evaluated toCountThreshold
BinTrue170411
BinFalse5470948591

"if" / "when" / "else" condition on line 309:

309:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 311:

311:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 312:

312:            if (rx_store_ide = '1') then 
Evaluated toCountThreshold
BinTrue530241
BinFalse5470588761

"if" / "when" / "else" condition on line 323:

323:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 325:

325:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 326:

326:            if (rx_store_rtr = '1') then 
Evaluated toCountThreshold
BinTrue701341
BinFalse5470417661

"if" / "when" / "else" condition on line 333:

333:    rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) 
Evaluated toCountThreshold
BinTrue771981
BinFalse300501

"if" / "when" / "else" condition on line 342:

342:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 344:

344:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 345:

345:            if (rx_store_edl = '1') then 
Evaluated toCountThreshold
BinTrue510461
BinFalse5470608541

"if" / "when" / "else" condition on line 359:

359:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 361:

361:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 362:

362:            if (rx_store_esi = '1') then 
Evaluated toCountThreshold
BinTrue280841
BinFalse5470838161

"if" / "when" / "else" condition on line 373:

373:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 375:

375:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 376:

376:            if (rx_store_brs = '1') then 
Evaluated toCountThreshold
BinTrue281321
BinFalse5470837681

"if" / "when" / "else" condition on line 387:

387:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 389:

389:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 390:

390:            if (rx_store_dlc = '1') then 
Evaluated toCountThreshold
BinTrue499521
BinFalse5470619481

"if" / "when" / "else" condition on line 401:

401:        if (rst_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26034931
BinFalse10942897291

"if" / "when" / "else" condition on line 403:

403:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5471119001
BinFalse5471778291

"if" / "when" / "else" condition on line 404:

404:            if (rx_store_stuff_count = '1') then 
Evaluated toCountThreshold
BinTrue127851
BinFalse5470991151

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RST_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 SCAN_MODE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_TRIGGER
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_DATA_NBS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_CLEAR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_SHIFT_ENA
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 RX_SHIFT_IN_SEL
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_BASE_ID
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_EXT_ID
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_IDE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_RTR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_EDL
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_DLC
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_ESI
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_BRS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_STUFF_COUNT
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Port:

 REC_IDENT
ElementFromToCountThreshold
Bin(28)01349771
Bin(28)10304961
Bin(27)01257971
Bin(27)10195531
Bin(26)01378821
Bin(26)10320841
Bin(25)01246071
Bin(25)10190931
Bin(24)01398611
Bin(24)10330291
Bin(23)01290501
Bin(23)10217211
Bin(22)01386731
Bin(22)10326101
Bin(21)01280171
Bin(21)10213071
Bin(20)01354041
Bin(20)10300521
Bin(19)01279091
Bin(19)10216921
Bin(18)01395481
Bin(18)10333941
Bin(17)0176071
Bin(17)10745421
Bin(16)0178531
Bin(16)10756451
Bin(15)0172301
Bin(15)10737281
Bin(14)0164671
Bin(14)10728891
Bin(13)0159831
Bin(13)10714061
Bin(12)0159521
Bin(12)10710541
Bin(11)0178211
Bin(11)10755781
Bin(10)0169861
Bin(10)10735691
Bin(9)0181031
Bin(9)10760971
Bin(8)0168511
Bin(8)10733391
Bin(7)0166671
Bin(7)10728311
Bin(6)0167761
Bin(6)10737831
Bin(5)0185851
Bin(5)10770831
Bin(4)0181551
Bin(4)10766241
Bin(3)0174071
Bin(3)10744401
Bin(2)0171431
Bin(2)10740781
Bin(1)0179901
Bin(1)10754611
Bin(0)0188011
Bin(0)10772391

Port:

 REC_DLC_D
ElementFromToCountThreshold
Bin(3)015773331
Bin(3)105789281
Bin(2)015866881
Bin(2)105882801
Bin(1)015958531
Bin(1)105974451
Bin(0)0113995371
Bin(0)1013979361

Port:

 REC_DLC
ElementFromToCountThreshold
Bin(3)01201311
Bin(3)10217311
Bin(2)01212721
Bin(2)10228691
Bin(1)01215281
Bin(1)10231281
Bin(0)01269611
Bin(0)10285581

Port:

 REC_IS_RTR
FromToCountThreshold
Bin01236361
Bin10252351

Port:

 REC_IDENT_TYPE
FromToCountThreshold
Bin01187961
Bin10203951

Port:

 REC_FRAME_TYPE
FromToCountThreshold
Bin01284491
Bin10300441

Port:

 REC_BRS
FromToCountThreshold
Bin01200491
Bin10216441

Port:

 REC_ESI
FromToCountThreshold
Bin0125811
Bin1041811

Port:

 STORE_DATA_WORD
ElementFromToCountThreshold
Bin(31)012418811
Bin(31)102434801
Bin(30)012492461
Bin(30)102508441
Bin(29)012602711
Bin(29)102618651
Bin(28)012686081
Bin(28)102702081
Bin(27)012785471
Bin(27)102801451
Bin(26)012859991
Bin(26)102875971
Bin(25)012944481
Bin(25)102960441
Bin(24)013034851
Bin(24)103050821
Bin(23)012930241
Bin(23)102946211
Bin(22)013013661
Bin(22)103029621
Bin(21)013089031
Bin(21)103105001
Bin(20)013169161
Bin(20)103185131
Bin(19)013302771
Bin(19)103318731
Bin(18)013376041
Bin(18)103392011
Bin(17)013436251
Bin(17)103452231
Bin(16)013516171
Bin(16)103532141
Bin(15)013932201
Bin(15)103948171
Bin(14)014069741
Bin(14)104085711
Bin(13)014170881
Bin(13)104186861
Bin(12)014274261
Bin(12)104290241
Bin(11)014397391
Bin(11)104413341
Bin(10)014525211
Bin(10)104541151
Bin(9)014622271
Bin(9)104638241
Bin(8)014748221
Bin(8)104764181
Bin(7)015202771
Bin(7)105218741
Bin(6)015334351
Bin(6)105350301
Bin(5)015425981
Bin(5)105441931
Bin(4)015540731
Bin(4)105556661
Bin(3)015657901
Bin(3)105673851
Bin(2)015773331
Bin(2)105789281
Bin(1)015866881
Bin(1)105882801
Bin(0)015958531
Bin(0)105974451

Port:

 RX_CRC
ElementFromToCountThreshold
Bin(20)016995261
Bin(20)1013592131
Bin(19)016177781
Bin(19)1012842181
Bin(18)016609441
Bin(18)1011685791
Bin(17)016374311
Bin(17)1011783371
Bin(16)0112932511
Bin(16)1020917311
Bin(15)017475501
Bin(15)1011934421
Bin(14)015867551
Bin(14)105655371
Bin(13)015718441
Bin(13)105933171
Bin(12)015996321
Bin(12)105901501
Bin(11)015907531
Bin(11)106139171
Bin(10)016296421
Bin(10)106074761
Bin(9)016160031
Bin(9)106374261
Bin(8)016536801
Bin(8)106262831
Bin(7)015203211
Bin(7)105219101
Bin(6)015334801
Bin(6)105350711
Bin(5)015426611
Bin(5)105442511
Bin(4)015541061
Bin(4)105557281
Bin(3)015658621
Bin(3)105674261
Bin(2)015774001
Bin(2)105789961
Bin(1)015867531
Bin(1)105883581
Bin(0)015959031
Bin(0)105975011

Port:

 RX_STUFF_COUNT
ElementFromToCountThreshold
Bin(3)0135041
Bin(3)1051041
Bin(2)0167761
Bin(2)1083751
Bin(1)0177611
Bin(1)1093591
Bin(0)0160731
Bin(0)1076721

Signal:

 RST_N_I_D
FromToCountThreshold
Bin01790491
Bin10790371

Signal:

 RST_N_I_Q_SCAN
FromToCountThreshold
Bin01640341
Bin10640231

Signal:

 RX_SHIFT_REG_Q
ElementFromToCountThreshold
Bin(31)018214901
Bin(31)1013456211
Bin(30)017410631
Bin(30)1013642501
Bin(29)016792011
Bin(29)1015643581
Bin(28)017531911
Bin(28)1015333421
Bin(27)017165921
Bin(27)1015533761
Bin(26)017743031
Bin(26)1014812101
Bin(25)017089871
Bin(25)1015662111
Bin(24)017822271
Bin(24)1015368061
Bin(23)0112996891
Bin(23)1022284851
Bin(22)018002571
Bin(22)1014757921
Bin(21)017728951
Bin(21)1014614101
Bin(20)018475861
Bin(20)1014128591
Bin(19)017608461
Bin(19)1014236951
Bin(18)018297661
Bin(18)1012937561
Bin(17)017898311
Bin(17)1013251731
Bin(16)018344151
Bin(16)1013327261
Bin(15)018443531
Bin(15)1011597921
Bin(14)0110595351
Bin(14)1010846641
Bin(13)018921751
Bin(13)1012648471
Bin(12)0110490501
Bin(12)1011424681
Bin(11)019137381
Bin(11)1012840511
Bin(10)0110838151
Bin(10)1011617861
Bin(9)019373331
Bin(9)1013052901
Bin(8)0111126751
Bin(8)1011854331
Bin(7)019957571
Bin(7)1013607391
Bin(6)0110802521
Bin(6)1010589571
Bin(5)0110633961
Bin(5)1011517451
Bin(4)0111398871
Bin(4)1011273001
Bin(3)0110586901
Bin(3)1012558851
Bin(2)0117408871
Bin(2)1016416501
Bin(1)0110794501
Bin(1)1011103271
Bin(0)0111349961
Bin(0)1010717741

Signal:

 RX_SHIFT_CMD
ElementFromToCountThreshold
Bin(3)0128364531
Bin(3)1097308231
Bin(2)0128815141
Bin(2)1096857621
Bin(1)0129342251
Bin(1)1096330511
Bin(0)0130717711
Bin(0)1094955051

Signal:

 RX_SHIFT_IN_SEL_DEMUXED
ElementFromToCountThreshold
Bin(3)01366551
Bin(3)10382561
Bin(2)01366551
Bin(2)10382561
Bin(1)01366551
Bin(1)10382561

Signal:

 REC_IS_RTR_I
FromToCountThreshold
Bin01236361
Bin10252351

Signal:

 REC_FRAME_TYPE_I
FromToCountThreshold
Bin01284491
Bin10300441

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 222:

 rx_clear = '1' or rst_n = '0' 
 <----LHS----->    <---RHS---> 
LHSRHSCountThreshold
BinFalseFalse822511
BinFalseTrue80721
BinTrueFalse709651

"=" expression on line 222:

 rx_clear = '1' 
Evaluated toCountThreshold
BinFalse903231
BinTrue709651

"=" expression on line 222:

 rst_n = '0' 
Evaluated toCountThreshold
BinFalse1532161
BinTrue80721

"=" expression on line 289:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 292:

 rx_store_base_id = '1' 
Evaluated toCountThreshold
BinFalse5470585371
BinTrue533631

"=" expression on line 297:

 rx_store_ext_id = '1' 
Evaluated toCountThreshold
BinFalse5470948591
BinTrue170411

"=" expression on line 309:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 312:

 rx_store_ide = '1' 
Evaluated toCountThreshold
BinFalse5470588761
BinTrue530241

"=" expression on line 323:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 326:

 rx_store_rtr = '1' 
Evaluated toCountThreshold
BinFalse5470417661
BinTrue701341

"=" expression on line 333:

 rec_frame_type_i = NORMAL_CAN 
Evaluated toCountThreshold
BinFalse300501
BinTrue771981

"=" expression on line 342:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 345:

 rx_store_edl = '1' 
Evaluated toCountThreshold
BinFalse5470608541
BinTrue510461

"=" expression on line 359:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 362:

 rx_store_esi = '1' 
Evaluated toCountThreshold
BinFalse5470838161
BinTrue280841

"=" expression on line 373:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 376:

 rx_store_brs = '1' 
Evaluated toCountThreshold
BinFalse5470837681
BinTrue281321

"=" expression on line 387:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 390:

 rx_store_dlc = '1' 
Evaluated toCountThreshold
BinFalse5470619481
BinTrue499521

"=" expression on line 401:

 rst_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10942897291
BinTrue26034931

"=" expression on line 404:

 rx_store_stuff_count = '1' 
Evaluated toCountThreshold
BinFalse5470991151
BinTrue127851

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: