File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Protocol control module.
71: --
72: -- Sub-modules:
73: -- 1. Protocol control FSM.
74: -- 2. TX Shift register.
75: -- 3. RX Shift register.
76: -- 4. Error detector.
77: -- 5. Control counter
78: -- 6. Re-integration counter.
79: -- 7. Retransmitt counter.
80: --------------------------------------------------------------------------------
81:
82: Library ieee;
83: use ieee.std_logic_1164.all;
84: use ieee.numeric_std.ALL;
85:
86: Library ctu_can_fd_rtl;
87: use ctu_can_fd_rtl.can_constants_pkg.all;
88: use ctu_can_fd_rtl.can_types_pkg.all;
89:
90: use ctu_can_fd_rtl.CAN_FD_register_map.all;
91: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
92:
93: entity mac_pc_top is
94: generic (
95: -- Control counter width
96: G_CTRL_CTR_WIDTH : natural;
97:
98: -- Retransmitt limit counter width
99: G_RETR_LIM_CTR_WIDTH : natural
100: );
101: port (
102: -------------------------------------------------------------------------------------------
103: -- Clock and Asynchronous Reset
104: -------------------------------------------------------------------------------------------
105: clk_sys : in std_logic;
106: rst_n : in std_logic;
107:
108: -------------------------------------------------------------------------------------------
109: -- DFT support
110: -------------------------------------------------------------------------------------------
111: scan_mode : in std_logic;
112:
113: -------------------------------------------------------------------------------------------
114: -- Memory registers interface
115: -------------------------------------------------------------------------------------------
116: mr_mode_acf : in std_logic;
117: mr_mode_stm : in std_logic;
118: mr_mode_bmm : in std_logic;
119: mr_mode_fde : in std_logic;
120: mr_mode_rom : in std_logic;
121: mr_mode_tstm : in std_logic;
122: mr_mode_sam : in std_logic;
123:
124: mr_settings_ena : in std_logic;
125: mr_settings_nisofd : in std_logic;
126: mr_settings_rtrth : in std_logic_vector(G_RETR_LIM_CTR_WIDTH - 1 downto 0);
127: mr_settings_rtrle : in std_logic;
128: mr_settings_ilbp : in std_logic;
129: mr_settings_pex : in std_logic;
130:
131: mr_command_ercrst : in std_logic;
132: mr_command_cpexs : in std_logic;
133:
134: mr_ssp_cfg_ssp_src : in std_logic_vector(1 downto 0);
135:
136: -- ALC register
137: alc_alc_bit : out std_logic_vector(4 downto 0);
138: alc_alc_id_field : out std_logic_vector(2 downto 0);
139:
140: -- ERR_CAPT register
141: err_capt_err_type : out std_logic_vector(2 downto 0);
142: err_capt_err_pos : out std_logic_vector(3 downto 0);
143: err_capt_err_erp : out std_logic;
144:
145: -- Protocol exception status
146: mr_status_pexs : out std_logic;
147:
148: -- Protocol control debug information
149: pc_dbg : out t_protocol_control_dbg;
150:
151: -------------------------------------------------------------------------------------------
152: -- TXT Buffers interface
153: -------------------------------------------------------------------------------------------
154: -- TX Data word
155: tran_word : in std_logic_vector(31 downto 0);
156:
157: -- TX Data length code
158: tran_dlc : in std_logic_vector(3 downto 0);
159:
160: -- TX Remote transmission request flag
161: tran_is_rtr : in std_logic;
162:
163: -- TX Identifier type (0-Basic, 1-Extended)
164: tran_ident_type : in std_logic;
165:
166: -- TX Frame type (0-CAN 2.0, 1-CAN FD)
167: tran_frame_type : in std_logic;
168:
169: -- TX Bit rate shift
170: tran_brs : in std_logic;
171:
172: -- TX Identifier
173: tran_identifier : in std_logic_vector(28 downto 0);
174:
175: -- TX frame test word
176: tran_frame_test : in t_frame_test_w;
177:
178: -- Frame in TXT Buffer is valid any can be transmitted.
179: tran_frame_valid : in std_logic;
180:
181: -- Transmission frame
182: tran_frame_parity_error : in std_logic;
183:
184: -- HW Commands for TX Arbitrator and TXT Buffers
185: txtb_hw_cmd : out t_txtb_hw_cmd;
186:
187: -- Pointer to TXT buffer memory
188: txtb_ptr : out natural range 0 to 20;
189:
190: -- Clock enable for TXT Buffer memory
191: txtb_clk_en : out std_logic;
192:
193: -- Selected TXT Buffer index changed
194: txtb_changed : in std_logic;
195:
196: -------------------------------------------------------------------------------------------
197: -- RX Buffer interface
198: -------------------------------------------------------------------------------------------
199: -- RX CAN Identifier
200: rec_ident : out std_logic_vector(28 downto 0);
201:
202: -- RX Data length code
203: rec_dlc : out std_logic_vector(3 downto 0);
204:
205: -- RX Remote transmission request flag
206: rec_is_rtr : out std_logic;
207:
208: -- RX Recieved identifier type (0-BASE Format, 1-Extended Format);
209: rec_ident_type : out std_logic;
210:
211: -- RX frame type (0-CAN 2.0, 1- CAN FD)
212: rec_frame_type : out std_logic;
213:
214: -- Received Loopback frame
215: rec_lbpf : out std_logic;
216:
217: -- RX Bit rate shift Flag
218: rec_brs : out std_logic;
219:
220: -- RX Error state indicator
221: rec_esi : out std_logic;
222:
223: -- RX Identifier is valid
224: rec_ivld : out std_logic;
225:
226: -- Store Metadata in RX Buffer
227: store_metadata : out std_logic;
228:
229: -- Abort storing of frame in RX Buffer. Revert to last frame.
230: rec_abort : out std_logic;
231:
232: -- Store data word to RX Buffer.
233: store_data : out std_logic;
234:
235: -- Data words to be stored to RX Buffer.
236: store_data_word : out std_logic_vector(31 downto 0);
237:
238: -- Pulse in Start of Frame
239: sof_pulse : out std_logic;
240:
241: -------------------------------------------------------------------------------------------
242: -- Operation control FSM Interface
243: -------------------------------------------------------------------------------------------
244: -- Unit is transmitter
245: is_transmitter : in std_logic;
246:
247: -- Unit is receiver
248: is_receiver : in std_logic;
249:
250: -- Loss of arbitration -> Turn receiver!
251: arbitration_lost : out std_logic;
252:
253: -- Set unit to be transmitter (in SOF)
254: set_transmitter : out std_logic;
255:
256: -- Set unit to be receiver
257: set_receiver : out std_logic;
258:
259: -- Set unit to be idle
260: set_idle : out std_logic;
261:
262: -------------------------------------------------------------------------------------------
263: -- Fault confinement Interface
264: -------------------------------------------------------------------------------------------
265: -- Unit is error active
266: is_err_active : in std_logic;
267:
268: -- Unit is error passive
269: is_err_passive : in std_logic;
270:
271: -- Unit is Bus-off
272: is_bus_off : in std_logic;
273:
274: -- Error detected
275: err_detected : out std_logic;
276:
277: -- Primary Error
278: primary_err : out std_logic;
279:
280: -- Active Error or Overload flag is being tranmsmitted
281: act_err_ovr_flag : out std_logic;
282:
283: -- Error delimiter too late
284: err_delim_late : out std_logic;
285:
286: -- Set unit to be error active
287: set_err_active : out std_logic;
288:
289: -- Error counters should remain unchanged
290: err_ctrs_unchanged : out std_logic;
291:
292: -------------------------------------------------------------------------------------------
293: -- TX and RX Trigger signals to Sample and Transmitt Data
294: -------------------------------------------------------------------------------------------
295: -- TX Trigger (in SYNC segment)
296: tx_trigger : in std_logic;
297:
298: -- RX Trigger (one clock cycle delayed after Sample point)
299: rx_trigger : in std_logic;
300:
301: -------------------------------------------------------------------------------------------
302: -- CAN Bus serial data stream
303: -------------------------------------------------------------------------------------------
304: -- TX Data
305: tx_data_nbs : out std_logic;
306:
307: -- TX Data (post bit stuffing)
308: tx_data_wbs : in std_logic;
309:
310: -- RX Data
311: rx_data_nbs : in std_logic;
312:
313: -------------------------------------------------------------------------------------------
314: -- Bit Stuffing Interface
315: -------------------------------------------------------------------------------------------
316: -- Bit Stuffing enabled
317: stuff_enable : out std_logic;
318:
319: -- Bit De-stuffing enabled
320: destuff_enable : out std_logic;
321:
322: -- Bit Stuffing type (0-Normal, 1-Fixed)
323: fixed_stuff : out std_logic;
324:
325: -- Frame transmission without SOF started
326: tx_frame_no_sof : out std_logic;
327:
328: -- Number of de-stuffed bits modulo 8
329: dst_ctr : in std_logic_vector(2 downto 0);
330:
331: -- Number of stuffed bits modulo 8
332: bst_ctr : in std_logic_vector(2 downto 0);
333:
334: -- Stuff Error
335: stuff_err : in std_logic;
336:
337: -------------------------------------------------------------------------------------------
338: -- Bus Sampling Interface
339: -------------------------------------------------------------------------------------------
340: -- Bit Error detected
341: bit_err : in std_logic;
342:
343: -- Reset Bit time measurement counter
344: btmc_reset : out std_logic;
345:
346: -- Start Measurement of data bit time (in TX Trigger)
347: dbt_measure_start : out std_logic;
348:
349: -- First SSP generated (in ESI bit)
350: gen_first_ssp : out std_logic;
351:
352: -- Synchronization edge
353: sync_edge : in std_logic;
354:
355: -- Bit error detection enabled
356: bit_err_enable : out std_logic;
357:
358: -------------------------------------------------------------------------------------------
359: -- CRC Interface
360: -------------------------------------------------------------------------------------------
361: -- Enable CRC calculation
362: crc_enable : out std_logic;
363:
364: -- CRC calculation - speculative enable
365: crc_spec_enable : out std_logic;
366:
367: -- Use RX Data for CRC calculation
368: crc_calc_from_rx : out std_logic;
369:
370: -- Load CRC Initialization vector
371: load_init_vect : out std_logic;
372:
373: -- Calculated CRC 15
374: crc_15 : in std_logic_vector(14 downto 0);
375:
376: -- Calculated CRC 17
377: crc_17 : in std_logic_vector(16 downto 0);
378:
379: -- Calculated CRC 21
380: crc_21 : in std_logic_vector(20 downto 0);
381:
382: -------------------------------------------------------------------------------------------
383: -- Control signals
384: -------------------------------------------------------------------------------------------
385: -- Sample control (Nominal, Data, Secondary)
386: sp_control : out std_logic_vector(1 downto 0);
387:
388: -- Sample control (Registered)
389: sp_control_q : out std_logic_vector(1 downto 0);
390:
391: -- Enable Nominal Bit time counters.
392: nbt_ctrs_en : out std_logic;
393:
394: -- Enable Data Bit time counters.
395: dbt_ctrs_en : out std_logic;
396:
397: -- Synchronisation control (No synchronisation, Hard Synchronisation, Resynchronisation
398: sync_control : out std_logic_vector(1 downto 0);
399:
400: -- Clear the Shift register for secondary sampling point.
401: ssp_reset : out std_logic;
402:
403: -- Enable measurement of Transmitter delay
404: tran_delay_meas : out std_logic;
405:
406: -- Transmitted frame is valid
407: tran_valid : out std_logic;
408:
409: -- Received frame is valid
410: rec_valid : out std_logic;
411:
412: -- Decrement Receive Error counter
413: decrement_rec : out std_logic;
414:
415: -- Bit Error in passive error flag after ACK Error
416: bit_err_after_ack_err : out std_logic;
417:
418: -------------------------------------------------------------------------------------------
419: -- Status signals
420: -------------------------------------------------------------------------------------------
421: -- Bit rate shifted
422: br_shifted : out std_logic;
423:
424: -- Form Error has occurred
425: form_err : out std_logic;
426:
427: -- ACK Error has occurred
428: ack_err : out std_logic;
429:
430: -- CRC Error has occurred
431: crc_err : out std_logic;
432:
433: -- Status of retransmit counter (for observation purpose)
434: retr_ctr : out std_logic_vector(G_RETR_LIM_CTR_WIDTH - 1 downto 0)
435: );
436: end entity;
437:
438: architecture rtl of mac_pc_top is
439:
440: -- Error frame request
441: signal err_frm_req : std_logic;
442:
443: -- Load commands for TX Shift register
444: signal tx_load_base_id : std_logic;
445: signal tx_load_ext_id : std_logic;
446: signal tx_load_dlc : std_logic;
447: signal tx_load_data_word : std_logic;
448: signal tx_load_stuff_count : std_logic;
449: signal tx_load_crc : std_logic;
450:
451: -- TX Shift register enabled
452: signal tx_shift_ena : std_logic;
453:
454: -- Transmit dominant bit
455: signal tx_dominant : std_logic;
456:
457: -- Clear all registers in RX Shift register
458: signal rx_clear : std_logic;
459:
460: -- Store commands for RX Shift register
461: signal rx_store_base_id : std_logic;
462: signal rx_store_ext_id : std_logic;
463: signal rx_store_ide : std_logic;
464: signal rx_store_rtr : std_logic;
465: signal rx_store_edl : std_logic;
466: signal rx_store_dlc : std_logic;
467: signal rx_store_esi : std_logic;
468: signal rx_store_brs : std_logic;
469: signal rx_store_stuff_count : std_logic;
470:
471: -- Clock Enable RX Shift register for each byte.
472: signal rx_shift_ena : std_logic_vector(3 downto 0);
473:
474: -- Selector for inputs of each byte of shift register (0-Previous byte output, 1-RX Data input)
475: signal rx_shift_in_sel : std_logic;
476:
477: -- RX value of Remote transmission request
478: signal rec_is_rtr_i : std_logic;
479:
480: -- RX value of DLC (combinational), valid only in last bit of DLC
481: signal rec_dlc_d : std_logic_vector(3 downto 0);
482:
483: -- RX value of DLC (captured)
484: signal rec_dlc_q : std_logic_vector(3 downto 0);
485:
486: -- RX frame type (0-CAN 2.0, 1- CAN FD)
487: signal rec_frame_type_i : std_logic;
488:
489: -- Preload control counter
490: signal ctrl_ctr_pload : std_logic;
491:
492: -- Control counter preload value
493: signal ctrl_ctr_pload_val : std_logic_vector(8 downto 0);
494:
495: -- Control counter is enabled
496: signal ctrl_ctr_ena : std_logic;
497:
498: -- Control counter is zero
499: signal ctrl_ctr_zero : std_logic;
500:
501: -- Control counter is equal to 1
502: signal ctrl_ctr_one : std_logic;
503:
504: -- Control counter counted multiple of 8 bits
505: signal ctrl_counted_byte : std_logic;
506:
507: -- Control counter byte index within a memory word
508: signal ctrl_counted_byte_index : std_logic_vector(1 downto 0);
509:
510: -- Control counter - TXT Buffer memory index
511: signal ctrl_ctr_mem_index : std_logic_vector(4 downto 0);
512:
513: -- Complementary counter enable
514: signal compl_ctr_ena : std_logic;
515:
516: -- Reintegration counter Clear (synchronous)
517: signal reinteg_ctr_clr : std_logic;
518:
519: -- Enable counting (with RX Trigger)
520: signal reinteg_ctr_enable : std_logic;
521:
522: -- Reintegration counter expired (reached 128)
523: signal reinteg_ctr_expired : std_logic;
524:
525: -- Clear Retransmitt counter
526: signal retr_ctr_clear : std_logic;
527:
528: -- Increment Retransmitt counter by 1
529: signal retr_ctr_add : std_logic;
530:
531: -- Retransmitt limit was reached
532: signal retr_limit_reached : std_logic;
533:
534: -- Form Error has occurred
535: signal form_err_i : std_logic;
536:
537: -- ACK Error has occurred
538: signal ack_err_i : std_logic;
539:
540: -- Perform CRC check
541: signal crc_check : std_logic;
542:
543: -- Bit Error in arbitration field
544: signal bit_err_arb : std_logic;
545:
546: -- Calculated CRC and Stuff count are matching received ones
547: signal crc_match : std_logic;
548:
549: -- CRC error signalling
550: signal crc_err_i : std_logic;
551:
552: -- Clear CRC Match flag
553: signal crc_clear_match_flag : std_logic;
554:
555: -- CRC Source (CRC15, CRC17, CRC21)
556: signal crc_src : std_logic_vector(1 downto 0);
557:
558: -- Error position field (for Error capture)
559: signal err_pos : std_logic_vector(3 downto 0);
560:
561: -- Received CRC (driven from RX Shift register)
562: signal rx_crc : std_logic_vector(20 downto 0);
563:
564: -- RX Stuff count (grey coded) + RX parity
565: signal rx_stuff_count : std_logic_vector(3 downto 0);
566:
567: -- Fixed Stuff (internal)
568: signal fixed_stuff_i : std_logic;
569:
570: -- Arbitration lost (internal)
571: signal arbitration_lost_i : std_logic;
572:
573: -- Part of arbitration currently transmitted
574: signal arbitration_part : std_logic_vector(2 downto 0);
575:
576: -- Debug status of protocol controller
577: signal pc_dbg_i : t_protocol_control_dbg;
578:
579: begin
580:
581: -----------------------------------------------------------------------------------------------
582: -- Protocol control FSM
583: -----------------------------------------------------------------------------------------------
584: i_mac_pc_fsm : entity ctu_can_fd_rtl.mac_pc_fsm
585: port map(
586: clk_sys => clk_sys, -- IN
587: rst_n => rst_n, -- IN
588:
589: -- Signals which cause state change
590: rx_trigger => rx_trigger, -- IN
591: err_frm_req => err_frm_req, -- IN
592:
593: -- Memory registers interface
594: mr_settings_ena => mr_settings_ena, -- IN
595: mr_settings_nisofd => mr_settings_nisofd, -- IN
596: mr_command_ercrst => mr_command_ercrst, -- IN
597: mr_mode_acf => mr_mode_acf, -- IN
598: mr_mode_stm => mr_mode_stm, -- IN
599: mr_mode_bmm => mr_mode_bmm, -- IN
600: mr_settings_rtrle => mr_settings_rtrle, -- IN
601: mr_settings_ilbp => mr_settings_ilbp, -- IN
602: mr_mode_fde => mr_mode_fde, -- IN
603: mr_ssp_cfg_ssp_src => mr_ssp_cfg_ssp_src, -- IN
604: mr_settings_pex => mr_settings_pex, -- IN
605: mr_command_cpexs => mr_command_cpexs, -- IN
606: mr_mode_rom => mr_mode_rom, -- IN
607: mr_mode_sam => mr_mode_sam, -- IN
608:
609: mr_status_pexs => mr_status_pexs, -- OUT
610:
611: pc_dbg => pc_dbg_i, -- OUT
612:
613: -- Data-path interface
614: tx_data_wbs => tx_data_wbs, -- IN
615: rx_data_nbs => rx_data_nbs, -- IN
616:
617: -- RX Buffer interface
618: store_metadata => store_metadata, -- OUT
619: store_data => store_data, -- OUT
620: rec_valid => rec_valid, -- OUT
621: rec_abort => rec_abort, -- OUT
622: sof_pulse => sof_pulse, -- OUT
623:
624: -- TXT Buffer, TX Arbitrator interface
625: tran_frame_valid => tran_frame_valid, -- IN
626: txtb_hw_cmd => txtb_hw_cmd, -- OUT
627: txtb_ptr => txtb_ptr, -- OUT
628: txtb_clk_en => txtb_clk_en, -- OUT
629: tran_dlc => tran_dlc, -- IN
630: tran_is_rtr => tran_is_rtr, -- IN
631: tran_frame_type => tran_frame_type, -- IN
632: tran_ident_type => tran_ident_type, -- IN
633: tran_brs => tran_brs, -- IN
634:
635: -- TX Shift register interface
636: tx_load_base_id => tx_load_base_id, -- OUT
637: tx_load_ext_id => tx_load_ext_id, -- OUT
638: tx_load_dlc => tx_load_dlc, -- OUT
639: tx_load_data_word => tx_load_data_word, -- OUT
640: tx_load_stuff_count => tx_load_stuff_count, -- OUT
641: tx_load_crc => tx_load_crc, -- OUT
642: tx_shift_ena => tx_shift_ena, -- OUT
643: tx_dominant => tx_dominant, -- OUT
644:
645: -- RX Shift register interface
646: rx_clear => rx_clear, -- OUT
647: rx_store_base_id => rx_store_base_id, -- OUT
648: rx_store_ext_id => rx_store_ext_id, -- OUT
649: rx_store_ide => rx_store_ide, -- OUT
650: rx_store_rtr => rx_store_rtr, -- OUT
651: rx_store_edl => rx_store_edl, -- OUT
652: rx_store_dlc => rx_store_dlc, -- OUT
653: rx_store_esi => rx_store_esi, -- OUT
654: rx_store_brs => rx_store_brs, -- OUT
655: rx_store_stuff_count => rx_store_stuff_count, -- OUT
656: rx_shift_ena => rx_shift_ena, -- OUT
657: rx_shift_in_sel => rx_shift_in_sel, -- OUT
658: rec_is_rtr => rec_is_rtr_i, -- IN
659: rec_dlc_d => rec_dlc_d, -- IN
660: rec_dlc_q => rec_dlc_q, -- IN
661: rec_frame_type => rec_frame_type_i, -- IN
662: rec_lbpf => rec_lbpf, -- OUT
663: rec_ivld => rec_ivld, -- OUT
664:
665: -- Control counter interface
666: ctrl_ctr_pload => ctrl_ctr_pload, -- OUT
667: ctrl_ctr_pload_val => ctrl_ctr_pload_val, -- OUT
668: ctrl_ctr_ena => ctrl_ctr_ena, -- OUT
669: ctrl_ctr_zero => ctrl_ctr_zero, -- IN
670: ctrl_ctr_one => ctrl_ctr_one, -- IN
671: ctrl_counted_byte => ctrl_counted_byte, -- IN
672: ctrl_counted_byte_index => ctrl_counted_byte_index, -- IN
673: ctrl_ctr_mem_index => ctrl_ctr_mem_index, -- IN
674: compl_ctr_ena => compl_ctr_ena, -- OUT
675: arbitration_part => arbitration_part, -- OUT
676:
677: -- Reintegration counter interface
678: reinteg_ctr_clr => reinteg_ctr_clr, -- OUT
679: reinteg_ctr_enable => reinteg_ctr_enable, -- OUT
680: reinteg_ctr_expired => reinteg_ctr_expired, -- IN
681:
682: -- Retransmitt counter interface
683: retr_ctr_clear => retr_ctr_clear, -- OUT
684: retr_ctr_add => retr_ctr_add, -- OUT
685: retr_limit_reached => retr_limit_reached, -- IN
686:
687: -- Error detector interface
688: form_err => form_err_i, -- OUT
689: ack_err => ack_err_i, -- OUT
690: crc_check => crc_check, -- OUT
691: bit_err_arb => bit_err_arb, -- OUT
692: bit_err_after_ack_err => bit_err_after_ack_err, -- OUT
693: crc_match => crc_match, -- IN
694: crc_err => crc_err_i, -- OUT
695: crc_clear_match_flag => crc_clear_match_flag, -- OUT
696: crc_src => crc_src, -- OUT
697: err_pos => err_pos, -- OUT
698:
699: -- Bit Stuffing/Destuffing control signals
700: stuff_enable => stuff_enable, -- OUT
701: destuff_enable => destuff_enable, -- OUT
702: fixed_stuff => fixed_stuff_i, -- OUT
703: tx_frame_no_sof => tx_frame_no_sof, -- OUT
704:
705: -- Operation control interface
706: is_transmitter => is_transmitter, -- IN
707: is_receiver => is_receiver, -- IN
708: arbitration_lost => arbitration_lost_i, -- OUT
709: set_transmitter => set_transmitter, -- OUT
710: set_receiver => set_receiver, -- OUT
711: set_idle => set_idle, -- OUT
712:
713: -- Fault confinement interface
714: primary_err => primary_err, -- OUT
715: act_err_ovr_flag => act_err_ovr_flag, -- OUT
716: set_err_active => set_err_active, -- OUT
717: err_delim_late => err_delim_late, -- OUT
718: is_err_active => is_err_active, -- IN
719: is_err_passive => is_err_passive, -- IN
720: is_bus_off => is_bus_off, -- IN
721: decrement_rec => decrement_rec, -- OUT
722:
723: -- Other control signals
724: sp_control => sp_control, -- OUT
725: sp_control_q => sp_control_q, -- OUT
726: nbt_ctrs_en => nbt_ctrs_en, -- OUT
727: dbt_ctrs_en => dbt_ctrs_en, -- OUT
728: sync_control => sync_control, -- OUT
729: ssp_reset => ssp_reset, -- OUT
730: tran_delay_meas => tran_delay_meas, -- OUT
731: tran_valid => tran_valid, -- OUT
732: crc_enable => crc_enable, -- OUT
733: crc_spec_enable => crc_spec_enable, -- OUT
734: crc_calc_from_rx => crc_calc_from_rx, -- OUT
735: load_init_vect => load_init_vect, -- OUT
736: bit_err_enable => bit_err_enable, -- OUT
737: br_shifted => br_shifted, -- OUT
738: btmc_reset => btmc_reset, -- OUT
739: dbt_measure_start => dbt_measure_start, -- OUT
740: gen_first_ssp => gen_first_ssp, -- OUT
741: sync_edge => sync_edge -- IN
742: );
743:
744: -----------------------------------------------------------------------------------------------
745: -- Control counter
746: -----------------------------------------------------------------------------------------------
747: i_mac_pc_control_counter : entity ctu_can_fd_rtl.mac_pc_control_counter
748: generic map(
749: G_CTRL_CTR_WIDTH => G_CTRL_CTR_WIDTH
750: )
751: port map(
752: clk_sys => clk_sys, -- IN
753: rst_n => rst_n, -- IN
754:
755: -- Control signals
756: rx_trigger => rx_trigger, -- IN
757: ctrl_ctr_ena => ctrl_ctr_ena, -- IN
758: ctrl_ctr_pload => ctrl_ctr_pload, -- IN
759: ctrl_ctr_pload_val => ctrl_ctr_pload_val, -- IN
760: compl_ctr_ena => compl_ctr_ena, -- IN
761: arbitration_lost => arbitration_lost_i, -- IN
762: arbitration_part => arbitration_part, -- IN
763:
764: -- Status signals
765: ctrl_ctr_zero => ctrl_ctr_zero, -- OUT
766: ctrl_ctr_one => ctrl_ctr_one, -- OUT
767: ctrl_counted_byte => ctrl_counted_byte, -- OUT
768: ctrl_counted_byte_index => ctrl_counted_byte_index, -- OUT
769: ctrl_ctr_mem_index => ctrl_ctr_mem_index, -- OUT
770:
771: -- Memory registers interface
772: alc_alc_bit => alc_alc_bit, -- OUT
773: alc_alc_id_field => alc_alc_id_field -- OUT
774: );
775:
776: -----------------------------------------------------------------------------------------------
777: -- Reintegration counter
778: -----------------------------------------------------------------------------------------------
779: i_mac_pc_reintegration_counter : entity ctu_can_fd_rtl.mac_pc_reintegration_counter
780: port map(
781: clk_sys => clk_sys, -- IN
782: rst_n => rst_n, -- IN
783:
784: -- Control signals
785: reinteg_ctr_clr => reinteg_ctr_clr, -- IN
786: reinteg_ctr_enable => reinteg_ctr_enable, -- IN
787: rx_trigger => rx_trigger, -- IN
788:
789: -- Status signals
790: reinteg_ctr_expired => reinteg_ctr_expired -- OUT
791: );
792:
793: -----------------------------------------------------------------------------------------------
794: -- Retransmitt counter
795: -----------------------------------------------------------------------------------------------
796: i_mac_pc_retransmitt_counter : entity ctu_can_fd_rtl.mac_pc_retransmitt_counter
797: generic map(
798: G_RETR_LIM_CTR_WIDTH => G_RETR_LIM_CTR_WIDTH
799: )
800: port map(
801: clk_sys => clk_sys, -- IN
802: rst_n => rst_n, -- IN
803:
804: -- Control signals
805: txtb_changed => txtb_changed, -- IN
806: retr_ctr_clear => retr_ctr_clear, -- IN
807: retr_ctr_add => retr_ctr_add, -- IN
808:
809: -- Memory registers interface
810: mr_settings_rtrth => mr_settings_rtrth, -- IN
811:
812: -- Status signals
813: retr_limit_reached => retr_limit_reached, -- OUT
814: retr_ctr => retr_ctr -- OUT
815: );
816:
817: -----------------------------------------------------------------------------------------------
818: -- Error detector
819: -----------------------------------------------------------------------------------------------
820: i_mac_pc_err_detector : entity ctu_can_fd_rtl.mac_pc_err_detector
821: port map(
822: clk_sys => clk_sys, -- IN
823: rst_n => rst_n, -- IN
824:
825: -- Data-path interface
826: tx_data => tx_data_wbs, -- IN
827: rx_data => rx_data_nbs, -- IN
828:
829: -- Error sources
830: bit_err => bit_err, -- IN
831: bit_err_arb => bit_err_arb, -- IN
832: stuff_err => stuff_err, -- IN
833: form_err => form_err_i, -- IN
834: ack_err => ack_err_i, -- IN
835: crc_err => crc_err_i, -- IN
836: tran_frame_parity_error => tran_frame_parity_error, -- IN
837:
838: -- Memory registers interface
839: mr_settings_nisofd => mr_settings_nisofd, -- IN
840: err_capt_err_type => err_capt_err_type, -- OUT
841: err_capt_err_pos => err_capt_err_pos, -- OUT
842: err_capt_err_erp => err_capt_err_erp, -- OUT
843:
844: -- CRC comparison data
845: rx_crc => rx_crc, -- IN
846: crc_15 => crc_15, -- IN
847: crc_17 => crc_17, -- IN
848: crc_21 => crc_21, -- IN
849: rx_stuff_count => rx_stuff_count, -- IN
850: dst_ctr => dst_ctr, -- IN
851:
852: -- Control signals
853: fixed_stuff => fixed_stuff_i, -- IN
854: err_pos => err_pos, -- IN
855: crc_check => crc_check, -- IN
856: crc_clear_match_flag => crc_clear_match_flag, -- IN
857: crc_src => crc_src, -- IN
858: is_arbitration => pc_dbg_i.is_arbitration, -- IN
859: is_transmitter => is_transmitter, -- IN
860: is_err_passive => is_err_passive, -- IN
861:
862: -- Status output
863: err_frm_req => err_frm_req, -- OUT
864: err_detected => err_detected, -- OUT
865: crc_match => crc_match, -- OUT
866: err_ctrs_unchanged => err_ctrs_unchanged -- OUT
867: );
868:
869: -----------------------------------------------------------------------------------------------
870: -- TX Shift register
871: -----------------------------------------------------------------------------------------------
872: i_mac_pc_tx_shift_reg : entity ctu_can_fd_rtl.mac_pc_tx_shift_reg
873: port map(
874: clk_sys => clk_sys, -- IN
875: rst_n => rst_n, -- IN
876:
877: mr_mode_tstm => mr_mode_tstm, -- IN
878:
879: tx_trigger => tx_trigger, -- IN
880: tx_data_nbs => tx_data_nbs, -- OUT
881:
882: -- Protocol control FSM interface
883: tx_load_base_id => tx_load_base_id, -- IN
884: tx_load_ext_id => tx_load_ext_id, -- IN
885: tx_load_dlc => tx_load_dlc, -- IN
886: tx_load_data_word => tx_load_data_word, -- IN
887: tx_load_stuff_count => tx_load_stuff_count, -- IN
888: tx_load_crc => tx_load_crc, -- IN
889: tx_shift_ena => tx_shift_ena, -- IN
890: tx_dominant => tx_dominant, -- IN
891: crc_src => crc_src, -- IN
892:
893: -- CAN CRC Interface
894: crc_15 => crc_15, -- IN
895: crc_17 => crc_17, -- IN
896: crc_21 => crc_21, -- IN
897:
898: err_frm_req => err_frm_req, -- IN
899: is_err_active => is_err_active, -- IN
900: bst_ctr => bst_ctr, -- IN
901: tran_identifier => tran_identifier, -- IN
902: tran_frame_test => tran_frame_test, -- IN
903: tran_word => tran_word, -- IN
904: tran_dlc => tran_dlc -- IN
905: );
906:
907: -----------------------------------------------------------------------------------------------
908: -- RX Shift register
909: -----------------------------------------------------------------------------------------------
910: i_mac_pc_rx_shift_reg : entity ctu_can_fd_rtl.mac_pc_rx_shift_reg
911: port map(
912: clk_sys => clk_sys, -- IN
913: rst_n => rst_n, -- IN
914:
915: -- DFT support
916: scan_mode => scan_mode, -- IN
917:
918: rx_trigger => rx_trigger, -- IN
919:
920: -- Data-path interface
921: rx_data_nbs => rx_data_nbs, -- IN
922:
923: -- Protocol control FSM interface
924: rx_clear => rx_clear, -- IN
925: rx_shift_ena => rx_shift_ena, -- IN
926: rx_shift_in_sel => rx_shift_in_sel, -- IN
927: rx_store_base_id => rx_store_base_id, -- IN
928: rx_store_ext_id => rx_store_ext_id, -- IN
929: rx_store_ide => rx_store_ide, -- IN
930: rx_store_rtr => rx_store_rtr, -- IN
931: rx_store_edl => rx_store_edl, -- IN
932: rx_store_dlc => rx_store_dlc, -- IN
933: rx_store_esi => rx_store_esi, -- IN
934: rx_store_brs => rx_store_brs, -- IN
935: rx_store_stuff_count => rx_store_stuff_count, -- IN
936:
937: -- RX Buffer interface
938: rec_ident => rec_ident, -- OUT
939: rec_dlc_d => rec_dlc_d, -- OUT
940: rec_dlc => rec_dlc_q, -- OUT
941: rec_is_rtr => rec_is_rtr_i, -- OUT
942: rec_ident_type => rec_ident_type, -- OUT
943: rec_frame_type => rec_frame_type_i, -- OUT
944: rec_brs => rec_brs, -- OUT
945: rec_esi => rec_esi, -- OUT
946: store_data_word => store_data_word, -- OUT
947:
948: -- CRC information for CRC comparison
949: rx_crc => rx_crc, -- OUT
950: rx_stuff_count => rx_stuff_count -- OUT
951: );
952:
953: -----------------------------------------------------------------------------------------------
954: -- Internal signals propagation to output
955: -----------------------------------------------------------------------------------------------
956: rec_frame_type <= rec_frame_type_i;
957: rec_is_rtr <= rec_is_rtr_i;
958: rec_dlc <= rec_dlc_q;
959: form_err <= form_err_i;
960: ack_err <= ack_err_i;
961: crc_err <= crc_err_i;
962: fixed_stuff <= fixed_stuff_i;
963: arbitration_lost <= arbitration_lost_i;
964: pc_dbg <= pc_dbg_i;
965:
966:
967: -- <RELEASE_OFF>
968: -----------------------------------------------------------------------------------------------
969: -- Assertions
970: -----------------------------------------------------------------------------------------------
971: -- psl default clock is rising_edge(clk_sys);
972:
973: -- psl no_invalid_ack_err_asrt : assert never
974: -- ((ack_err = '1' or crc_err = '1' or stuff_err = '1') and (pc_dbg_i.is_err = '1'))
975: -- report "ACK, Stuff, CRC Errors can't occur during Error or overload flag";
976:
977: -- psl sample_sec_proper_asrt : assert never
978: -- (sp_control = SECONDARY_SAMPLE and is_transmitter = '0')
979: -- report "Secondary sampling is allowed only for transmitter!";
980:
981: -- psl no_simul_tx_rx_trigger_asrt : assert never
982: -- (tx_trigger = '1' and rx_trigger = '1')
983: -- report "RX Trigger and TX Trigger can't be active at once!";
984:
985: -- psl no_simul_transmitter_receiver_asrt : assert never
986: -- (is_transmitter = '1' and is_receiver = '1')
987: -- report "Unit can't be transmitter and receiver simultaneously!";
988:
989: -- psl no_h_sync_in_data_bit_rate_asrt : assert always
990: -- (sync_control = HARD_SYNC) -> (sp_control = NOMINAL_SAMPLE)
991: -- report "Hard synchronisation shall be used in Nominal bit rate only!";
992:
993: -- psl no_simul_err_req_asrt : assert never
994: -- (tran_valid = '1' and err_frm_req = '1')
995: -- report "Tranmission OK and Error frame request can't occur at once!";
996:
997: -- <RELEASE_ON>
998:
999: end architecture;