NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_tx_shift_reg.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_TX_SHIFT_REG.I_TX_SHIFT_REG	100.0 % (7/7)	100.0 % (8/8)	100.0 % (202/202)	100.0 % (6/6)	N.A.	N.A.	100.0 % (223/223)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_TX_SHIFT_REG.I_TX_SHIFT_REG

100.0 % (7/7)

100.0 % (8/8)

100.0 % (202/202)

100.0 % (6/6)

N.A.

100.0 % (223/223)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 129:

129: reg_output <= shift_regs(G_WIDTH - 1);
Count: 1052453
Threshold: 1

If statement on lines 136 to 145:

136:        if (rst_n = G_RESET_POLARITY) then 
137:            shift_regs <= G_RESET_VALUE; 
...
144:            end if; 
145:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 137:

137: shift_regs <= G_RESET_VALUE;
Count: 2422674
Threshold: 1

If statement on lines 140 to 144:

140:            if (preload = '1') then 
141:                shift_regs <= preload_val; 
142:            elsif (enable = '1') then 
143:                shift_regs <= shift_regs(G_WIDTH - 2 downto 0) & '0'; 
144:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 141:

141: shift_regs <= preload_val;
Count: 316701
Threshold: 1

Signal assignment statement on line 143:

143: shift_regs <= shift_regs(G_WIDTH - 2 downto 0) & '0';
Count: 2356473
Threshold: 1

Signal assignment statement on line 151:

151: reg_stat <= shift_regs;
Count: 2289612
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 136:

136: if (rst_n = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 139:

139: elsif (rising_edge(clk)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 140:

140: if (preload = '1') then

	Evaluated to	Count	Threshold
Bin	True	316701	1
Bin	False	546857633	1

"if" / "when" / "else" condition on line 142:

142: elsif (enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	2356473	1
Bin	False	544501160	1

Uncovered toggles:

Excluded toggles:

Port:

CLK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRELOAD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRELOAD_VAL

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

REG_STAT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	524626	1
Bin	(31)	1	0	526226	1
Bin	(30)	0	1	501242	1
Bin	(30)	1	0	502841	1
Bin	(29)	0	1	476270	1
Bin	(29)	1	0	477868	1
Bin	(28)	0	1	451529	1
Bin	(28)	1	0	453127	1
Bin	(27)	0	1	410628	1
Bin	(27)	1	0	412227	1
Bin	(26)	0	1	393774	1
Bin	(26)	1	0	395373	1
Bin	(25)	0	1	368795	1
Bin	(25)	1	0	370393	1
Bin	(24)	0	1	351332	1
Bin	(24)	1	0	352931	1
Bin	(23)	0	1	327660	1
Bin	(23)	1	0	329260	1
Bin	(22)	0	1	310700	1
Bin	(22)	1	0	312301	1
Bin	(21)	0	1	286959	1
Bin	(21)	1	0	288558	1
Bin	(20)	0	1	261046	1
Bin	(20)	1	0	262645	1
Bin	(19)	0	1	244874	1
Bin	(19)	1	0	246474	1
Bin	(18)	0	1	232731	1
Bin	(18)	1	0	234330	1
Bin	(17)	0	1	215271	1
Bin	(17)	1	0	216869	1
Bin	(16)	0	1	194900	1
Bin	(16)	1	0	196501	1
Bin	(15)	0	1	180140	1
Bin	(15)	1	0	181739	1
Bin	(14)	0	1	164448	1
Bin	(14)	1	0	166049	1
Bin	(13)	0	1	149980	1
Bin	(13)	1	0	151581	1
Bin	(12)	0	1	140862	1
Bin	(12)	1	0	142463	1
Bin	(11)	0	1	130768	1
Bin	(11)	1	0	132369	1
Bin	(10)	0	1	121765	1
Bin	(10)	1	0	123366	1
Bin	(9)	0	1	110919	1
Bin	(9)	1	0	112520	1
Bin	(8)	0	1	101713	1
Bin	(8)	1	0	103314	1
Bin	(7)	0	1	91302	1
Bin	(7)	1	0	92903	1
Bin	(6)	0	1	82421	1
Bin	(6)	1	0	84022	1
Bin	(5)	0	1	71509	1
Bin	(5)	1	0	73110	1
Bin	(4)	0	1	63369	1
Bin	(4)	1	0	64970	1
Bin	(3)	0	1	52815	1
Bin	(3)	1	0	54416	1
Bin	(2)	0	1	44574	1
Bin	(2)	1	0	46175	1
Bin	(1)	0	1	34622	1
Bin	(1)	1	0	36223	1
Bin	(0)	0	1	26427	1
Bin	(0)	1	0	28028	1

Port:

REG_OUTPUT

	From	To	Count	Threshold
Bin	0	1	524626	1
Bin	1	0	526226	1

Signal:

SHIFT_REGS

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1136443	1
Bin	(31)	1	0	1151568	1
Bin	(30)	0	1	501242	1
Bin	(30)	1	0	625258	1
Bin	(29)	0	1	476270	1
Bin	(29)	1	0	478381	1
Bin	(28)	0	1	451529	1
Bin	(28)	1	0	453618	1
Bin	(27)	0	1	410628	1
Bin	(27)	1	0	412698	1
Bin	(26)	0	1	393774	1
Bin	(26)	1	0	395824	1
Bin	(25)	0	1	368795	1
Bin	(25)	1	0	370832	1
Bin	(24)	0	1	351332	1
Bin	(24)	1	0	353346	1
Bin	(23)	0	1	327660	1
Bin	(23)	1	0	329656	1
Bin	(22)	0	1	310700	1
Bin	(22)	1	0	312681	1
Bin	(21)	0	1	286959	1
Bin	(21)	1	0	288923	1
Bin	(20)	0	1	261046	1
Bin	(20)	1	0	262994	1
Bin	(19)	0	1	244874	1
Bin	(19)	1	0	246799	1
Bin	(18)	0	1	232731	1
Bin	(18)	1	0	234630	1
Bin	(17)	0	1	215271	1
Bin	(17)	1	0	217145	1
Bin	(16)	0	1	194900	1
Bin	(16)	1	0	196757	1
Bin	(15)	0	1	180140	1
Bin	(15)	1	0	181977	1
Bin	(14)	0	1	164448	1
Bin	(14)	1	0	166270	1
Bin	(13)	0	1	149980	1
Bin	(13)	1	0	151784	1
Bin	(12)	0	1	140862	1
Bin	(12)	1	0	142662	1
Bin	(11)	0	1	130768	1
Bin	(11)	1	0	132561	1
Bin	(10)	0	1	121765	1
Bin	(10)	1	0	123545	1
Bin	(9)	0	1	110919	1
Bin	(9)	1	0	112690	1
Bin	(8)	0	1	101713	1
Bin	(8)	1	0	103476	1
Bin	(7)	0	1	91302	1
Bin	(7)	1	0	93054	1
Bin	(6)	0	1	82421	1
Bin	(6)	1	0	84157	1
Bin	(5)	0	1	71509	1
Bin	(5)	1	0	73223	1
Bin	(4)	0	1	63369	1
Bin	(4)	1	0	65072	1
Bin	(3)	0	1	52815	1
Bin	(3)	1	0	54509	1
Bin	(2)	0	1	44574	1
Bin	(2)	1	0	46259	1
Bin	(1)	0	1	34622	1
Bin	(1)	1	0	36289	1
Bin	(0)	0	1	26427	1
Bin	(0)	1	0	28075	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 136:

rst_n = G_RESET_POLARITY

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 140:

preload = '1'

	Evaluated to	Count	Threshold
Bin	False	546857633	1
Bin	True	316701	1

"=" expression on line 142:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	544501160	1
Bin	True	2356473	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_TX_SHIFT_REG.I_TX_SHIFT_REG

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_tx_shift_reg.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 129:

If statement on lines 136 to 145:

Signal assignment statement on line 137:

If statement on lines 140 to 144:

Signal assignment statement on line 141:

Signal assignment statement on line 143:

Signal assignment statement on line 151:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 136:

"if" / "when" / "else" condition on line 139:

"if" / "when" / "else" condition on line 140:

"if" / "when" / "else" condition on line 142:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 136:

"=" expression on line 140:

"=" expression on line 142:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: