File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_tx_shift_reg.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- TX Shift register
71: --
72: -- Purpose:
73: -- Creates TX Serial data stream in multi-bit fields on CAN bus. Controlled
74: -- by Protocol control FSM. Preloaded in "Process" pipeline stage. Shifted in
75: -- "Stuff" pipeline stage. Single bit fields are transmitted via forcing the
76: -- TX output by Protocol control FSM to Dominant value.
77: --------------------------------------------------------------------------------
78:
79: Library ieee;
80: use ieee.std_logic_1164.all;
81: use ieee.numeric_std.ALL;
82:
83: Library ctu_can_fd_rtl;
84: use ctu_can_fd_rtl.can_constants_pkg.all;
85: use ctu_can_fd_rtl.can_types_pkg.all;
86:
87: use ctu_can_fd_rtl.CAN_FD_register_map.all;
88: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
89:
90: entity mac_pc_tx_shift_reg is
91: port (
92: -------------------------------------------------------------------------------------------
93: -- Clock and Asynchronous Reset
94: -------------------------------------------------------------------------------------------
95: clk_sys : in std_logic;
96: rst_n : in std_logic;
97:
98: -------------------------------------------------------------------------------------------
99: -- Memory registers interface
100: -------------------------------------------------------------------------------------------
101: mr_mode_tstm : in std_logic;
102:
103: -------------------------------------------------------------------------------------------
104: -- Trigger signals
105: -------------------------------------------------------------------------------------------
106: -- RX Trigger
107: tx_trigger : in std_logic;
108:
109: -------------------------------------------------------------------------------------------
110: -- Data-path interface
111: -------------------------------------------------------------------------------------------
112: -- Actual TX Data (no bit stuffing)
113: tx_data_nbs : out std_logic;
114:
115: -------------------------------------------------------------------------------------------
116: -- Protocol control FSM interface
117: -------------------------------------------------------------------------------------------
118: -- Load Base Identifier to TX Shift register
119: tx_load_base_id : in std_logic;
120:
121: -- Load extended Identifier to TX Shift register
122: tx_load_ext_id : in std_logic;
123:
124: -- Load DLC to TX Shift register
125: tx_load_dlc : in std_logic;
126:
127: -- Load Data word to TX Shift register
128: tx_load_data_word : in std_logic;
129:
130: -- Load Stuff count
131: tx_load_stuff_count : in std_logic;
132:
133: -- Load CRC to TX Shift register
134: tx_load_crc : in std_logic;
135:
136: -- Shift register enable (shifts with TX Trigger)
137: tx_shift_ena : in std_logic;
138:
139: -- Force Dominant value instead of value from shift register
140: tx_dominant : in std_logic;
141:
142: -- CRC Source (CRC15, CRC17, CRC21)
143: crc_src : in std_logic_vector(1 downto 0);
144:
145: -------------------------------------------------------------------------------------------
146: -- CAN CRC Interface
147: -------------------------------------------------------------------------------------------
148: -- Calculated CRC 15
149: crc_15 : in std_logic_vector(14 downto 0);
150:
151: -- Calculated CRC 17
152: crc_17 : in std_logic_vector(16 downto 0);
153:
154: -- Calculated CRC 21
155: crc_21 : in std_logic_vector(20 downto 0);
156:
157: -------------------------------------------------------------------------------------------
158: -- Error detector Interface
159: -------------------------------------------------------------------------------------------
160: -- Error frame request
161: err_frm_req : in std_logic;
162:
163: -------------------------------------------------------------------------------------------
164: -- Fault confinement Interface
165: -------------------------------------------------------------------------------------------
166: -- Unit is error active
167: is_err_active : in std_logic;
168:
169: -------------------------------------------------------------------------------------------
170: -- Bit Stuffing / Destuffing Interface
171: -------------------------------------------------------------------------------------------
172: -- Stuff counter modulo 8
173: bst_ctr : in std_logic_vector(2 downto 0);
174:
175: -------------------------------------------------------------------------------------------
176: -- TXT Buffers interface
177: -------------------------------------------------------------------------------------------
178: -- TX Identifier
179: tran_identifier : in std_logic_vector(28 downto 0);
180:
181: -- TX Frame test
182: tran_frame_test : in t_frame_test_w;
183:
184: -- TXT Buffer RAM word
185: tran_word : in std_logic_vector(31 downto 0);
186:
187: -- TX Data length code
188: tran_dlc : in std_logic_vector(3 downto 0)
189: );
190: end entity;
191:
192: architecture rtl of mac_pc_tx_shift_reg is
193:
194: -- Shift register output
195: signal tx_sr_output : std_logic;
196:
197: -- Shift register clock enable
198: signal tx_sr_ce : std_logic;
199:
200: -- Shift register preload
201: signal tx_sr_pload : std_logic;
202: signal tx_sr_pload_val : std_logic_vector(31 downto 0);
203:
204: -- ID Loaded from TXT Buffer RAM
205: signal tx_base_id : std_logic_vector(10 downto 0);
206: signal tx_ext_id : std_logic_vector(17 downto 0);
207:
208: -- Selected CRC to be transmitted
209: signal tx_crc : std_logic_vector(20 downto 0);
210:
211: -- CRC with some bit flipped
212: signal tx_crc_flipped : std_logic_vector(20 downto 0);
213:
214: -- Stuff counter (grey coded)
215: signal bst_ctr_grey : std_logic_vector(2 downto 0);
216: signal bst_parity : std_logic;
217: signal stuff_count : std_logic_vector(3 downto 0);
218:
219: constant C_RX_SHIFT_REG_RST_VAL : std_logic_vector(31 downto 0) := (others => '0');
220:
221: -- TX Frame corruption / bit flips
222: signal flip_mask : std_logic_vector(20 downto 0);
223:
224: -- Stuff count field with single bit flipped
225: signal stuff_count_flipped : std_logic_vector(3 downto 0);
226:
227: -- TX DLC swapped with FRAME_TEST_W[TPRM]
228: signal tran_dlc_swapped : std_logic_vector(3 downto 0);
229:
230: -- Transmitted word with endianity swapped
231: signal tran_word_swapped : std_logic_vector(31 downto 0);
232:
233: begin
234:
235: -- Tick shift register in Sync (TX Trigger)!
236: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')
237: else
238: '0';
239:
240: -- Shift register pre-load
241: tx_sr_pload <= '1' when (tx_load_base_id = '1' or
242: tx_load_ext_id = '1' or
243: tx_load_dlc = '1' or
244: tx_load_data_word = '1' or
245: tx_load_stuff_count = '1' or
246: tx_load_crc = '1')
247: else
248: '0';
249:
250: -- CRC to be transmitted
251: tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else
252: crc_17 & "0000" when (crc_src = C_CRC17_SRC) else
253: crc_21;
254:
255: -- Stuff counter grey coding
256: with bst_ctr select bst_ctr_grey <=
257: "001" when "001",
258: "011" when "010",
259: "010" when "011",
260: "110" when "100",
261: "111" when "101",
262: "101" when "110",
263: "100" when "111",
264: "000" when others;
265:
266: bst_parity <= bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2);
267:
268: stuff_count <= bst_ctr_grey & bst_parity;
269:
270: -- Choosing Base and Ext IDs from TXT Buffer RAM memory words!
271: tx_base_id <= tran_identifier(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
272: tx_ext_id <= tran_identifier(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
273:
274: tran_word_swapped <= tran_word(7 downto 0) & tran_word(15 downto 8) &
275: tran_word(23 downto 16) & tran_word(31 downto 24);
276:
277: -----------------------------------------------------------------------------------------------
278: -- Corruption features for transmitted frames
279: -----------------------------------------------------------------------------------------------
280: p_flip_mask_compute : process(tran_frame_test, mr_mode_tstm)
281: begin
282: flip_mask <= (others => '0');
283: if (mr_mode_tstm = '1') then
284: flip_mask(20 - to_integer(unsigned(tran_frame_test.tprm))) <= '1';
285: end if;
286: end process;
287:
288: -- Flip a bit in CRC on TPRM index
289: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')
290: else
291: tx_crc;
292:
293: -- Flip bit of Stuff count on TPRM index
294: stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')
295: else
296: stuff_count;
297:
298: -- Swap transmitted DLC with arbtirary value
299: tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and
300: mr_mode_tstm = '1')
301: else
302: tran_dlc;
303:
304: -----------------------------------------------------------------------------------------------
305: -- Shift register pre-load value:
306: -- 1. Base ID is loaded from TXT Buffer memory.
307: -- 2. Extended ID is loaded from TXT Buffer memory;
308: -- 3. DLC is loaded from Output of TX Arbitrator.
309: -- 4. TXT Buffer word is loaded from TXT Buffer memory.
310: -- 5. Calculated CRC is loaded from output of CAN CRC.
311: -----------------------------------------------------------------------------------------------
312: tx_sr_pload_val <=
313: tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else
314: tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else
315: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else
316: tran_word_swapped when (tx_load_data_word = '1') else
317: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else
318: tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else
319: (others => '0');
320:
321: -----------------------------------------------------------------------------------------------
322: -- TX Shift register instance
323: -----------------------------------------------------------------------------------------------
324: i_tx_shift_reg : entity ctu_can_fd_rtl.shift_reg_preload
325: generic map (
326: G_RESET_POLARITY => '0',
327: G_RESET_VALUE => C_RX_SHIFT_REG_RST_VAL,
328: G_WIDTH => 32
329: )
330: port map (
331: clk => clk_sys, -- IN
332: rst_n => rst_n, -- IN
333: preload => tx_sr_pload, -- IN
334: preload_val => tx_sr_pload_val, -- IN
335: enable => tx_sr_ce, -- IN
336:
337: reg_stat => open, -- OUT
338: reg_output => tx_sr_output -- OUT
339: );
340:
341: -----------------------------------------------------------------------------------------------
342: -- Calculation of next data bit value!
343: -----------------------------------------------------------------------------------------------
344: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else
345: RECESSIVE when (err_frm_req = '1') else
346: DOMINANT when (tx_dominant = '1') else
347: tx_sr_output when (tx_shift_ena = '1') else
348: RECESSIVE;
349:
350: -----------------------------------------------------------------------------------------------
351: -- Assertions
352: -----------------------------------------------------------------------------------------------
353:
354: -- psl default clock is rising_edge(clk_sys);
355:
356: -- psl no_sim_tx_shift_reg_load_1_asrt : assert never
357: -- (tx_load_base_id = '1' and
358: -- (tx_load_ext_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1'
359: -- or tx_load_stuff_count = '1' or tx_load_crc = '1'))
360: -- report "TX SHIFT REG: Base Identifier shall not be loaded simultaneously with other data!";
361:
362: -- psl no_sim_tx_shift_reg_load_2_asrt : assert never
363: -- (tx_load_ext_id = '1' and
364: -- (tx_load_base_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1'
365: -- or tx_load_stuff_count = '1' or tx_load_crc = '1'))
366: -- report "TX SHIFT REG: Extended Identifier shall not be loaded simultaneously with other data!";
367:
368: -- psl no_sim_tx_shift_reg_load_3_asrt : assert never
369: -- (tx_load_dlc = '1' and
370: -- (tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_data_word = '1'
371: -- or tx_load_stuff_count = '1' or tx_load_crc = '1'))
372: -- report "TX SHIFT REG: DLC shall not be loaded simultaneously with other data!";
373:
374: -- psl no_sim_tx_shift_reg_load_4_asrt : assert never
375: -- (tx_load_data_word = '1' and
376: -- (tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1'
377: -- or tx_load_stuff_count = '1' or tx_load_crc = '1'))
378: -- report "TX SHIFT REG: DLC shall not be loaded simultaneously with other data!";
379:
380: -- psl no_sim_tx_shift_reg_load_5_asrt : assert never
381: -- (tx_load_stuff_count = '1' and
382: -- (tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1'
383: -- or tx_load_data_word = '1' or tx_load_crc = '1'))
384: -- report "TX SHIFT REG: Stuff count shall not be loaded simultaneously with other data!";
385:
386: -- psl no_sim_tx_shift_reg_load_6_asrt : assert never
387: -- (tx_load_crc = '1' and
388: -- (tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1'
389: -- or tx_load_data_word = '1' or tx_load_stuff_count = '1'))
390: -- report "TX SHIFT REG: CRC shall not be loaded simultaneously with other data!";
391:
392: end architecture;