NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_DATA_EDGE_DETECTOR	100.0 % (19/19)	100.0 % (12/12)	100.0 % (28/28)	100.0 % (35/35)	N.A.	N.A.	100.0 % (94/94)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_DATA_EDGE_DETECTOR

100.0 % (19/19)

100.0 % (12/12)

100.0 % (28/28)

100.0 % (35/35)

N.A.

100.0 % (94/94)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 161 to 172:

161:        if (rst_n = '0') then 
162:            rx_data_prev        <= RECESSIVE; 
...
171:            end if; 
172:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 162:

162: rx_data_prev <= RECESSIVE;
Count: 2422674
Threshold: 1

Signal assignment statement on line 163:

163: tx_data_prev <= RECESSIVE;
Count: 2422674
Threshold: 1

Signal assignment statement on line 164:

164: rx_data_sync_prev <= RECESSIVE;
Count: 2422674
Threshold: 1

Signal assignment statement on line 166:

166: rx_data_prev <= rx_data;
Count: 547174334
Threshold: 1

Signal assignment statement on line 167:

167: tx_data_prev <= tx_data;
Count: 547174334
Threshold: 1

If statement on lines 169 to 171:

169:            if (tq_edge = '1') then 
170:                rx_data_sync_prev <= rx_data; 
171:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 170:

170: rx_data_sync_prev <= rx_data;
Count: 345459013
Threshold: 1

If statement on lines 180 to 182:

180:    tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE) 
181:                     else 
182:                 '0';

Count: 2552323
Threshold: 1

Signal assignment statement on line 180:

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)
Count: 638509
Threshold: 1

Signal assignment statement on line 182:

182: '0';
Count: 1913814
Threshold: 1

If statement on lines 189 to 191:

189:    rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE) 
190:                     else 
191:                 '0';

Count: 5633104
Threshold: 1

Signal assignment statement on line 189:

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)
Count: 1408291
Threshold: 1

Signal assignment statement on line 191:

191: '0';
Count: 4224813
Threshold: 1

If statement on lines 201 to 206:

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and 
204:                          (tq_edge = '1') 
205:                     else 
206:                 '0';

Count: 231705269
Threshold: 1

Signal assignment statement on line 201:

201: sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and
Count: 1562664
Threshold: 1

Signal assignment statement on line 206:

206: '0';
Count: 230142605
Threshold: 1

Signal assignment statement on line 211:

211: rx_edge <= rx_edge_i;
Count: 2819784
Threshold: 1

Signal assignment statement on line 212:

212: tx_edge <= tx_edge_i;
Count: 1280220
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 161:

161: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 165:

165: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 169:

169: if (tq_edge = '1') then

	Evaluated to	Count	Threshold
Bin	True	345459013	1
Bin	False	201715321	1

"if" / "when" / "else" condition on line 180:

180: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	True	638509	1
Bin	False	1913814	1

"if" / "when" / "else" condition on line 189:

189: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)

	Evaluated to	Count	Threshold
Bin	True	1408291	1
Bin	False	4224813	1

"if" / "when" / "else" condition on lines 201 to 204:

201:    sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and 
202:                          (rx_data_sync_prev = RECESSIVE) and 
203:                          (prev_rx_sample /= rx_data) and 
204:                          (tq_edge = '1')

	Evaluated to	Count	Threshold
Bin	True	1562664	1
Bin	False	230142605	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_DATA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_DATA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PREV_RX_SAMPLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TQ_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TX_EDGE

	From	To	Count	Threshold
Bin	0	1	638509	1
Bin	1	0	640110	1

Port:

RX_EDGE

	From	To	Count	Threshold
Bin	0	1	1408291	1
Bin	1	0	1409892	1

Port:

SYNC_EDGE

	From	To	Count	Threshold
Bin	0	1	1562664	1
Bin	1	0	1564265	1

Signal:

RX_DATA_PREV

	From	To	Count	Threshold
Bin	0	1	1409892	1
Bin	1	0	1408291	1

Signal:

TX_DATA_PREV

	From	To	Count	Threshold
Bin	0	1	638480	1
Bin	1	0	636881	1

Signal:

RX_DATA_SYNC_PREV

	From	To	Count	Threshold
Bin	0	1	1408383	1
Bin	1	0	1406782	1

Signal:

RX_EDGE_I

	From	To	Count	Threshold
Bin	0	1	1408291	1
Bin	1	0	1409892	1

Signal:

TX_EDGE_I

	From	To	Count	Threshold
Bin	0	1	638509	1
Bin	1	0	640110	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 161:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 169:

tq_edge = '1'

	Evaluated to	Count	Threshold
Bin	False	201715321	1
Bin	True	345459013	1

"and" expression on line 180:

 (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE) 
  <---------LHS--------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	638480	1
Bin	True	False	636852	1
Bin	True	True	638509	1

"/=" expression on line 180:

tx_data_prev /= tx_data

	Evaluated to	Count	Threshold
Bin	False	1276962	1
Bin	True	1275361	1

"=" expression on line 180:

tx_data_prev = RECESSIVE

	Evaluated to	Count	Threshold
Bin	False	1275334	1
Bin	True	1276989	1

"and" expression on line 189:

 (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE) 
  <---------LHS--------->       <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	1407947	1
Bin	True	False	1408240	1
Bin	True	True	1408291	1

"/=" expression on line 189:

rx_data_prev /= rx_data

	Evaluated to	Count	Threshold
Bin	False	2816573	1
Bin	True	2816531	1

"=" expression on line 189:

rx_data_prev = RECESSIVE

	Evaluated to	Count	Threshold
Bin	False	2816866	1
Bin	True	2816238	1

"and" expression on lines 201 to 204:

 (rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) and (prev_rx_sample /= rx_data) and (tq_edge = '1') 
 <----------------------------------------------LHS----------------------------------------------->      <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	117834767	1
Bin	True	False	480731	1
Bin	True	True	1562664	1

"and" expression on lines 201 to 203:

 (rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) and (prev_rx_sample /= rx_data) 
 <------------------------------LHS------------------------------->      <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	38474996	1
Bin	True	False	6601	1
Bin	True	True	2043395	1

"and" expression on lines 201 to 202:

 (rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) 
  <-----------LHS------------>       <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	152514731	1
Bin	True	False	2054536	1
Bin	True	True	2049996	1

"/=" expression on line 201:

rx_data_sync_prev /= rx_data

	Evaluated to	Count	Threshold
Bin	False	227600737	1
Bin	True	4104532	1

"=" expression on line 202:

rx_data_sync_prev = RECESSIVE

	Evaluated to	Count	Threshold
Bin	False	77140542	1
Bin	True	154564727	1

"/=" expression on line 203:

prev_rx_sample /= rx_data

	Evaluated to	Count	Threshold
Bin	False	191186878	1
Bin	True	40518391	1

"=" expression on line 204:

tq_edge = '1'

	Evaluated to	Count	Threshold
Bin	False	112307838	1
Bin	True	119397431	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_DATA_EDGE_DETECTOR

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 161 to 172:

Signal assignment statement on line 162:

Signal assignment statement on line 163:

Signal assignment statement on line 164:

Signal assignment statement on line 166:

Signal assignment statement on line 167:

If statement on lines 169 to 171:

Signal assignment statement on line 170:

If statement on lines 180 to 182:

Signal assignment statement on line 180:

Signal assignment statement on line 182:

If statement on lines 189 to 191:

Signal assignment statement on line 189:

Signal assignment statement on line 191:

If statement on lines 201 to 206:

Signal assignment statement on line 201:

Signal assignment statement on line 206:

Signal assignment statement on line 211:

Signal assignment statement on line 212:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 161:

"if" / "when" / "else" condition on line 165:

"if" / "when" / "else" condition on line 169:

"if" / "when" / "else" condition on line 180:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on lines 201 to 204:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 161:

"=" expression on line 169:

"and" expression on line 180:

"/=" expression on line 180:

"=" expression on line 180:

"and" expression on line 189:

"/=" expression on line 189:

"=" expression on line 189:

"and" expression on lines 201 to 204:

"and" expression on lines 201 to 203:

"and" expression on lines 201 to 202:

"/=" expression on line 201:

"=" expression on line 202:

"/=" expression on line 203:

"=" expression on line 204:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: