NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_MAC_FC_FSM	100.0 % (47/47)	100.0 % (38/38)	100.0 % (100/100)	100.0 % (33/33)	100.0 % (6/6)	N.A.	100.0 % (224/224)
I_MAC_FC_ERR_COUNTERS	100.0 % (89/89)	100.0 % (76/76)	100.0 % (536/536)	100.0 % (116/116)	N.A.	N.A.	100.0 % (817/817)
I_MAC_FC_RULES	100.0 % (18/18)	100.0 % (16/16)	100.0 % (34/34)	98.4 % (65/66)	N.A.	N.A.	99.2 % (133/134)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_MAC_FC_FSM

100.0 % (47/47)

100.0 % (38/38)

100.0 % (100/100)

100.0 % (33/33)

100.0 % (6/6)

N.A.

100.0 % (224/224)

I_MAC_FC_ERR_COUNTERS

100.0 % (89/89)

100.0 % (76/76)

100.0 % (536/536)

100.0 % (116/116)

N.A.

100.0 % (817/817)

I_MAC_FC_RULES

100.0 % (18/18)

100.0 % (16/16)

100.0 % (34/34)

98.4 % (65/66)

N.A.

99.2 % (133/134)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP	100.0 % (2/2)	N.A.	100.0 % (246/246)	N.A.	N.A.	N.A.	100.0 % (248/248)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP

100.0 % (2/2)

N.A.

100.0 % (246/246)

N.A.

100.0 % (248/248)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 291:

291: tx_err_ctr <= tx_err_ctr_i;
Count: 33872
Threshold: 1

Signal assignment statement on line 292:

292: rx_err_ctr <= rx_err_ctr_i;
Count: 27275
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_EWL_EW_LIMIT

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_ERP_ERP_LIMIT

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_CTR_PRES_CTPV

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_CTR_PRES_PTX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_PRX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_ENORM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_EFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TRANSMITTER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_RECEIVER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SET_ERR_ACTIVE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DETECTED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_CTRS_UNCHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRIMARY_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ACT_ERR_OVR_FLAG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DELIM_LATE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DECREMENT_REC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_AFTER_ACK_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_STATUS_EWL

	From	To	Count	Threshold
Bin	0	1	780	1
Bin	1	0	2380	1

Port:

FCS_CHANGED

	From	To	Count	Threshold
Bin	0	1	15993	1
Bin	1	0	17594	1

Port:

ERR_WARNING_LIMIT_PULSE

	From	To	Count	Threshold
Bin	0	1	3160	1
Bin	1	0	4761	1

Port:

IS_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	8426	1
Bin	1	0	8415	1

Port:

IS_ERR_PASSIVE

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	2372	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8238	1

Port:

TX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	249	1
Bin	(8)	1	0	1850	1
Bin	(7)	0	1	517	1
Bin	(7)	1	0	2118	1
Bin	(6)	0	1	501	1
Bin	(6)	1	0	2102	1
Bin	(5)	0	1	805	1
Bin	(5)	1	0	2406	1
Bin	(4)	0	1	1933	1
Bin	(4)	1	0	3534	1
Bin	(3)	0	1	12743	1
Bin	(3)	1	0	14344	1
Bin	(2)	0	1	2955	1
Bin	(2)	1	0	4556	1
Bin	(1)	0	1	3324	1
Bin	(1)	1	0	4925	1
Bin	(0)	0	1	3524	1
Bin	(0)	1	0	5125	1

Port:

RX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	130	1
Bin	(8)	1	0	1731	1
Bin	(7)	0	1	350	1
Bin	(7)	1	0	1951	1
Bin	(6)	0	1	255	1
Bin	(6)	1	0	1854	1
Bin	(5)	0	1	363	1
Bin	(5)	1	0	1963	1
Bin	(4)	0	1	497	1
Bin	(4)	1	0	2098	1
Bin	(3)	0	1	685	1
Bin	(3)	1	0	2285	1
Bin	(2)	0	1	617	1
Bin	(2)	1	0	2218	1
Bin	(1)	0	1	1191	1
Bin	(1)	1	0	2792	1
Bin	(0)	0	1	11216	1
Bin	(0)	1	0	12809	1

Port:

NORM_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	1667	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	1668	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	1661	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	1664	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	1668	1
Bin	(9)	0	1	63	1
Bin	(9)	1	0	1662	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1671	1
Bin	(7)	0	1	75	1
Bin	(7)	1	0	1673	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1696	1
Bin	(5)	0	1	155	1
Bin	(5)	1	0	1752	1
Bin	(4)	0	1	276	1
Bin	(4)	1	0	1876	1
Bin	(3)	0	1	608	1
Bin	(3)	1	0	2205	1
Bin	(2)	0	1	1361	1
Bin	(2)	1	0	2958	1
Bin	(1)	0	1	3082	1
Bin	(1)	1	0	4678	1
Bin	(0)	0	1	11727	1
Bin	(0)	1	0	13323	1

Port:

DATA_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	63	1
Bin	(15)	1	0	1661	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1667	1
Bin	(13)	0	1	67	1
Bin	(13)	1	0	1665	1
Bin	(12)	0	1	65	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	61	1
Bin	(11)	1	0	1658	1
Bin	(10)	0	1	64	1
Bin	(10)	1	0	1661	1
Bin	(9)	0	1	75	1
Bin	(9)	1	0	1673	1
Bin	(8)	0	1	85	1
Bin	(8)	1	0	1682	1
Bin	(7)	0	1	98	1
Bin	(7)	1	0	1696	1
Bin	(6)	0	1	133	1
Bin	(6)	1	0	1732	1
Bin	(5)	0	1	209	1
Bin	(5)	1	0	1805	1
Bin	(4)	0	1	352	1
Bin	(4)	1	0	1952	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1295	1
Bin	(2)	1	0	2895	1
Bin	(1)	0	1	2523	1
Bin	(1)	1	0	4120	1
Bin	(0)	0	1	5589	1
Bin	(0)	1	0	7187	1

Signal:

TX_ERR_CTR_I

	Element	From	To	Count	Threshold
Bin	(8)	0	1	249	1
Bin	(8)	1	0	1850	1
Bin	(7)	0	1	517	1
Bin	(7)	1	0	2118	1
Bin	(6)	0	1	501	1
Bin	(6)	1	0	2102	1
Bin	(5)	0	1	805	1
Bin	(5)	1	0	2406	1
Bin	(4)	0	1	1933	1
Bin	(4)	1	0	3534	1
Bin	(3)	0	1	12743	1
Bin	(3)	1	0	14344	1
Bin	(2)	0	1	2955	1
Bin	(2)	1	0	4556	1
Bin	(1)	0	1	3324	1
Bin	(1)	1	0	4925	1
Bin	(0)	0	1	3524	1
Bin	(0)	1	0	5125	1

Signal:

RX_ERR_CTR_I

	Element	From	To	Count	Threshold
Bin	(8)	0	1	130	1
Bin	(8)	1	0	1731	1
Bin	(7)	0	1	350	1
Bin	(7)	1	0	1951	1
Bin	(6)	0	1	255	1
Bin	(6)	1	0	1854	1
Bin	(5)	0	1	363	1
Bin	(5)	1	0	1963	1
Bin	(4)	0	1	497	1
Bin	(4)	1	0	2098	1
Bin	(3)	0	1	685	1
Bin	(3)	1	0	2285	1
Bin	(2)	0	1	617	1
Bin	(2)	1	0	2218	1
Bin	(1)	0	1	1191	1
Bin	(1)	1	0	2792	1
Bin	(0)	0	1	11216	1
Bin	(0)	1	0	12809	1

Signal:

INC_ONE

	From	To	Count	Threshold
Bin	0	1	45943	1
Bin	1	0	47544	1

Signal:

INC_EIGHT

	From	To	Count	Threshold
Bin	0	1	81279	1
Bin	1	0	82880	1

Signal:

DEC_ONE

	From	To	Count	Threshold
Bin	0	1	26067	1
Bin	1	0	27668	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 291:

Signal assignment statement on line 292:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

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Covered toggles:

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Signal:

Signal:

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Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: