NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP.G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_T

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/generated/control_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_REG	100.0 % (22/22)	100.0 % (30/30)	100.0 % (40/40)	100.0 % (23/23)	N.A.	N.A.	100.0 % (115/115)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP.G_FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_T	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement	Branch	Toggle	Expression	FSM state	Functional

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: