NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
G_TXTB_PORT_A_CS(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
G_TXTB_PORT_A_CS(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
G_TXTB_PORT_A_CS(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
G_TXTB_PORT_A_CS(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
G_TXTB_PORT_A_CS(4)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
G_TXTB_PORT_A_CS(5)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
G_TXTB_PORT_A_CS(6)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
G_TXTB_PORT_A_CS(7)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)
I_CLK_GATE_CONTROL_REGS	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
I_CLK_GATE_TEST_REGS	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
I_CONTROL_REGISTERS_REG_MAP	100.0 % (2348/2348)	100.0 % (2692/2692)	100.0 % (7926/7926)	100.0 % (2297/2297)	N.A.	100.0 % (73/73)	100.0 % (15336/15336)
G_TEST_REGISTERS_TRUE	100.0 % (289/289)	100.0 % (353/353)	100.0 % (1064/1064)	100.0 % (286/286)	N.A.	100.0 % (7/7)	100.0 % (1999/1999)
I_SOFT_RST_RST_REG	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
I_GLOBAL_RST_RST_REG	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
G_MT_2_TXT_BUFFS	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
G_MT_3_TXT_BUFFS	100.0 % (4/4)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (11/11)
G_MT_4_TXT_BUFFS	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
G_MT_5_TXT_BUFFS	100.0 % (4/4)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (11/11)
G_MT_6_TXT_BUFFS	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (2/2)
G_MT_7_TXT_BUFFS	100.0 % (4/4)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (11/11)
G_TXTB_FUNC_COV(0)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
G_TXTB_FUNC_COV(1)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
G_TXTB_FUNC_COV(2)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
G_TXTB_FUNC_COV(3)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
G_TXTB_FUNC_COV(4)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
G_TXTB_FUNC_COV(5)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
G_TXTB_FUNC_COV(6)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.
G_TXTB_FUNC_COV(7)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP	100.0 % (153/153)	100.0 % (40/40)	100.0 % (5550/5550)	98.6 % (72/73)	N.A.	N.A.	99.9 % (5815/5816)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 351:

351: txtb_port_a_data_in <= data_in;
Count: 2197364
Threshold: 1

Signal assignment statement on line 357:

357: txtb_port_a_address <= adress(6 downto 2);
Count: 55726872
Threshold: 1

If statement on lines 362 to 363:

362:    scs_and_swr <= '1' when (scs = '1' and swr = '1') else 
363:                   '0';

Count: 96534436
Threshold: 1

Signal assignment statement on line 362:

362: scs_and_swr <= '1' when (scs = '1' and swr = '1') else
Count: 802432
Threshold: 1

Signal assignment statement on line 363:

363: '0';
Count: 95732004
Threshold: 1

Signal assignment statement on line 381:

381: txtb_port_a_be <= sbe;
Count: 55725271
Threshold: 1

If statement on lines 386 to 389:

386:    control_registers_cs <= '1' when (adress(11 downto 8) = CONTROL_REGISTERS_BLOCK) and 
387:                                     (scs = '1') 
388:                                else 
389:                            '0';

Count: 96536037
Threshold: 1

Signal assignment statement on line 386:

386: control_registers_cs <= '1' when (adress(11 downto 8) = CONTROL_REGISTERS_BLOCK) and
Count: 19663072
Threshold: 1

Signal assignment statement on line 389:

389: '0';
Count: 76872965
Threshold: 1

If statement on lines 391 to 394:

391:    test_registers_cs <= '1' when (adress(11 downto 8) = TEST_REGISTERS_BLOCK) and 
392:                                  (scs = '1') 
393:                             else 
394:                         '0';

Count: 96536037
Threshold: 1

Signal assignment statement on line 391:

391: test_registers_cs <= '1' when (adress(11 downto 8) = TEST_REGISTERS_BLOCK) and
Count: 313081
Threshold: 1

Signal assignment statement on line 394:

394: '0';
Count: 96222956
Threshold: 1

If statement on lines 401 to 407:

401:        if (rst_n = '0') then 
402:            control_registers_cs_reg  <= '0'; 
...
406:            test_registers_cs_reg <= test_registers_cs; 
407:        end if;

Count: 1096779517
Threshold: 1

Signal assignment statement on line 402:

402: control_registers_cs_reg <= '0';
Count: 50386
Threshold: 1

Signal assignment statement on line 403:

403: test_registers_cs_reg <= '0';
Count: 50386
Threshold: 1

Signal assignment statement on line 405:

405: control_registers_cs_reg <= control_registers_cs;
Count: 548359143
Threshold: 1

Signal assignment statement on line 406:

406: test_registers_cs_reg <= test_registers_cs;
Count: 548359143
Threshold: 1

If statement on lines 414 to 416:

414:    data_out <= control_registers_rdata when (control_registers_cs_reg = '1') else 
415:                   test_registers_rdata when (test_registers_cs_reg = '1') else 
416:                        (others => '0');

Count: 21368953
Threshold: 1

Signal assignment statement on line 414:

414: data_out <= control_registers_rdata when (control_registers_cs_reg = '1') else
Count: 10813545
Threshold: 1

Signal assignment statement on line 415:

415: test_registers_rdata when (test_registers_cs_reg = '1') else
Count: 101956
Threshold: 1

Signal assignment statement on line 416:

416: (others => '0');
Count: 10453452
Threshold: 1

If statement on lines 423 to 425:

423:    control_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (control_registers_cs = '1') 
424:                               else 
425:                           '0';

Count: 95053016
Threshold: 1

Signal assignment statement on line 423:

423: control_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (control_registers_cs = '1')
Count: 19663072
Threshold: 1

Signal assignment statement on line 425:

425: '0';
Count: 75389944
Threshold: 1

If statement on lines 427 to 429:

427:    test_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (test_registers_cs = '1') 
428:                            else 
429:                        '0';

Count: 56353034
Threshold: 1

Signal assignment statement on line 427:

427: test_regs_clk_en <= '1' when (srd = '1' or swr = '1') and (test_registers_cs = '1')
Count: 313081
Threshold: 1

Signal assignment statement on line 429:

429: '0';
Count: 56039953
Threshold: 1

Signal assignment statement on line 487:

487: mr_ctrl_out <= mr_ctrl_out_i;
Count: 500536
Threshold: 1

Signal assignment statement on line 551:

551: mr_tst_out <= mr_tst_out_i;
Count: 202431
Threshold: 1

Signal assignment statement on line 557:

557: reg_lock_1_active <= not mr_ctrl_out_i.mode_tstm;
Count: 5255
Threshold: 1

Signal assignment statement on line 560:

560: reg_lock_2_active <= mr_ctrl_out_i.settings_ena;
Count: 16156
Threshold: 1

Signal assignment statement on line 571:

571: soft_res_d_n <= not mr_ctrl_out_i.mode_rst;
Count: 66622
Threshold: 1

If statement on lines 592 to 594:

592:    res_core_d_n <= '0' when (mr_ctrl_out_i.mode_rst = '1' or mr_ctrl_out_i.settings_ena = '0') 
593:                        else 
594:                    '1';

Count: 81177
Threshold: 1

Signal assignment statement on line 592:

592: res_core_d_n <= '0' when (mr_ctrl_out_i.mode_rst = '1' or mr_ctrl_out_i.settings_ena = '0')
Count: 19724
Threshold: 1

Signal assignment statement on line 594:

594: '1';
Count: 61453
Threshold: 1

Signal assignment statement on line 616:

616: res_soft_n <= soft_res_q_n;
Count: 19290
Threshold: 1

Signal assignment statement on line 624:

624: mr_tx_priority(0) <= mr_ctrl_out_i.tx_priority_txt1p;
Count: 3611
Threshold: 1

Signal assignment statement on line 625:

625: mr_tx_command_txbi(0) <= mr_ctrl_out_i.tx_command_txb1;
Count: 16306
Threshold: 1

Signal assignment statement on line 627:

627: mr_tx_priority(1) <= mr_ctrl_out_i.tx_priority_txt2p;
Count: 3644
Threshold: 1

If statement on lines 628 to 630:

628:    mr_tx_command_txbi(1)   <= mr_ctrl_out_i.tx_command_txb2 when (mr_ctrl_out_i.mode_txbbm = '0') 
629:                                                             else 
630:                               mr_ctrl_out_i.tx_command_txb1 or mr_ctrl_out_i.tx_command_txb2;

Count: 17034
Threshold: 1

Signal assignment statement on line 628:

628: mr_tx_command_txbi(1) <= mr_ctrl_out_i.tx_command_txb2 when (mr_ctrl_out_i.mode_txbbm = '0')
Count: 15292
Threshold: 1

Signal assignment statement on line 630:

630:                               mr_ctrl_out_i.tx_command_txb1 or mr_ctrl_out_i.tx_command_txb2;

Count: 1742
Threshold: 1

Signal assignment statement on line 675:

675: mr_ctrl_in.device_id_device_id <= G_DEVICE_ID;
Count: 1601
Threshold: 1

Signal assignment statement on line 678:

678: mr_ctrl_in.version_ver_minor <= G_VERSION_MINOR;
Count: 1601
Threshold: 1

Signal assignment statement on line 679:

679: mr_ctrl_in.version_ver_major <= G_VERSION_MAJOR;
Count: 1601
Threshold: 1

If statement on lines 682 to 684:

682:    mr_ctrl_in.status_idle <= '1' when (cc_stat.is_bus_off = '1') else 
683:                              '1' when (cc_stat.is_idle = '1') else 
684:                              '0';

Count: 117733
Threshold: 1

Signal assignment statement on line 682:

682: mr_ctrl_in.status_idle <= '1' when (cc_stat.is_bus_off = '1') else
Count: 8364
Threshold: 1

Signal assignment statement on line 683:

683: '1' when (cc_stat.is_idle = '1') else
Count: 56100
Threshold: 1

Signal assignment statement on line 684:

684: '0';
Count: 53269
Threshold: 1

Signal assignment statement on line 685:

685: mr_ctrl_in.status_ewl <= cc_stat.status_ewl;
Count: 4761
Threshold: 1

Signal assignment statement on line 686:

686: mr_ctrl_in.status_txs <= cc_stat.is_transmitter;
Count: 44322
Threshold: 1

Signal assignment statement on line 687:

687: mr_ctrl_in.status_rxs <= cc_stat.is_receiver;
Count: 64941
Threshold: 1

Signal assignment statement on line 692:

692: mr_ctrl_in.status_txnf <= '0';
Count: 82710
Threshold: 1

Loop statement on lines 693 to 697:

693:        for i in 0 to G_TXT_BUF_COUNT - 1 loop 
694:            if (txtb_state(i) = TXT_ETY) then 
695:                mr_ctrl_in.status_txnf <= '1'; 
696:            end if; 
697:        end loop;

Count: 82710
Threshold: 1

If statement on lines 694 to 696:

694:            if (txtb_state(i) = TXT_ETY) then 
695:                mr_ctrl_in.status_txnf <= '1'; 
696:            end if;

Count: 276974
Threshold: 1

Signal assignment statement on line 695:

695: mr_ctrl_in.status_txnf <= '1';
Count: 144613
Threshold: 1

Signal assignment statement on line 700:

700: mr_ctrl_in.status_rxne <= not rx_empty;
Count: 19503
Threshold: 1

Signal assignment statement on line 701:

701: mr_ctrl_in.status_dor <= rx_data_overrun;
Count: 3264
Threshold: 1

Signal assignment statement on line 702:

702: mr_ctrl_in.status_eft <= pc_dbg.is_err;
Count: 57912
Threshold: 1

Signal assignment statement on line 703:

703: mr_ctrl_in.status_pexs <= cc_stat.status_pexs;
Count: 3352
Threshold: 1

Signal assignment statement on line 704:

704: mr_ctrl_in.status_rxpe <= rx_parity_error;
Count: 3228
Threshold: 1

If statement on lines 709 to 730:

709:        if (soft_res_q_n = '0') then 
710:            mr_ctrl_in.status_txpe <= '0'; 
...
729:            end if; 
730:        end if;

Count: 1096782854
Threshold: 1

Signal assignment statement on line 710:

710: mr_ctrl_in.status_txpe <= '0';
Count: 67342
Threshold: 1

Signal assignment statement on line 711:

711: mr_ctrl_in.status_txdpe <= '0';
Count: 67342
Threshold: 1

Loop statement on lines 713 to 721:

713:            for i in 0 to G_TXT_BUF_COUNT - 1 loop 
714:                if (txtb_parity_error_valid(i) = '1') then 
...
720:                end if; 
721:            end loop;

Count: 548351099
Threshold: 1

If statement on lines 714 to 716:

714:                if (txtb_parity_error_valid(i) = '1') then 
715:                    mr_ctrl_in.status_txpe <= '1'; 
716:                end if;

Count: 1332752148
Threshold: 1

Signal assignment statement on line 715:

715: mr_ctrl_in.status_txpe <= '1';
Count: 377
Threshold: 1

If statement on lines 718 to 720:

718:                if (txtb_bb_parity_error(i / 2) = '1') then 
719:                    mr_ctrl_in.status_txdpe <= '1'; 
720:                end if;

Count: 1332752148
Threshold: 1

Signal assignment statement on line 719:

719: mr_ctrl_in.status_txdpe <= '1';
Count: 88
Threshold: 1

If statement on lines 723 to 725:

723:            if (mr_ctrl_out_i.command_ctxpe = '1') then 
724:                mr_ctrl_in.status_txpe <= '0'; 
725:            end if;

Count: 548351099
Threshold: 1

Signal assignment statement on line 724:

724: mr_ctrl_in.status_txpe <= '0';
Count: 440
Threshold: 1

If statement on lines 727 to 729:

727:            if (mr_ctrl_out_i.command_ctxdpe = '1') then 
728:                mr_ctrl_in.status_txdpe <= '0'; 
729:            end if;

Count: 548351099
Threshold: 1

Signal assignment statement on line 728:

728: mr_ctrl_in.status_txdpe <= '0';
Count: 40
Threshold: 1

Sequential statement on lines 733 to 735:

733:    mr_ctrl_in.status_stcnt <= '1' when G_TRAFFIC_CTRS_EN 
734:                                   else 
735:                               '0';

Count: 1601
Threshold: 1

Sequential statement on lines 736 to 738:

736:    mr_ctrl_in.status_sprt <= '1' when G_PARITY_EN 
737:                                  else 
738:                              '0';

Count: 1601
Threshold: 1

Sequential statement on lines 739 to 741:

739:    mr_ctrl_in.status_strgs <= '1' when G_TEST_REGS_EN 
740:                                   else 
741:                               '0';

Count: 1601
Threshold: 1

Signal assignment statement on line 744:

744: mr_ctrl_in.int_stat_rxi <= mr_int_stat_rxi_o;
Count: 4812
Threshold: 1

Signal assignment statement on line 745:

745: mr_ctrl_in.int_stat_txi <= mr_int_stat_txi_o;
Count: 5626
Threshold: 1

Signal assignment statement on line 746:

746: mr_ctrl_in.int_stat_ewli <= mr_int_stat_ewli_o;
Count: 4389
Threshold: 1

Signal assignment statement on line 747:

747: mr_ctrl_in.int_stat_doi <= mr_int_stat_doi_o;
Count: 3244
Threshold: 1

Signal assignment statement on line 748:

748: mr_ctrl_in.int_stat_fcsi <= mr_int_stat_fcsi_o;
Count: 9798
Threshold: 1

Signal assignment statement on line 749:

749: mr_ctrl_in.int_stat_ali <= mr_int_stat_ali_o;
Count: 3400
Threshold: 1

Signal assignment statement on line 750:

750: mr_ctrl_in.int_stat_bei <= mr_int_stat_bei_o;
Count: 6028
Threshold: 1

Signal assignment statement on line 751:

751: mr_ctrl_in.int_stat_ofi <= mr_int_stat_ofi_o;
Count: 3506
Threshold: 1

Signal assignment statement on line 752:

752: mr_ctrl_in.int_stat_rxfi <= mr_int_stat_rxfi_o;
Count: 3242
Threshold: 1

Signal assignment statement on line 753:

753: mr_ctrl_in.int_stat_bsi <= mr_int_stat_bsi_o;
Count: 5817
Threshold: 1

Signal assignment statement on line 754:

754: mr_ctrl_in.int_stat_rbnei <= mr_int_stat_rbnei_o;
Count: 5068
Threshold: 1

Signal assignment statement on line 755:

755: mr_ctrl_in.int_stat_txbhci <= mr_int_stat_txbhci_o;
Count: 6556
Threshold: 1

Signal assignment statement on line 758:

758: mr_ctrl_in.int_ena_set_int_ena_set <= mr_int_ena_set_int_ena_set_o;
Count: 3774
Threshold: 1

Signal assignment statement on line 761:

761: mr_ctrl_in.int_mask_set_int_mask_set <= mr_int_mask_set_int_mask_set_o;
Count: 3436
Threshold: 1

Signal assignment statement on line 764:

764: mr_ctrl_in.fault_state_era <= cc_stat.is_err_active;
Count: 18442
Threshold: 1

Signal assignment statement on line 765:

765: mr_ctrl_in.fault_state_erp <= cc_stat.is_err_passive;
Count: 4744
Threshold: 1

Signal assignment statement on line 766:

766: mr_ctrl_in.fault_state_bof <= cc_stat.is_bus_off;
Count: 18066
Threshold: 1

Signal assignment statement on line 769:

769: mr_ctrl_in.rec_rec_val <= cc_stat.rx_err_ctr;
Count: 27275
Threshold: 1

Signal assignment statement on line 772:

772: mr_ctrl_in.tec_tec_val <= cc_stat.tx_err_ctr;
Count: 33872
Threshold: 1

Signal assignment statement on line 775:

775: mr_ctrl_in.err_norm_err_norm_val <= cc_stat.norm_err_ctr;
Count: 27615
Threshold: 1

Signal assignment statement on line 776:

776: mr_ctrl_in.err_fd_err_fd_val <= cc_stat.data_err_ctr;
Count: 14578
Threshold: 1

Sequential statement on lines 779 to 780:

779:    mr_ctrl_in.filter_status_sfa <= '1' when G_FILT_A_EN else 
780:                                    '0';

Count: 1601
Threshold: 1

Sequential statement on lines 782 to 783:

782:    mr_ctrl_in.filter_status_sfb <= '1' when G_FILT_B_EN else 
783:                                    '0';

Count: 1601
Threshold: 1

Sequential statement on lines 785 to 786:

785:    mr_ctrl_in.filter_status_sfc <= '1' when G_FILT_C_EN else 
786:                                    '0';

Count: 1601
Threshold: 1

Sequential statement on lines 788 to 789:

788:    mr_ctrl_in.filter_status_sfr <= '1' when G_FILT_RANGE_EN else 
789:                                    '0';

Count: 1601
Threshold: 1

Signal assignment statement on line 792:

792: mr_ctrl_in.rx_mem_info_rx_buff_size <= std_logic_vector(to_unsigned(G_RX_BUF_SIZE, 13));
Count: 1601
Threshold: 1

Signal assignment statement on line 796:

796: mr_ctrl_in.rx_mem_info_rx_mem_free <= (others => '0');
Count: 67808
Threshold: 1

Signal assignment statement on line 797:

797: mr_ctrl_in.rx_mem_info_rx_mem_free(G_RX_BUF_PTR_WIDTH downto 0) <= rx_mem_free;
Count: 67808
Threshold: 1

Signal assignment statement on line 803:

803: mr_ctrl_in.rx_pointers_rx_wpp <= (others => '0');
Count: 17651
Threshold: 1

Signal assignment statement on line 804:

804: mr_ctrl_in.rx_pointers_rx_wpp(G_RX_BUF_PTR_WIDTH - 1 downto 0) <= rx_write_pointer;
Count: 17651
Threshold: 1

Signal assignment statement on line 809:

809: mr_ctrl_in.rx_pointers_rx_rpp <= (others => '0');
Count: 54937
Threshold: 1

Signal assignment statement on line 810:

810: mr_ctrl_in.rx_pointers_rx_rpp(G_RX_BUF_PTR_WIDTH - 1 downto 0) <= rx_read_pointer;
Count: 54937
Threshold: 1

Signal assignment statement on line 814:

814: mr_ctrl_in.rx_status_rxe <= rx_empty;
Count: 19503
Threshold: 1

Signal assignment statement on line 815:

815: mr_ctrl_in.rx_status_rxf <= rx_full;
Count: 3242
Threshold: 1

Signal assignment statement on line 816:

816: mr_ctrl_in.rx_status_rxmof <= rx_mof;
Count: 23319
Threshold: 1

Signal assignment statement on line 820:

820: mr_ctrl_in.rx_status_rxfrc <= (others => '0');
Count: 26156
Threshold: 1

Signal assignment statement on line 821:

821: mr_ctrl_in.rx_status_rxfrc(G_RX_BUF_FRAME_CNT_WIDTH - 1 downto 0) <= rx_frame_count;
Count: 26156
Threshold: 1

Signal assignment statement on line 825:

825: mr_ctrl_in.rx_data_rx_data <= rxb_port_b_data_out;
Count: 59708
Threshold: 1

Variable assignment statement on line 831:

831: txtb_state_padded := (others => (others => '0'));
Count: 82710
Threshold: 1

Variable assignment statement on line 832:

832: txtb_state_padded(G_TXT_BUF_COUNT - 1 downto 0) := txtb_state;
Count: 82710
Threshold: 1

Signal assignment statement on line 834:

834: mr_ctrl_in.tx_status_tx1s <= txtb_state_padded(0);
Count: 82710
Threshold: 1

Signal assignment statement on line 835:

835: mr_ctrl_in.tx_status_tx2s <= txtb_state_padded(1);
Count: 82710
Threshold: 1

Signal assignment statement on line 836:

836: mr_ctrl_in.tx_status_tx3s <= txtb_state_padded(2);
Count: 82710
Threshold: 1

Signal assignment statement on line 837:

837: mr_ctrl_in.tx_status_tx4s <= txtb_state_padded(3);
Count: 82710
Threshold: 1

Signal assignment statement on line 838:

838: mr_ctrl_in.tx_status_tx5s <= txtb_state_padded(4);
Count: 82710
Threshold: 1

Signal assignment statement on line 839:

839: mr_ctrl_in.tx_status_tx6s <= txtb_state_padded(5);
Count: 82710
Threshold: 1

Signal assignment statement on line 840:

840: mr_ctrl_in.tx_status_tx7s <= txtb_state_padded(6);
Count: 82710
Threshold: 1

Signal assignment statement on line 841:

841: mr_ctrl_in.tx_status_tx8s <= txtb_state_padded(7);
Count: 82710
Threshold: 1

Signal assignment statement on line 845:

845: mr_ctrl_in.txtb_info_txt_buffer_count <= std_logic_vector(to_unsigned(G_TXT_BUF_COUNT, 4));
Count: 1601
Threshold: 1

Signal assignment statement on line 848:

848: mr_ctrl_in.err_capt_err_pos <= cc_stat.err_pos;
Count: 12035
Threshold: 1

Signal assignment statement on line 849:

849: mr_ctrl_in.err_capt_err_type <= cc_stat.err_type;
Count: 7061
Threshold: 1

Signal assignment statement on line 850:

850: mr_ctrl_in.err_capt_err_erp <= cc_stat.err_erp;
Count: 3792
Threshold: 1

Signal assignment statement on line 853:

853: mr_ctrl_in.retr_ctr_retr_ctr_val <= cc_stat.retr_ctr;
Count: 4527
Threshold: 1

Signal assignment statement on line 856:

856: mr_ctrl_in.alc_alc_bit <= cc_stat.alc_bit;
Count: 3825
Threshold: 1

Signal assignment statement on line 857:

857: mr_ctrl_in.alc_alc_id_field <= cc_stat.alc_id_field;
Count: 3473
Threshold: 1

Signal assignment statement on line 860:

860: mr_ctrl_in.ts_info_ts_bits <= std_logic_vector(to_unsigned(G_TS_BITS, 6));
Count: 1601
Threshold: 1

Signal assignment statement on line 863:

863: mr_ctrl_in.trv_delay_trv_delay_value <= trv_delay;
Count: 7672
Threshold: 1

Signal assignment statement on line 866:

866: mr_ctrl_in.rx_fr_ctr_rx_fr_ctr_val <= cc_stat.rx_frame_ctr;
Count: 15394
Threshold: 1

Signal assignment statement on line 869:

869: mr_ctrl_in.tx_fr_ctr_tx_fr_ctr_val <= cc_stat.tx_frame_ctr;
Count: 8155
Threshold: 1

Signal assignment statement on line 872:

872: mr_ctrl_in.debug_register_stuff_count <= cc_stat.bst_ctr;
Count: 298951
Threshold: 1

Signal assignment statement on line 873:

873: mr_ctrl_in.debug_register_destuff_count <= cc_stat.dst_ctr;
Count: 999446
Threshold: 1

Signal assignment statement on line 874:

874: mr_ctrl_in.debug_register_pc_arb <= pc_dbg.is_arbitration;
Count: 115022
Threshold: 1

Signal assignment statement on line 875:

875: mr_ctrl_in.debug_register_pc_con <= pc_dbg.is_control;
Count: 105734
Threshold: 1

Signal assignment statement on line 876:

876: mr_ctrl_in.debug_register_pc_dat <= pc_dbg.is_data;
Count: 76512
Threshold: 1

Signal assignment statement on line 877:

877: mr_ctrl_in.debug_register_pc_stc <= pc_dbg.is_stuff_count;
Count: 29236
Threshold: 1

Signal assignment statement on line 878:

878: mr_ctrl_in.debug_register_pc_crc <= pc_dbg.is_crc;
Count: 65530
Threshold: 1

Signal assignment statement on line 879:

879: mr_ctrl_in.debug_register_pc_crcd <= pc_dbg.is_crc_delim;
Count: 62606
Threshold: 1

Signal assignment statement on line 880:

880: mr_ctrl_in.debug_register_pc_ack <= pc_dbg.is_ack;
Count: 62298
Threshold: 1

Signal assignment statement on line 881:

881: mr_ctrl_in.debug_register_pc_ackd <= pc_dbg.is_ack_delim;
Count: 59442
Threshold: 1

Signal assignment statement on line 882:

882: mr_ctrl_in.debug_register_pc_eof <= pc_dbg.is_eof;
Count: 57652
Threshold: 1

Signal assignment statement on line 883:

883: mr_ctrl_in.debug_register_pc_int <= pc_dbg.is_intermission;
Count: 107009
Threshold: 1

Signal assignment statement on line 884:

884: mr_ctrl_in.debug_register_pc_susp <= pc_dbg.is_suspend;
Count: 8900
Threshold: 1

Signal assignment statement on line 885:

885: mr_ctrl_in.debug_register_pc_ovr <= pc_dbg.is_overload;
Count: 4260
Threshold: 1

Signal assignment statement on line 886:

886: mr_ctrl_in.debug_register_pc_sof <= pc_dbg.is_sof;
Count: 53498
Threshold: 1

Signal assignment statement on line 889:

889: mr_ctrl_in.yolo_reg_yolo_val <= YOLO_VAL_RSTVAL;
Count: 1601
Threshold: 1

Signal assignment statement on line 892:

892: mr_ctrl_in.timestamp_low_timestamp_low <= timestamp(31 downto 0);
Count: 548382586
Threshold: 1

Signal assignment statement on line 893:

893: mr_ctrl_in.timestamp_high_timestamp_high <= timestamp(63 downto 32);
Count: 3442
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	802432	1
Bin	False	95732004	1

	Evaluated to	Count	Threshold
Bin	True	19663072	1
Bin	False	76872965	1

	Evaluated to	Count	Threshold
Bin	True	313081	1
Bin	False	96222956	1

	Evaluated to	Count	Threshold
Bin	True	50386	1
Bin	False	1096729131	1

	Evaluated to	Count	Threshold
Bin	True	548359143	1
Bin	False	548369988	1

	Evaluated to	Count	Threshold
Bin	True	10813545	1
Bin	False	10555408	1

	Evaluated to	Count	Threshold
Bin	True	101956	1
Bin	False	10453452	1

	Evaluated to	Count	Threshold
Bin	True	19663072	1
Bin	False	75389944	1

	Evaluated to	Count	Threshold
Bin	True	313081	1
Bin	False	56039953	1

	Evaluated to	Count	Threshold
Bin	True	19724	1
Bin	False	61453	1

	Evaluated to	Count	Threshold
Bin	True	15292	1
Bin	False	1742	1

	Evaluated to	Count	Threshold
Bin	True	8364	1
Bin	False	109369	1

	Evaluated to	Count	Threshold
Bin	True	56100	1
Bin	False	53269	1

	Evaluated to	Count	Threshold
Bin	True	144613	1
Bin	False	132361	1

	Evaluated to	Count	Threshold
Bin	True	67342	1
Bin	False	1096715512	1

	Evaluated to	Count	Threshold
Bin	True	548351099	1
Bin	False	548364413	1

	Evaluated to	Count	Threshold
Bin	True	377	1
Bin	False	1332751771	1

	Evaluated to	Count	Threshold
Bin	True	88	1
Bin	False	1332752060	1

	Evaluated to	Count	Threshold
Bin	True	440	1
Bin	False	548350659	1

	Evaluated to	Count	Threshold
Bin	True	40	1
Bin	False	548351059	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ADRESS

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SCS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SRD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SWR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SBE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TIMESTAMP

	Element	From	To	Threshold	Excluded due to
Bin	(63)	0	1	1	Exclude file
Bin	(63)	1	0	1	Exclude file
Bin	(62)	0	1	1	Exclude file
Bin	(62)	1	0	1	Exclude file
Bin	(61)	0	1	1	Exclude file
Bin	(61)	1	0	1	Exclude file
Bin	(60)	0	1	1	Exclude file
Bin	(60)	1	0	1	Exclude file
Bin	(59)	0	1	1	Exclude file
Bin	(59)	1	0	1	Exclude file
Bin	(58)	0	1	1	Exclude file
Bin	(58)	1	0	1	Exclude file
Bin	(57)	0	1	1	Exclude file
Bin	(57)	1	0	1	Exclude file
Bin	(56)	0	1	1	Exclude file
Bin	(56)	1	0	1	Exclude file
Bin	(55)	0	1	1	Exclude file
Bin	(55)	1	0	1	Exclude file
Bin	(54)	0	1	1	Exclude file
Bin	(54)	1	0	1	Exclude file
Bin	(53)	0	1	1	Exclude file
Bin	(53)	1	0	1	Exclude file
Bin	(52)	0	1	1	Exclude file
Bin	(52)	1	0	1	Exclude file
Bin	(51)	0	1	1	Exclude file
Bin	(51)	1	0	1	Exclude file
Bin	(50)	0	1	1	Exclude file
Bin	(50)	1	0	1	Exclude file
Bin	(49)	0	1	1	Exclude file
Bin	(49)	1	0	1	Exclude file
Bin	(48)	0	1	1	Exclude file
Bin	(48)	1	0	1	Exclude file
Bin	(47)	0	1	1	Exclude file
Bin	(47)	1	0	1	Exclude file
Bin	(46)	0	1	1	Exclude file
Bin	(46)	1	0	1	Exclude file
Bin	(45)	0	1	1	Exclude file
Bin	(45)	1	0	1	Exclude file
Bin	(44)	0	1	1	Exclude file
Bin	(44)	1	0	1	Exclude file
Bin	(43)	0	1	1	Exclude file
Bin	(43)	1	0	1	Exclude file
Bin	(42)	0	1	1	Exclude file
Bin	(42)	1	0	1	Exclude file
Bin	(41)	0	1	1	Exclude file
Bin	(41)	1	0	1	Exclude file
Bin	(40)	0	1	1	Exclude file
Bin	(40)	1	0	1	Exclude file
Bin	(39)	0	1	1	Exclude file
Bin	(39)	1	0	1	Exclude file
Bin	(38)	0	1	1	Exclude file
Bin	(38)	1	0	1	Exclude file
Bin	(37)	0	1	1	Exclude file
Bin	(37)	1	0	1	Exclude file
Bin	(36)	0	1	1	Exclude file
Bin	(36)	1	0	1	Exclude file
Bin	(35)	0	1	1	Exclude file
Bin	(35)	1	0	1	Exclude file
Bin	(34)	0	1	1	Exclude file
Bin	(34)	1	0	1	Exclude file
Bin	(33)	0	1	1	Exclude file
Bin	(33)	1	0	1	Exclude file
Bin	(32)	0	1	1	Exclude file
Bin	(32)	1	0	1	Exclude file
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_RDATA_TST_RDATA_RXB

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_RDATA_TST_RDATA_TXB

	Element	From	To	Threshold	Excluded due to
Bin	(7)(31)	0	1	1	Exclude file
Bin	(7)(31)	1	0	1	Exclude file
Bin	(7)(30)	0	1	1	Exclude file
Bin	(7)(30)	1	0	1	Exclude file
Bin	(7)(29)	0	1	1	Exclude file
Bin	(7)(29)	1	0	1	Exclude file
Bin	(7)(28)	0	1	1	Exclude file
Bin	(7)(28)	1	0	1	Exclude file
Bin	(7)(27)	0	1	1	Exclude file
Bin	(7)(27)	1	0	1	Exclude file
Bin	(7)(26)	0	1	1	Exclude file
Bin	(7)(26)	1	0	1	Exclude file
Bin	(7)(25)	0	1	1	Exclude file
Bin	(7)(25)	1	0	1	Exclude file
Bin	(7)(24)	0	1	1	Exclude file
Bin	(7)(24)	1	0	1	Exclude file
Bin	(7)(23)	0	1	1	Exclude file
Bin	(7)(23)	1	0	1	Exclude file
Bin	(7)(22)	0	1	1	Exclude file
Bin	(7)(22)	1	0	1	Exclude file
Bin	(7)(21)	0	1	1	Exclude file
Bin	(7)(21)	1	0	1	Exclude file
Bin	(7)(20)	0	1	1	Exclude file
Bin	(7)(20)	1	0	1	Exclude file
Bin	(7)(19)	0	1	1	Exclude file
Bin	(7)(19)	1	0	1	Exclude file
Bin	(7)(18)	0	1	1	Exclude file
Bin	(7)(18)	1	0	1	Exclude file
Bin	(7)(17)	0	1	1	Exclude file
Bin	(7)(17)	1	0	1	Exclude file
Bin	(7)(16)	0	1	1	Exclude file
Bin	(7)(16)	1	0	1	Exclude file
Bin	(7)(15)	0	1	1	Exclude file
Bin	(7)(15)	1	0	1	Exclude file
Bin	(7)(14)	0	1	1	Exclude file
Bin	(7)(14)	1	0	1	Exclude file
Bin	(7)(13)	0	1	1	Exclude file
Bin	(7)(13)	1	0	1	Exclude file
Bin	(7)(12)	0	1	1	Exclude file
Bin	(7)(12)	1	0	1	Exclude file
Bin	(7)(11)	0	1	1	Exclude file
Bin	(7)(11)	1	0	1	Exclude file
Bin	(7)(10)	0	1	1	Exclude file
Bin	(7)(10)	1	0	1	Exclude file
Bin	(7)(9)	0	1	1	Exclude file
Bin	(7)(9)	1	0	1	Exclude file
Bin	(7)(8)	0	1	1	Exclude file
Bin	(7)(8)	1	0	1	Exclude file
Bin	(7)(7)	0	1	1	Exclude file
Bin	(7)(7)	1	0	1	Exclude file
Bin	(7)(6)	0	1	1	Exclude file
Bin	(7)(6)	1	0	1	Exclude file
Bin	(7)(5)	0	1	1	Exclude file
Bin	(7)(5)	1	0	1	Exclude file
Bin	(7)(4)	0	1	1	Exclude file
Bin	(7)(4)	1	0	1	Exclude file
Bin	(7)(3)	0	1	1	Exclude file
Bin	(7)(3)	1	0	1	Exclude file
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(31)	0	1	1	Exclude file
Bin	(6)(31)	1	0	1	Exclude file
Bin	(6)(30)	0	1	1	Exclude file
Bin	(6)(30)	1	0	1	Exclude file
Bin	(6)(29)	0	1	1	Exclude file
Bin	(6)(29)	1	0	1	Exclude file
Bin	(6)(28)	0	1	1	Exclude file
Bin	(6)(28)	1	0	1	Exclude file
Bin	(6)(27)	0	1	1	Exclude file
Bin	(6)(27)	1	0	1	Exclude file
Bin	(6)(26)	0	1	1	Exclude file
Bin	(6)(26)	1	0	1	Exclude file
Bin	(6)(25)	0	1	1	Exclude file
Bin	(6)(25)	1	0	1	Exclude file
Bin	(6)(24)	0	1	1	Exclude file
Bin	(6)(24)	1	0	1	Exclude file
Bin	(6)(23)	0	1	1	Exclude file
Bin	(6)(23)	1	0	1	Exclude file
Bin	(6)(22)	0	1	1	Exclude file
Bin	(6)(22)	1	0	1	Exclude file
Bin	(6)(21)	0	1	1	Exclude file
Bin	(6)(21)	1	0	1	Exclude file
Bin	(6)(20)	0	1	1	Exclude file
Bin	(6)(20)	1	0	1	Exclude file
Bin	(6)(19)	0	1	1	Exclude file
Bin	(6)(19)	1	0	1	Exclude file
Bin	(6)(18)	0	1	1	Exclude file
Bin	(6)(18)	1	0	1	Exclude file
Bin	(6)(17)	0	1	1	Exclude file
Bin	(6)(17)	1	0	1	Exclude file
Bin	(6)(16)	0	1	1	Exclude file
Bin	(6)(16)	1	0	1	Exclude file
Bin	(6)(15)	0	1	1	Exclude file
Bin	(6)(15)	1	0	1	Exclude file
Bin	(6)(14)	0	1	1	Exclude file
Bin	(6)(14)	1	0	1	Exclude file
Bin	(6)(13)	0	1	1	Exclude file
Bin	(6)(13)	1	0	1	Exclude file
Bin	(6)(12)	0	1	1	Exclude file
Bin	(6)(12)	1	0	1	Exclude file
Bin	(6)(11)	0	1	1	Exclude file
Bin	(6)(11)	1	0	1	Exclude file
Bin	(6)(10)	0	1	1	Exclude file
Bin	(6)(10)	1	0	1	Exclude file
Bin	(6)(9)	0	1	1	Exclude file
Bin	(6)(9)	1	0	1	Exclude file
Bin	(6)(8)	0	1	1	Exclude file
Bin	(6)(8)	1	0	1	Exclude file
Bin	(6)(7)	0	1	1	Exclude file
Bin	(6)(7)	1	0	1	Exclude file
Bin	(6)(6)	0	1	1	Exclude file
Bin	(6)(6)	1	0	1	Exclude file
Bin	(6)(5)	0	1	1	Exclude file
Bin	(6)(5)	1	0	1	Exclude file
Bin	(6)(4)	0	1	1	Exclude file
Bin	(6)(4)	1	0	1	Exclude file
Bin	(6)(3)	0	1	1	Exclude file
Bin	(6)(3)	1	0	1	Exclude file
Bin	(6)(2)	0	1	1	Exclude file
Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
Bin	(6)(1)	1	0	1	Exclude file
Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
Bin	(5)(31)	0	1	1	Exclude file
Bin	(5)(31)	1	0	1	Exclude file
Bin	(5)(30)	0	1	1	Exclude file
Bin	(5)(30)	1	0	1	Exclude file
Bin	(5)(29)	0	1	1	Exclude file
Bin	(5)(29)	1	0	1	Exclude file
Bin	(5)(28)	0	1	1	Exclude file
Bin	(5)(28)	1	0	1	Exclude file
Bin	(5)(27)	0	1	1	Exclude file
Bin	(5)(27)	1	0	1	Exclude file
Bin	(5)(26)	0	1	1	Exclude file
Bin	(5)(26)	1	0	1	Exclude file
Bin	(5)(25)	0	1	1	Exclude file
Bin	(5)(25)	1	0	1	Exclude file
Bin	(5)(24)	0	1	1	Exclude file
Bin	(5)(24)	1	0	1	Exclude file
Bin	(5)(23)	0	1	1	Exclude file
Bin	(5)(23)	1	0	1	Exclude file
Bin	(5)(22)	0	1	1	Exclude file
Bin	(5)(22)	1	0	1	Exclude file
Bin	(5)(21)	0	1	1	Exclude file
Bin	(5)(21)	1	0	1	Exclude file
Bin	(5)(20)	0	1	1	Exclude file
Bin	(5)(20)	1	0	1	Exclude file
Bin	(5)(19)	0	1	1	Exclude file
Bin	(5)(19)	1	0	1	Exclude file
Bin	(5)(18)	0	1	1	Exclude file
Bin	(5)(18)	1	0	1	Exclude file
Bin	(5)(17)	0	1	1	Exclude file
Bin	(5)(17)	1	0	1	Exclude file
Bin	(5)(16)	0	1	1	Exclude file
Bin	(5)(16)	1	0	1	Exclude file
Bin	(5)(15)	0	1	1	Exclude file
Bin	(5)(15)	1	0	1	Exclude file
Bin	(5)(14)	0	1	1	Exclude file
Bin	(5)(14)	1	0	1	Exclude file
Bin	(5)(13)	0	1	1	Exclude file
Bin	(5)(13)	1	0	1	Exclude file
Bin	(5)(12)	0	1	1	Exclude file
Bin	(5)(12)	1	0	1	Exclude file
Bin	(5)(11)	0	1	1	Exclude file
Bin	(5)(11)	1	0	1	Exclude file
Bin	(5)(10)	0	1	1	Exclude file
Bin	(5)(10)	1	0	1	Exclude file
Bin	(5)(9)	0	1	1	Exclude file
Bin	(5)(9)	1	0	1	Exclude file
Bin	(5)(8)	0	1	1	Exclude file
Bin	(5)(8)	1	0	1	Exclude file
Bin	(5)(7)	0	1	1	Exclude file
Bin	(5)(7)	1	0	1	Exclude file
Bin	(5)(6)	0	1	1	Exclude file
Bin	(5)(6)	1	0	1	Exclude file
Bin	(5)(5)	0	1	1	Exclude file
Bin	(5)(5)	1	0	1	Exclude file
Bin	(5)(4)	0	1	1	Exclude file
Bin	(5)(4)	1	0	1	Exclude file
Bin	(5)(3)	0	1	1	Exclude file
Bin	(5)(3)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(31)	0	1	1	Exclude file
Bin	(4)(31)	1	0	1	Exclude file
Bin	(4)(30)	0	1	1	Exclude file
Bin	(4)(30)	1	0	1	Exclude file
Bin	(4)(29)	0	1	1	Exclude file
Bin	(4)(29)	1	0	1	Exclude file
Bin	(4)(28)	0	1	1	Exclude file
Bin	(4)(28)	1	0	1	Exclude file
Bin	(4)(27)	0	1	1	Exclude file
Bin	(4)(27)	1	0	1	Exclude file
Bin	(4)(26)	0	1	1	Exclude file
Bin	(4)(26)	1	0	1	Exclude file
Bin	(4)(25)	0	1	1	Exclude file
Bin	(4)(25)	1	0	1	Exclude file
Bin	(4)(24)	0	1	1	Exclude file
Bin	(4)(24)	1	0	1	Exclude file
Bin	(4)(23)	0	1	1	Exclude file
Bin	(4)(23)	1	0	1	Exclude file
Bin	(4)(22)	0	1	1	Exclude file
Bin	(4)(22)	1	0	1	Exclude file
Bin	(4)(21)	0	1	1	Exclude file
Bin	(4)(21)	1	0	1	Exclude file
Bin	(4)(20)	0	1	1	Exclude file
Bin	(4)(20)	1	0	1	Exclude file
Bin	(4)(19)	0	1	1	Exclude file
Bin	(4)(19)	1	0	1	Exclude file
Bin	(4)(18)	0	1	1	Exclude file
Bin	(4)(18)	1	0	1	Exclude file
Bin	(4)(17)	0	1	1	Exclude file
Bin	(4)(17)	1	0	1	Exclude file
Bin	(4)(16)	0	1	1	Exclude file
Bin	(4)(16)	1	0	1	Exclude file
Bin	(4)(15)	0	1	1	Exclude file
Bin	(4)(15)	1	0	1	Exclude file
Bin	(4)(14)	0	1	1	Exclude file
Bin	(4)(14)	1	0	1	Exclude file
Bin	(4)(13)	0	1	1	Exclude file
Bin	(4)(13)	1	0	1	Exclude file
Bin	(4)(12)	0	1	1	Exclude file
Bin	(4)(12)	1	0	1	Exclude file
Bin	(4)(11)	0	1	1	Exclude file
Bin	(4)(11)	1	0	1	Exclude file
Bin	(4)(10)	0	1	1	Exclude file
Bin	(4)(10)	1	0	1	Exclude file
Bin	(4)(9)	0	1	1	Exclude file
Bin	(4)(9)	1	0	1	Exclude file
Bin	(4)(8)	0	1	1	Exclude file
Bin	(4)(8)	1	0	1	Exclude file
Bin	(4)(7)	0	1	1	Exclude file
Bin	(4)(7)	1	0	1	Exclude file
Bin	(4)(6)	0	1	1	Exclude file
Bin	(4)(6)	1	0	1	Exclude file
Bin	(4)(5)	0	1	1	Exclude file
Bin	(4)(5)	1	0	1	Exclude file
Bin	(4)(4)	0	1	1	Exclude file
Bin	(4)(4)	1	0	1	Exclude file
Bin	(4)(3)	0	1	1	Exclude file
Bin	(4)(3)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(31)	0	1	1	Exclude file
Bin	(3)(31)	1	0	1	Exclude file
Bin	(3)(30)	0	1	1	Exclude file
Bin	(3)(30)	1	0	1	Exclude file
Bin	(3)(29)	0	1	1	Exclude file
Bin	(3)(29)	1	0	1	Exclude file
Bin	(3)(28)	0	1	1	Exclude file
Bin	(3)(28)	1	0	1	Exclude file
Bin	(3)(27)	0	1	1	Exclude file
Bin	(3)(27)	1	0	1	Exclude file
Bin	(3)(26)	0	1	1	Exclude file
Bin	(3)(26)	1	0	1	Exclude file
Bin	(3)(25)	0	1	1	Exclude file
Bin	(3)(25)	1	0	1	Exclude file
Bin	(3)(24)	0	1	1	Exclude file
Bin	(3)(24)	1	0	1	Exclude file
Bin	(3)(23)	0	1	1	Exclude file
Bin	(3)(23)	1	0	1	Exclude file
Bin	(3)(22)	0	1	1	Exclude file
Bin	(3)(22)	1	0	1	Exclude file
Bin	(3)(21)	0	1	1	Exclude file
Bin	(3)(21)	1	0	1	Exclude file
Bin	(3)(20)	0	1	1	Exclude file
Bin	(3)(20)	1	0	1	Exclude file
Bin	(3)(19)	0	1	1	Exclude file
Bin	(3)(19)	1	0	1	Exclude file
Bin	(3)(18)	0	1	1	Exclude file
Bin	(3)(18)	1	0	1	Exclude file
Bin	(3)(17)	0	1	1	Exclude file
Bin	(3)(17)	1	0	1	Exclude file
Bin	(3)(16)	0	1	1	Exclude file
Bin	(3)(16)	1	0	1	Exclude file
Bin	(3)(15)	0	1	1	Exclude file
Bin	(3)(15)	1	0	1	Exclude file
Bin	(3)(14)	0	1	1	Exclude file
Bin	(3)(14)	1	0	1	Exclude file
Bin	(3)(13)	0	1	1	Exclude file
Bin	(3)(13)	1	0	1	Exclude file
Bin	(3)(12)	0	1	1	Exclude file
Bin	(3)(12)	1	0	1	Exclude file
Bin	(3)(11)	0	1	1	Exclude file
Bin	(3)(11)	1	0	1	Exclude file
Bin	(3)(10)	0	1	1	Exclude file
Bin	(3)(10)	1	0	1	Exclude file
Bin	(3)(9)	0	1	1	Exclude file
Bin	(3)(9)	1	0	1	Exclude file
Bin	(3)(8)	0	1	1	Exclude file
Bin	(3)(8)	1	0	1	Exclude file
Bin	(3)(7)	0	1	1	Exclude file
Bin	(3)(7)	1	0	1	Exclude file
Bin	(3)(6)	0	1	1	Exclude file
Bin	(3)(6)	1	0	1	Exclude file
Bin	(3)(5)	0	1	1	Exclude file
Bin	(3)(5)	1	0	1	Exclude file
Bin	(3)(4)	0	1	1	Exclude file
Bin	(3)(4)	1	0	1	Exclude file
Bin	(3)(3)	0	1	1	Exclude file
Bin	(3)(3)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(31)	0	1	1	Exclude file
Bin	(2)(31)	1	0	1	Exclude file
Bin	(2)(30)	0	1	1	Exclude file
Bin	(2)(30)	1	0	1	Exclude file
Bin	(2)(29)	0	1	1	Exclude file
Bin	(2)(29)	1	0	1	Exclude file
Bin	(2)(28)	0	1	1	Exclude file
Bin	(2)(28)	1	0	1	Exclude file
Bin	(2)(27)	0	1	1	Exclude file
Bin	(2)(27)	1	0	1	Exclude file
Bin	(2)(26)	0	1	1	Exclude file
Bin	(2)(26)	1	0	1	Exclude file
Bin	(2)(25)	0	1	1	Exclude file
Bin	(2)(25)	1	0	1	Exclude file
Bin	(2)(24)	0	1	1	Exclude file
Bin	(2)(24)	1	0	1	Exclude file
Bin	(2)(23)	0	1	1	Exclude file
Bin	(2)(23)	1	0	1	Exclude file
Bin	(2)(22)	0	1	1	Exclude file
Bin	(2)(22)	1	0	1	Exclude file
Bin	(2)(21)	0	1	1	Exclude file
Bin	(2)(21)	1	0	1	Exclude file
Bin	(2)(20)	0	1	1	Exclude file
Bin	(2)(20)	1	0	1	Exclude file
Bin	(2)(19)	0	1	1	Exclude file
Bin	(2)(19)	1	0	1	Exclude file
Bin	(2)(18)	0	1	1	Exclude file
Bin	(2)(18)	1	0	1	Exclude file
Bin	(2)(17)	0	1	1	Exclude file
Bin	(2)(17)	1	0	1	Exclude file
Bin	(2)(16)	0	1	1	Exclude file
Bin	(2)(16)	1	0	1	Exclude file
Bin	(2)(15)	0	1	1	Exclude file
Bin	(2)(15)	1	0	1	Exclude file
Bin	(2)(14)	0	1	1	Exclude file
Bin	(2)(14)	1	0	1	Exclude file
Bin	(2)(13)	0	1	1	Exclude file
Bin	(2)(13)	1	0	1	Exclude file
Bin	(2)(12)	0	1	1	Exclude file
Bin	(2)(12)	1	0	1	Exclude file
Bin	(2)(11)	0	1	1	Exclude file
Bin	(2)(11)	1	0	1	Exclude file
Bin	(2)(10)	0	1	1	Exclude file
Bin	(2)(10)	1	0	1	Exclude file
Bin	(2)(9)	0	1	1	Exclude file
Bin	(2)(9)	1	0	1	Exclude file
Bin	(2)(8)	0	1	1	Exclude file
Bin	(2)(8)	1	0	1	Exclude file
Bin	(2)(7)	0	1	1	Exclude file
Bin	(2)(7)	1	0	1	Exclude file
Bin	(2)(6)	0	1	1	Exclude file
Bin	(2)(6)	1	0	1	Exclude file
Bin	(2)(5)	0	1	1	Exclude file
Bin	(2)(5)	1	0	1	Exclude file
Bin	(2)(4)	0	1	1	Exclude file
Bin	(2)(4)	1	0	1	Exclude file
Bin	(2)(3)	0	1	1	Exclude file
Bin	(2)(3)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(31)	0	1	1	Exclude file
Bin	(1)(31)	1	0	1	Exclude file
Bin	(1)(30)	0	1	1	Exclude file
Bin	(1)(30)	1	0	1	Exclude file
Bin	(1)(29)	0	1	1	Exclude file
Bin	(1)(29)	1	0	1	Exclude file
Bin	(1)(28)	0	1	1	Exclude file
Bin	(1)(28)	1	0	1	Exclude file
Bin	(1)(27)	0	1	1	Exclude file
Bin	(1)(27)	1	0	1	Exclude file
Bin	(1)(26)	0	1	1	Exclude file
Bin	(1)(26)	1	0	1	Exclude file
Bin	(1)(25)	0	1	1	Exclude file
Bin	(1)(25)	1	0	1	Exclude file
Bin	(1)(24)	0	1	1	Exclude file
Bin	(1)(24)	1	0	1	Exclude file
Bin	(1)(23)	0	1	1	Exclude file
Bin	(1)(23)	1	0	1	Exclude file
Bin	(1)(22)	0	1	1	Exclude file
Bin	(1)(22)	1	0	1	Exclude file
Bin	(1)(21)	0	1	1	Exclude file
Bin	(1)(21)	1	0	1	Exclude file
Bin	(1)(20)	0	1	1	Exclude file
Bin	(1)(20)	1	0	1	Exclude file
Bin	(1)(19)	0	1	1	Exclude file
Bin	(1)(19)	1	0	1	Exclude file
Bin	(1)(18)	0	1	1	Exclude file
Bin	(1)(18)	1	0	1	Exclude file
Bin	(1)(17)	0	1	1	Exclude file
Bin	(1)(17)	1	0	1	Exclude file
Bin	(1)(16)	0	1	1	Exclude file
Bin	(1)(16)	1	0	1	Exclude file
Bin	(1)(15)	0	1	1	Exclude file
Bin	(1)(15)	1	0	1	Exclude file
Bin	(1)(14)	0	1	1	Exclude file
Bin	(1)(14)	1	0	1	Exclude file
Bin	(1)(13)	0	1	1	Exclude file
Bin	(1)(13)	1	0	1	Exclude file
Bin	(1)(12)	0	1	1	Exclude file
Bin	(1)(12)	1	0	1	Exclude file
Bin	(1)(11)	0	1	1	Exclude file
Bin	(1)(11)	1	0	1	Exclude file
Bin	(1)(10)	0	1	1	Exclude file
Bin	(1)(10)	1	0	1	Exclude file
Bin	(1)(9)	0	1	1	Exclude file
Bin	(1)(9)	1	0	1	Exclude file
Bin	(1)(8)	0	1	1	Exclude file
Bin	(1)(8)	1	0	1	Exclude file
Bin	(1)(7)	0	1	1	Exclude file
Bin	(1)(7)	1	0	1	Exclude file
Bin	(1)(6)	0	1	1	Exclude file
Bin	(1)(6)	1	0	1	Exclude file
Bin	(1)(5)	0	1	1	Exclude file
Bin	(1)(5)	1	0	1	Exclude file
Bin	(1)(4)	0	1	1	Exclude file
Bin	(1)(4)	1	0	1	Exclude file
Bin	(1)(3)	0	1	1	Exclude file
Bin	(1)(3)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(31)	0	1	1	Exclude file
Bin	(0)(31)	1	0	1	Exclude file
Bin	(0)(30)	0	1	1	Exclude file
Bin	(0)(30)	1	0	1	Exclude file
Bin	(0)(29)	0	1	1	Exclude file
Bin	(0)(29)	1	0	1	Exclude file
Bin	(0)(28)	0	1	1	Exclude file
Bin	(0)(28)	1	0	1	Exclude file
Bin	(0)(27)	0	1	1	Exclude file
Bin	(0)(27)	1	0	1	Exclude file
Bin	(0)(26)	0	1	1	Exclude file
Bin	(0)(26)	1	0	1	Exclude file
Bin	(0)(25)	0	1	1	Exclude file
Bin	(0)(25)	1	0	1	Exclude file
Bin	(0)(24)	0	1	1	Exclude file
Bin	(0)(24)	1	0	1	Exclude file
Bin	(0)(23)	0	1	1	Exclude file
Bin	(0)(23)	1	0	1	Exclude file
Bin	(0)(22)	0	1	1	Exclude file
Bin	(0)(22)	1	0	1	Exclude file
Bin	(0)(21)	0	1	1	Exclude file
Bin	(0)(21)	1	0	1	Exclude file
Bin	(0)(20)	0	1	1	Exclude file
Bin	(0)(20)	1	0	1	Exclude file
Bin	(0)(19)	0	1	1	Exclude file
Bin	(0)(19)	1	0	1	Exclude file
Bin	(0)(18)	0	1	1	Exclude file
Bin	(0)(18)	1	0	1	Exclude file
Bin	(0)(17)	0	1	1	Exclude file
Bin	(0)(17)	1	0	1	Exclude file
Bin	(0)(16)	0	1	1	Exclude file
Bin	(0)(16)	1	0	1	Exclude file
Bin	(0)(15)	0	1	1	Exclude file
Bin	(0)(15)	1	0	1	Exclude file
Bin	(0)(14)	0	1	1	Exclude file
Bin	(0)(14)	1	0	1	Exclude file
Bin	(0)(13)	0	1	1	Exclude file
Bin	(0)(13)	1	0	1	Exclude file
Bin	(0)(12)	0	1	1	Exclude file
Bin	(0)(12)	1	0	1	Exclude file
Bin	(0)(11)	0	1	1	Exclude file
Bin	(0)(11)	1	0	1	Exclude file
Bin	(0)(10)	0	1	1	Exclude file
Bin	(0)(10)	1	0	1	Exclude file
Bin	(0)(9)	0	1	1	Exclude file
Bin	(0)(9)	1	0	1	Exclude file
Bin	(0)(8)	0	1	1	Exclude file
Bin	(0)(8)	1	0	1	Exclude file
Bin	(0)(7)	0	1	1	Exclude file
Bin	(0)(7)	1	0	1	Exclude file
Bin	(0)(6)	0	1	1	Exclude file
Bin	(0)(6)	1	0	1	Exclude file
Bin	(0)(5)	0	1	1	Exclude file
Bin	(0)(5)	1	0	1	Exclude file
Bin	(0)(4)	0	1	1	Exclude file
Bin	(0)(4)	1	0	1	Exclude file
Bin	(0)(3)	0	1	1	Exclude file
Bin	(0)(3)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

RX_FULL

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_EMPTY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_FRAME_COUNT

	Element	From	To	Threshold	Excluded due to
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_MEM_FREE

	Element	From	To	Threshold	Excluded due to
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_READ_POINTER

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_WRITE_POINTER

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_DATA_OVERRUN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_MOF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_PARITY_ERROR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RXB_PORT_B_DATA_OUT

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_STATE

	Element	From	To	Threshold	Excluded due to
Bin	(7)(3)	0	1	1	Exclude file
Bin	(7)(3)	1	0	1	Exclude file
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(3)	0	1	1	Exclude file
Bin	(6)(3)	1	0	1	Exclude file
Bin	(6)(2)	0	1	1	Exclude file
Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
Bin	(6)(1)	1	0	1	Exclude file
Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
Bin	(5)(3)	0	1	1	Exclude file
Bin	(5)(3)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(3)	0	1	1	Exclude file
Bin	(4)(3)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(3)	0	1	1	Exclude file
Bin	(3)(3)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(3)	0	1	1	Exclude file
Bin	(2)(3)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(3)	0	1	1	Exclude file
Bin	(1)(3)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(3)	0	1	1	Exclude file
Bin	(0)(3)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

TXTB_PARITY_ERROR_VALID

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_BB_PARITY_ERROR

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRV_DELAY

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_STAT_RXI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_TXI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_EWLI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_DOI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_FCSI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_ALI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_BEI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_OFI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_RXFI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_BSI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_RBNEI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_STAT_TXBHCI_O

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_INT_ENA_SET_INT_ENA_SET_O

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_INT_MASK_SET_INT_MASK_SET_O

	Element	From	To	Threshold	Excluded due to
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Signal:

MR_CTRL_IN

	Element	From	To	Threshold	Excluded due to
Bin	DEVICE_ID_DEVICE_ID(15)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(14)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(13)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(12)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(11)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(10)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(9)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(8)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(7)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(6)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(5)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(4)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(3)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(2)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(1)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(0)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(7)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(6)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(5)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(4)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(3)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(2)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(1)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(0)	1	0	1	Exclude file
Bin	VERSION_VER_MAJOR(7)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(6)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(5)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(4)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(3)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(2)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(1)	1	0	1	Exclude file
Bin	VERSION_VER_MAJOR(0)	0	1	1	Exclude file
Bin	STATUS_STRGS	1	0	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(11)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(10)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(9)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(8)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(6)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(4)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(3)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(2)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(1)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(0)	0	1	1	Exclude file
Bin	TXTB_INFO_TXT_BUFFER_COUNT(0)	0	1	1	Exclude file
Bin	TS_INFO_TS_BITS(5)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(4)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(3)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(2)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(1)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(0)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(31)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(30)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(29)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(28)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(27)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(26)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(25)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(24)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(23)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(22)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(21)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(20)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(19)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(18)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(17)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(16)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(15)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(14)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(13)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(12)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(11)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(10)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(9)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(8)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(7)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(6)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(5)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(4)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(3)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(2)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(1)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(0)	1	0	1	Exclude file

Covered toggles:

Port:

RES_SOFT_N

	From	To	Count	Threshold
Bin	0	1	9645	1
Bin	1	0	8044	1

Port:

RES_CORE_N

	From	To	Count	Threshold
Bin	0	1	8084	1
Bin	1	0	8072	1

Port:

DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	22677	1
Bin	(31)	1	0	24278	1
Bin	(30)	0	1	24476	1
Bin	(30)	1	0	26077	1
Bin	(29)	0	1	24634	1
Bin	(29)	1	0	26235	1
Bin	(28)	0	1	31553	1
Bin	(28)	1	0	33154	1
Bin	(27)	0	1	35413	1
Bin	(27)	1	0	37014	1
Bin	(26)	0	1	31003	1
Bin	(26)	1	0	32604	1
Bin	(25)	0	1	49405	1
Bin	(25)	1	0	51006	1
Bin	(24)	0	1	39545	1
Bin	(24)	1	0	41146	1
Bin	(23)	0	1	49408	1
Bin	(23)	1	0	51009	1
Bin	(22)	0	1	123548	1
Bin	(22)	1	0	125149	1
Bin	(21)	0	1	39315	1
Bin	(21)	1	0	40916	1
Bin	(20)	0	1	52815	1
Bin	(20)	1	0	54416	1
Bin	(19)	0	1	49857	1
Bin	(19)	1	0	51458	1
Bin	(18)	0	1	303808	1
Bin	(18)	1	0	305409	1
Bin	(17)	0	1	120142	1
Bin	(17)	1	0	121743	1
Bin	(16)	0	1	134855	1
Bin	(16)	1	0	136456	1
Bin	(15)	0	1	168376	1
Bin	(15)	1	0	169977	1
Bin	(14)	0	1	577695	1
Bin	(14)	1	0	579296	1
Bin	(13)	0	1	131940	1
Bin	(13)	1	0	133541	1
Bin	(12)	0	1	189641	1
Bin	(12)	1	0	191242	1
Bin	(11)	0	1	148472	1
Bin	(11)	1	0	150073	1
Bin	(10)	0	1	1556677	1
Bin	(10)	1	0	1558278	1
Bin	(9)	0	1	347871	1
Bin	(9)	1	0	349472	1
Bin	(8)	0	1	3294824	1
Bin	(8)	1	0	3296425	1
Bin	(7)	0	1	971042	1
Bin	(7)	1	0	972643	1
Bin	(6)	0	1	3108317	1
Bin	(6)	1	0	3109918	1
Bin	(5)	0	1	1993440	1
Bin	(5)	1	0	1995041	1
Bin	(4)	0	1	3695765	1
Bin	(4)	1	0	3697366	1
Bin	(3)	0	1	4245985	1
Bin	(3)	1	0	4247586	1
Bin	(2)	0	1	949010	1
Bin	(2)	1	0	950611	1
Bin	(1)	0	1	1555900	1
Bin	(1)	1	0	1557501	1
Bin	(0)	0	1	1946672	1
Bin	(0)	1	0	1948273	1

Port:

MR_CTRL_OUT

	Element	From	To	Count	Threshold
Bin	MODE_RST	0	1	868	1
Bin	MODE_RST	1	0	32877	1
Bin	MODE_BMM	0	1	15	1
Bin	MODE_BMM	1	0	1616	1
Bin	MODE_STM	0	1	160	1
Bin	MODE_STM	1	0	1761	1
Bin	MODE_AFM	0	1	68	1
Bin	MODE_AFM	1	0	1669	1
Bin	MODE_FDE	0	1	1801	1
Bin	MODE_FDE	1	0	200	1
Bin	MODE_TTTM	0	1	55	1
Bin	MODE_TTTM	1	0	1656	1
Bin	MODE_ROM	0	1	51	1
Bin	MODE_ROM	1	0	1652	1
Bin	MODE_ACF	0	1	19	1
Bin	MODE_ACF	1	0	1620	1
Bin	MODE_TSTM	0	1	1027	1
Bin	MODE_TSTM	1	0	2627	1
Bin	MODE_RXBAM	0	1	1731	1
Bin	MODE_RXBAM	1	0	130	1
Bin	MODE_TXBBM	0	1	33	1
Bin	MODE_TXBBM	1	0	1634	1
Bin	MODE_SAM	0	1	55	1
Bin	MODE_SAM	1	0	1656	1
Bin	MODE_ERFM	0	1	153	1
Bin	MODE_ERFM	1	0	1754	1
Bin	SETTINGS_RTRLE	0	1	2454	1
Bin	SETTINGS_RTRLE	1	0	4055	1
Bin	SETTINGS_RTRTH(3)	0	1	22	1
Bin	SETTINGS_RTRTH(3)	1	0	1623	1
Bin	SETTINGS_RTRTH(2)	0	1	54	1
Bin	SETTINGS_RTRTH(2)	1	0	1655	1
Bin	SETTINGS_RTRTH(1)	0	1	22	1
Bin	SETTINGS_RTRTH(1)	1	0	1623	1
Bin	SETTINGS_RTRTH(0)	0	1	53	1
Bin	SETTINGS_RTRTH(0)	1	0	1654	1
Bin	SETTINGS_ILBP	0	1	130	1
Bin	SETTINGS_ILBP	1	0	1731	1
Bin	SETTINGS_ENA	0	1	6483	1
Bin	SETTINGS_ENA	1	0	8072	1
Bin	SETTINGS_NISOFD	0	1	130	1
Bin	SETTINGS_NISOFD	1	0	1731	1
Bin	SETTINGS_PEX	0	1	72	1
Bin	SETTINGS_PEX	1	0	1673	1
Bin	SETTINGS_TBFBO	0	1	2533	1
Bin	SETTINGS_TBFBO	1	0	944	1
Bin	SETTINGS_FDRF	0	1	4	1
Bin	SETTINGS_FDRF	1	0	1605	1
Bin	SETTINGS_PCHKE	0	1	124	1
Bin	SETTINGS_PCHKE	1	0	1725	1
Bin	COMMAND_RXRPMV	0	1	21	1
Bin	COMMAND_RXRPMV	1	0	3064	1
Bin	COMMAND_RRB	0	1	460	1
Bin	COMMAND_RRB	1	0	3064	1
Bin	COMMAND_CDO	0	1	20	1
Bin	COMMAND_CDO	1	0	3064	1
Bin	COMMAND_ERCRST	0	1	170	1
Bin	COMMAND_ERCRST	1	0	3064	1
Bin	COMMAND_RXFCRST	0	1	124	1
Bin	COMMAND_RXFCRST	1	0	3064	1
Bin	COMMAND_TXFCRST	0	1	124	1
Bin	COMMAND_TXFCRST	1	0	3064	1
Bin	COMMAND_CPEXS	0	1	60	1
Bin	COMMAND_CPEXS	1	0	3064	1
Bin	COMMAND_CRXPE	0	1	40	1
Bin	COMMAND_CRXPE	1	0	3064	1
Bin	COMMAND_CTXPE	0	1	440	1
Bin	COMMAND_CTXPE	1	0	3064	1
Bin	COMMAND_CTXDPE	0	1	40	1
Bin	COMMAND_CTXDPE	1	0	3064	1
Bin	INT_STAT_RXI	0	1	40	1
Bin	INT_STAT_RXI	1	0	1748	1
Bin	INT_STAT_TXI	0	1	42	1
Bin	INT_STAT_TXI	1	0	1748	1
Bin	INT_STAT_EWLI	0	1	30	1
Bin	INT_STAT_EWLI	1	0	1748	1
Bin	INT_STAT_DOI	0	1	16	1
Bin	INT_STAT_DOI	1	0	1748	1
Bin	INT_STAT_FCSI	0	1	80	1
Bin	INT_STAT_FCSI	1	0	1748	1
Bin	INT_STAT_ALI	0	1	5	1
Bin	INT_STAT_ALI	1	0	1748	1
Bin	INT_STAT_BEI	0	1	15	1
Bin	INT_STAT_BEI	1	0	1748	1
Bin	INT_STAT_OFI	0	1	5	1
Bin	INT_STAT_OFI	1	0	1748	1
Bin	INT_STAT_RXFI	0	1	15	1
Bin	INT_STAT_RXFI	1	0	1748	1
Bin	INT_STAT_BSI	0	1	43	1
Bin	INT_STAT_BSI	1	0	1748	1
Bin	INT_STAT_RBNEI	0	1	50	1
Bin	INT_STAT_RBNEI	1	0	1748	1
Bin	INT_STAT_TXBHCI	0	1	52	1
Bin	INT_STAT_TXBHCI	1	0	1748	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	2373	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	2409	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	2389	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	2424	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	2419	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	2419	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	2419	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	0	1	476	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	1	0	2209	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	0	1	512	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	1	0	2173	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	0	1	492	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	1	0	2193	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	1	0	2158	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	1	0	2163	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	1	0	2163	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	1	0	2163	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	66	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	2261	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	40	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	2287	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	50	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	2277	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	15	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	2312	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	2317	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	2317	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	0	1	409	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	1	0	2142	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	0	1	435	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	1	0	2116	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	0	1	425	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	1	0	2126	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	0	1	460	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	1	0	2091	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	1	0	2086	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	1	0	2086	1
Bin	BTR_PROP(6)	0	1	205	1
Bin	BTR_PROP(6)	1	0	1804	1
Bin	BTR_PROP(5)	0	1	313	1
Bin	BTR_PROP(5)	1	0	1911	1
Bin	BTR_PROP(4)	0	1	228	1
Bin	BTR_PROP(4)	1	0	1826	1
Bin	BTR_PROP(3)	0	1	272	1
Bin	BTR_PROP(3)	1	0	1870	1
Bin	BTR_PROP(2)	0	1	3820	1
Bin	BTR_PROP(2)	1	0	2220	1
Bin	BTR_PROP(1)	0	1	265	1
Bin	BTR_PROP(1)	1	0	1863	1
Bin	BTR_PROP(0)	0	1	1795	1
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Bin	BTR_PH1(5)	0	1	317	1
Bin	BTR_PH1(5)	1	0	1916	1
Bin	BTR_PH1(4)	0	1	253	1
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Bin	BTR_PH1(3)	0	1	263	1
Bin	BTR_PH1(3)	1	0	1862	1
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Bin	BTR_PH1(1)	0	1	1925	1
Bin	BTR_PH1(1)	1	0	325	1
Bin	BTR_PH1(0)	0	1	2091	1
Bin	BTR_PH1(0)	1	0	492	1
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Bin	BTR_PH2(5)	1	0	1805	1
Bin	BTR_PH2(4)	0	1	346	1
Bin	BTR_PH2(4)	1	0	1944	1
Bin	BTR_PH2(3)	0	1	315	1
Bin	BTR_PH2(3)	1	0	1914	1
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Bin	BTR_PH2(2)	1	0	2275	1
Bin	BTR_PH2(1)	0	1	3412	1
Bin	BTR_PH2(1)	1	0	5003	1
Bin	BTR_PH2(0)	0	1	2158	1
Bin	BTR_PH2(0)	1	0	557	1
Bin	BTR_BRP(7)	0	1	14	1
Bin	BTR_BRP(7)	1	0	1615	1
Bin	BTR_BRP(6)	0	1	12	1
Bin	BTR_BRP(6)	1	0	1613	1
Bin	BTR_BRP(5)	0	1	12	1
Bin	BTR_BRP(5)	1	0	1613	1
Bin	BTR_BRP(4)	0	1	16	1
Bin	BTR_BRP(4)	1	0	1617	1
Bin	BTR_BRP(3)	0	1	4831	1
Bin	BTR_BRP(3)	1	0	3242	1
Bin	BTR_BRP(2)	0	1	929	1
Bin	BTR_BRP(2)	1	0	2523	1
Bin	BTR_BRP(1)	0	1	4762	1
Bin	BTR_BRP(1)	1	0	3170	1
Bin	BTR_BRP(0)	0	1	2316	1
Bin	BTR_BRP(0)	1	0	3914	1
Bin	BTR_SJW(4)	0	1	209	1
Bin	BTR_SJW(4)	1	0	1807	1
Bin	BTR_SJW(3)	0	1	266	1
Bin	BTR_SJW(3)	1	0	1864	1
Bin	BTR_SJW(2)	0	1	965	1
Bin	BTR_SJW(2)	1	0	2563	1
Bin	BTR_SJW(1)	0	1	2623	1
Bin	BTR_SJW(1)	1	0	1031	1
Bin	BTR_SJW(0)	0	1	3116	1
Bin	BTR_SJW(0)	1	0	4714	1
Bin	BTR_FD_PROP_FD(5)	0	1	243	1
Bin	BTR_FD_PROP_FD(5)	1	0	1841	1
Bin	BTR_FD_PROP_FD(4)	0	1	291	1
Bin	BTR_FD_PROP_FD(4)	1	0	1889	1
Bin	BTR_FD_PROP_FD(3)	0	1	273	1
Bin	BTR_FD_PROP_FD(3)	1	0	1871	1
Bin	BTR_FD_PROP_FD(2)	0	1	1195	1
Bin	BTR_FD_PROP_FD(2)	1	0	2784	1
Bin	BTR_FD_PROP_FD(1)	0	1	4706	1
Bin	BTR_FD_PROP_FD(1)	1	0	3114	1
Bin	BTR_FD_PROP_FD(0)	0	1	3890	1
Bin	BTR_FD_PROP_FD(0)	1	0	2289	1
Bin	BTR_FD_PH1_FD(4)	0	1	253	1
Bin	BTR_FD_PH1_FD(4)	1	0	1852	1
Bin	BTR_FD_PH1_FD(3)	0	1	299	1
Bin	BTR_FD_PH1_FD(3)	1	0	1898	1
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Bin	BTR_FD_PH1_FD(2)	1	0	2766	1
Bin	BTR_FD_PH1_FD(1)	0	1	1704	1
Bin	BTR_FD_PH1_FD(1)	1	0	104	1
Bin	BTR_FD_PH1_FD(0)	0	1	3847	1
Bin	BTR_FD_PH1_FD(0)	1	0	2247	1
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Bin	BTR_FD_PH2_FD(4)	1	0	1880	1
Bin	BTR_FD_PH2_FD(3)	0	1	317	1
Bin	BTR_FD_PH2_FD(3)	1	0	1916	1
Bin	BTR_FD_PH2_FD(2)	0	1	1209	1
Bin	BTR_FD_PH2_FD(2)	1	0	2799	1
Bin	BTR_FD_PH2_FD(1)	0	1	1725	1
Bin	BTR_FD_PH2_FD(1)	1	0	125	1
Bin	BTR_FD_PH2_FD(0)	0	1	3868	1
Bin	BTR_FD_PH2_FD(0)	1	0	2267	1
Bin	BTR_FD_BRP_FD(7)	0	1	18	1
Bin	BTR_FD_BRP_FD(7)	1	0	1619	1
Bin	BTR_FD_BRP_FD(6)	0	1	30	1
Bin	BTR_FD_BRP_FD(6)	1	0	1631	1
Bin	BTR_FD_BRP_FD(5)	0	1	17	1
Bin	BTR_FD_BRP_FD(5)	1	0	1618	1
Bin	BTR_FD_BRP_FD(4)	0	1	27	1
Bin	BTR_FD_BRP_FD(4)	1	0	1628	1
Bin	BTR_FD_BRP_FD(3)	0	1	28	1
Bin	BTR_FD_BRP_FD(3)	1	0	1629	1
Bin	BTR_FD_BRP_FD(2)	0	1	4843	1
Bin	BTR_FD_BRP_FD(2)	1	0	3254	1
Bin	BTR_FD_BRP_FD(1)	0	1	764	1
Bin	BTR_FD_BRP_FD(1)	1	0	2363	1
Bin	BTR_FD_BRP_FD(0)	0	1	2598	1
Bin	BTR_FD_BRP_FD(0)	1	0	4189	1
Bin	BTR_FD_SJW_FD(4)	0	1	238	1
Bin	BTR_FD_SJW_FD(4)	1	0	1836	1
Bin	BTR_FD_SJW_FD(3)	0	1	282	1
Bin	BTR_FD_SJW_FD(3)	1	0	1880	1
Bin	BTR_FD_SJW_FD(2)	0	1	924	1
Bin	BTR_FD_SJW_FD(2)	1	0	2522	1
Bin	BTR_FD_SJW_FD(1)	0	1	2557	1
Bin	BTR_FD_SJW_FD(1)	1	0	965	1
Bin	BTR_FD_SJW_FD(0)	0	1	959	1
Bin	BTR_FD_SJW_FD(0)	1	0	2557	1
Bin	EWL_EW_LIMIT(7)	0	1	89	1
Bin	EWL_EW_LIMIT(7)	1	0	1690	1
Bin	EWL_EW_LIMIT(6)	0	1	1680	1
Bin	EWL_EW_LIMIT(6)	1	0	79	1
Bin	EWL_EW_LIMIT(5)	0	1	1672	1
Bin	EWL_EW_LIMIT(5)	1	0	71	1
Bin	EWL_EW_LIMIT(4)	0	1	78	1
Bin	EWL_EW_LIMIT(4)	1	0	1679	1
Bin	EWL_EW_LIMIT(3)	0	1	82	1
Bin	EWL_EW_LIMIT(3)	1	0	1683	1
Bin	EWL_EW_LIMIT(2)	0	1	85	1
Bin	EWL_EW_LIMIT(2)	1	0	1686	1
Bin	EWL_EW_LIMIT(1)	0	1	86	1
Bin	EWL_EW_LIMIT(1)	1	0	1687	1
Bin	EWL_EW_LIMIT(0)	0	1	87	1
Bin	EWL_EW_LIMIT(0)	1	0	1688	1
Bin	ERP_ERP_LIMIT(7)	0	1	1743	1
Bin	ERP_ERP_LIMIT(7)	1	0	142	1
Bin	ERP_ERP_LIMIT(6)	0	1	24	1
Bin	ERP_ERP_LIMIT(6)	1	0	1625	1
Bin	ERP_ERP_LIMIT(5)	0	1	21	1
Bin	ERP_ERP_LIMIT(5)	1	0	1622	1
Bin	ERP_ERP_LIMIT(4)	0	1	27	1
Bin	ERP_ERP_LIMIT(4)	1	0	1628	1
Bin	ERP_ERP_LIMIT(3)	0	1	21	1
Bin	ERP_ERP_LIMIT(3)	1	0	1622	1
Bin	ERP_ERP_LIMIT(2)	0	1	25	1
Bin	ERP_ERP_LIMIT(2)	1	0	1626	1
Bin	ERP_ERP_LIMIT(1)	0	1	23	1
Bin	ERP_ERP_LIMIT(1)	1	0	1624	1
Bin	ERP_ERP_LIMIT(0)	0	1	21	1
Bin	ERP_ERP_LIMIT(0)	1	0	1622	1
Bin	CTR_PRES_CTPV(8)	0	1	256	1
Bin	CTR_PRES_CTPV(8)	1	0	1857	1
Bin	CTR_PRES_CTPV(7)	0	1	2687	1
Bin	CTR_PRES_CTPV(7)	1	0	4288	1
Bin	CTR_PRES_CTPV(6)	0	1	703	1
Bin	CTR_PRES_CTPV(6)	1	0	2304	1
Bin	CTR_PRES_CTPV(5)	0	1	2728	1
Bin	CTR_PRES_CTPV(5)	1	0	4329	1
Bin	CTR_PRES_CTPV(4)	0	1	2839	1
Bin	CTR_PRES_CTPV(4)	1	0	4440	1
Bin	CTR_PRES_CTPV(3)	0	1	919	1
Bin	CTR_PRES_CTPV(3)	1	0	2520	1
Bin	CTR_PRES_CTPV(2)	0	1	2891	1
Bin	CTR_PRES_CTPV(2)	1	0	4492	1
Bin	CTR_PRES_CTPV(1)	0	1	1003	1
Bin	CTR_PRES_CTPV(1)	1	0	2604	1
Bin	CTR_PRES_CTPV(0)	0	1	750	1
Bin	CTR_PRES_CTPV(0)	1	0	2351	1
Bin	CTR_PRES_PTX	0	1	19364	1
Bin	CTR_PRES_PTX	1	0	45544	1
Bin	CTR_PRES_PRX	0	1	19759	1
Bin	CTR_PRES_PRX	1	0	45544	1
Bin	CTR_PRES_ENORM	0	1	6608	1
Bin	CTR_PRES_ENORM	1	0	45544	1
Bin	CTR_PRES_EFD	0	1	6608	1
Bin	CTR_PRES_EFD	1	0	45544	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	0	1	390	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	1	0	1991	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	0	1	365	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	1	0	1966	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	0	1	342	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	1	0	1943	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	0	1	328	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	1	0	1929	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	0	1	399	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	1	0	2000	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	0	1	362	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	1	0	1963	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	0	1	367	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	1	0	1968	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	0	1	345	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	1	0	1946	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	0	1	394	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	1	0	1995	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	0	1	380	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	1	0	1981	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	0	1	388	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	1	0	1989	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	0	1	104	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	1	0	1705	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	0	1	98	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	1	0	1699	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	0	1	98	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	1	0	1699	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	0	1	130	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	1	0	1731	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	0	1	90	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	1	0	1691	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	0	1	101	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	1	0	1702	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	0	1	77	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	1	0	1678	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	0	1	246	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	1	0	1847	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	0	1	285	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	1	0	1886	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	0	1	238	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	1	0	1839	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	0	1	257	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	1	0	1858	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	0	1	257	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	1	0	1858	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	0	1	251	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	1	0	1852	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	0	1	275	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	1	0	1876	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	0	1	286	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	1	0	1887	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	0	1	264	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	1	0	1865	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	0	1	244	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	1	0	1845	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	0	1	282	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	1	0	1883	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	0	1	764	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	1	0	2365	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	0	1	799	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	1	0	2400	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	0	1	820	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	1	0	2421	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	0	1	809	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	1	0	2410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	0	1	766	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	1	0	2367	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	0	1	806	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	1	0	2407	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	0	1	808	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	1	0	2409	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	0	1	794	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	1	0	2395	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	0	1	833	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	1	0	2434	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	0	1	823	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	1	0	2424	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	0	1	823	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	1	0	2424	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	1	0	2011	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	0	1	385	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	1	0	1986	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	0	1	391	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	1	0	1992	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	0	1	449	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	1	0	2050	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	1	0	1998	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	0	1	380	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	1	0	1981	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	0	1	442	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	1	0	2043	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	0	1	394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	1	0	1995	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	0	1	398	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	1	0	1999	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	0	1	377	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	1	0	1978	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	0	1	360	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	1	0	1961	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	0	1	393	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	1	0	1994	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	0	1	403	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	1	0	2004	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	1	0	1998	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	1	0	2011	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	0	1	402	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	1	0	2003	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	0	1	422	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	1	0	2023	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	0	1	95	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	1	0	1696	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	0	1	103	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	1	0	1704	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	0	1	101	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	1	0	1702	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	0	1	104	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	1	0	1705	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	0	1	90	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	1	0	1691	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	0	1	92	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	1	0	1693	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	0	1	81	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	1	0	1682	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	0	1	107	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	1	0	1708	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	0	1	16	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	1	0	1617	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	0	1	19	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	1	0	1620	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	0	1	28	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	1	0	1629	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	0	1	37	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	1	0	1638	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	0	1	35	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	1	0	1636	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	0	1	23	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	1	0	1624	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	0	1	21	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	1	0	1622	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	0	1	60	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	1	0	1661	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	1	0	1671	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	1	0	1668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	1	0	1671	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	0	1	63	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	1	0	1664	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	1	0	1671	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	1	0	1668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	1	0	1671	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	0	1	196	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	1	0	1797	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	0	1	196	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	1	0	1797	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	0	1	217	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	1	0	1818	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	0	1	183	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	1	0	1784	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	0	1	218	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	1	0	1819	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	0	1	206	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	1	0	1807	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	0	1	200	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	1	0	1801	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	0	1	225	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	1	0	1826	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	0	1	229	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	1	0	1830	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	0	1	201	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	1	0	1802	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	0	1	209	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	1	0	1810	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	0	1	87	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	1	0	1688	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	0	1	104	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	1	0	1705	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	0	1	91	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	1	0	1692	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	0	1	103	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	1	0	1704	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	0	1	108	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	1	0	1709	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	0	1	107	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	1	0	1708	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	0	1	93	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	1	0	1694	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	0	1	98	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	1	0	1699	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	0	1	96	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	1	0	1697	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	0	1	86	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	1	0	1687	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	0	1	114	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	1	0	1715	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	0	1	92	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	1	0	1693	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	0	1	115	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	1	0	1716	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	0	1	93	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	1	0	1694	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	0	1	108	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	1	0	1709	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	0	1	85	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	1	0	1686	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	0	1	95	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	1	0	1696	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	0	1	89	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	1	0	1690	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	0	1	82	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	1	0	1683	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	0	1	108	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	1	0	1709	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	0	1	79	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	1	0	1680	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	0	1	101	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	1	0	1702	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	0	1	105	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	1	0	1706	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	0	1	92	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	1	0	1693	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	0	1	85	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	1	0	1686	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	0	1	99	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	1	0	1700	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	0	1	19	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	1	0	1620	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	0	1	20	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	1	0	1621	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	0	1	27	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	1	0	1628	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	0	1	28	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	1	0	1629	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	0	1	22	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	1	0	1623	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	0	1	14	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	1	0	1615	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	1	0	1668	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	1	0	1668	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	0	1	68	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	1	0	1669	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	1	0	1664	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	1	0	1664	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	0	1	68	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	1	0	1669	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	0	1	60	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	1	0	1661	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	0	1	77	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	1	0	1678	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	1	0	1668	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	0	1	184	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	1	0	1785	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	0	1	188	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	1	0	1789	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	0	1	201	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	1	0	1802	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	0	1	196	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	1	0	1797	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	0	1	193	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	1	0	1794	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	0	1	190	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	1	0	1791	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	0	1	204	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	1	0	1805	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	0	1	225	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	1	0	1826	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	0	1	201	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	1	0	1802	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	0	1	206	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	1	0	1807	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	0	1	94	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	1	0	1695	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	0	1	97	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	1	0	1698	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	1	0	1705	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	0	1	93	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	1	0	1694	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	0	1	107	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	1	0	1708	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	1	0	1705	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	0	1	113	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	1	0	1714	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	0	1	96	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	1	0	1697	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	0	1	91	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	1	0	1692	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	0	1	90	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	1	0	1691	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	0	1	99	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	1	0	1700	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	0	1	89	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	1	0	1690	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	0	1	107	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	1	0	1708	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	1	0	1711	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	1	0	1711	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	1	0	1602	1
Bin	FILTER_CONTROL_FANB	0	1	2052	1
Bin	FILTER_CONTROL_FANB	1	0	451	1
Bin	FILTER_CONTROL_FANE	0	1	2029	1
Bin	FILTER_CONTROL_FANE	1	0	428	1
Bin	FILTER_CONTROL_FAFB	0	1	2060	1
Bin	FILTER_CONTROL_FAFB	1	0	459	1
Bin	FILTER_CONTROL_FAFE	0	1	2029	1
Bin	FILTER_CONTROL_FAFE	1	0	428	1
Bin	FILTER_CONTROL_FBNB	0	1	106	1
Bin	FILTER_CONTROL_FBNB	1	0	1707	1
Bin	FILTER_CONTROL_FBNE	0	1	105	1
Bin	FILTER_CONTROL_FBNE	1	0	1706	1
Bin	FILTER_CONTROL_FBFB	0	1	107	1
Bin	FILTER_CONTROL_FBFB	1	0	1708	1
Bin	FILTER_CONTROL_FBFE	0	1	105	1
Bin	FILTER_CONTROL_FBFE	1	0	1706	1
Bin	FILTER_CONTROL_FCNB	0	1	106	1
Bin	FILTER_CONTROL_FCNB	1	0	1707	1
Bin	FILTER_CONTROL_FCNE	0	1	105	1
Bin	FILTER_CONTROL_FCNE	1	0	1706	1
Bin	FILTER_CONTROL_FCFB	0	1	107	1
Bin	FILTER_CONTROL_FCFB	1	0	1708	1
Bin	FILTER_CONTROL_FCFE	0	1	105	1
Bin	FILTER_CONTROL_FCFE	1	0	1706	1
Bin	FILTER_CONTROL_FRNB	0	1	6	1
Bin	FILTER_CONTROL_FRNB	1	0	1607	1
Bin	FILTER_CONTROL_FRNE	0	1	5	1
Bin	FILTER_CONTROL_FRNE	1	0	1606	1
Bin	FILTER_CONTROL_FRFB	0	1	6	1
Bin	FILTER_CONTROL_FRFB	1	0	1607	1
Bin	FILTER_CONTROL_FRFE	0	1	5	1
Bin	FILTER_CONTROL_FRFE	1	0	1606	1
Bin	RX_SETTINGS_RTSOP	0	1	5	1
Bin	RX_SETTINGS_RTSOP	1	0	1606	1
Bin	RX_DATA_READ	0	1	51013	1
Bin	RX_DATA_READ	1	0	52614	1
Bin	TX_COMMAND_TXCE	0	1	354	1
Bin	TX_COMMAND_TXCE	1	0	25291	1
Bin	TX_COMMAND_TXCR	0	1	21602	1
Bin	TX_COMMAND_TXCR	1	0	25291	1
Bin	TX_COMMAND_TXCA	0	1	1734	1
Bin	TX_COMMAND_TXCA	1	0	25291	1
Bin	TX_COMMAND_TXB1	0	1	6554	1
Bin	TX_COMMAND_TXB1	1	0	8151	1
Bin	TX_COMMAND_TXB2	0	1	5585	1
Bin	TX_COMMAND_TXB2	1	0	7186	1
Bin	TX_COMMAND_TXB3	0	1	319	1
Bin	TX_COMMAND_TXB3	1	0	1920	1
Bin	TX_COMMAND_TXB4	0	1	348	1
Bin	TX_COMMAND_TXB4	1	0	1949	1
Bin	TX_COMMAND_TXB5	0	1	84	1
Bin	TX_COMMAND_TXB5	1	0	1685	1
Bin	TX_COMMAND_TXB6	0	1	64	1
Bin	TX_COMMAND_TXB6	1	0	1665	1
Bin	TX_COMMAND_TXB7	0	1	76	1
Bin	TX_COMMAND_TXB7	1	0	1677	1
Bin	TX_COMMAND_TXB8	0	1	68	1
Bin	TX_COMMAND_TXB8	1	0	1669	1
Bin	TX_PRIORITY_TXT1P(2)	0	1	111	1
Bin	TX_PRIORITY_TXT1P(2)	1	0	1712	1
Bin	TX_PRIORITY_TXT1P(1)	0	1	113	1
Bin	TX_PRIORITY_TXT1P(1)	1	0	1714	1
Bin	TX_PRIORITY_TXT1P(0)	0	1	1721	1
Bin	TX_PRIORITY_TXT1P(0)	1	0	120	1
Bin	TX_PRIORITY_TXT2P(2)	0	1	93	1
Bin	TX_PRIORITY_TXT2P(2)	1	0	1694	1
Bin	TX_PRIORITY_TXT2P(1)	0	1	121	1
Bin	TX_PRIORITY_TXT2P(1)	1	0	1722	1
Bin	TX_PRIORITY_TXT2P(0)	0	1	119	1
Bin	TX_PRIORITY_TXT2P(0)	1	0	1720	1
Bin	TX_PRIORITY_TXT3P(2)	0	1	84	1
Bin	TX_PRIORITY_TXT3P(2)	1	0	1685	1
Bin	TX_PRIORITY_TXT3P(1)	0	1	92	1
Bin	TX_PRIORITY_TXT3P(1)	1	0	1693	1
Bin	TX_PRIORITY_TXT3P(0)	0	1	102	1
Bin	TX_PRIORITY_TXT3P(0)	1	0	1703	1
Bin	TX_PRIORITY_TXT4P(2)	0	1	85	1
Bin	TX_PRIORITY_TXT4P(2)	1	0	1686	1
Bin	TX_PRIORITY_TXT4P(1)	0	1	100	1
Bin	TX_PRIORITY_TXT4P(1)	1	0	1701	1
Bin	TX_PRIORITY_TXT4P(0)	0	1	87	1
Bin	TX_PRIORITY_TXT4P(0)	1	0	1688	1
Bin	TX_PRIORITY_TXT5P(2)	0	1	27	1
Bin	TX_PRIORITY_TXT5P(2)	1	0	1628	1
Bin	TX_PRIORITY_TXT5P(1)	0	1	29	1
Bin	TX_PRIORITY_TXT5P(1)	1	0	1630	1
Bin	TX_PRIORITY_TXT5P(0)	0	1	22	1
Bin	TX_PRIORITY_TXT5P(0)	1	0	1623	1
Bin	TX_PRIORITY_TXT6P(2)	0	1	17	1
Bin	TX_PRIORITY_TXT6P(2)	1	0	1618	1
Bin	TX_PRIORITY_TXT6P(1)	0	1	19	1
Bin	TX_PRIORITY_TXT6P(1)	1	0	1620	1
Bin	TX_PRIORITY_TXT6P(0)	0	1	23	1
Bin	TX_PRIORITY_TXT6P(0)	1	0	1624	1
Bin	TX_PRIORITY_TXT7P(2)	0	1	23	1
Bin	TX_PRIORITY_TXT7P(2)	1	0	1624	1
Bin	TX_PRIORITY_TXT7P(1)	0	1	22	1
Bin	TX_PRIORITY_TXT7P(1)	1	0	1623	1
Bin	TX_PRIORITY_TXT7P(0)	0	1	30	1
Bin	TX_PRIORITY_TXT7P(0)	1	0	1631	1
Bin	TX_PRIORITY_TXT8P(2)	0	1	25	1
Bin	TX_PRIORITY_TXT8P(2)	1	0	1626	1
Bin	TX_PRIORITY_TXT8P(1)	0	1	25	1
Bin	TX_PRIORITY_TXT8P(1)	1	0	1626	1
Bin	TX_PRIORITY_TXT8P(0)	0	1	20	1
Bin	TX_PRIORITY_TXT8P(0)	1	0	1621	1
Bin	SSP_CFG_SSP_OFFSET(7)	0	1	25	1
Bin	SSP_CFG_SSP_OFFSET(7)	1	0	1626	1
Bin	SSP_CFG_SSP_OFFSET(6)	0	1	27	1
Bin	SSP_CFG_SSP_OFFSET(6)	1	0	1628	1
Bin	SSP_CFG_SSP_OFFSET(5)	0	1	46	1
Bin	SSP_CFG_SSP_OFFSET(5)	1	0	1647	1
Bin	SSP_CFG_SSP_OFFSET(4)	0	1	53	1
Bin	SSP_CFG_SSP_OFFSET(4)	1	0	1654	1
Bin	SSP_CFG_SSP_OFFSET(3)	0	1	4303	1
Bin	SSP_CFG_SSP_OFFSET(3)	1	0	2714	1
Bin	SSP_CFG_SSP_OFFSET(2)	0	1	527	1
Bin	SSP_CFG_SSP_OFFSET(2)	1	0	2128	1
Bin	SSP_CFG_SSP_OFFSET(1)	0	1	2900	1
Bin	SSP_CFG_SSP_OFFSET(1)	1	0	1311	1
Bin	SSP_CFG_SSP_OFFSET(0)	0	1	2397	1
Bin	SSP_CFG_SSP_OFFSET(0)	1	0	3998	1
Bin	SSP_CFG_SSP_SRC(1)	0	1	45	1
Bin	SSP_CFG_SSP_SRC(1)	1	0	1646	1
Bin	SSP_CFG_SSP_SRC(0)	0	1	814	1
Bin	SSP_CFG_SSP_SRC(0)	1	0	2403	1

Port:

MR_TST_OUT

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32324	1
Bin	TST_CONTROL_TWRSTB	1	0	35216	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	47001	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	47001	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	47001	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	47001	1
Bin	TST_DEST_TST_ADDR(11)	0	1	325	1
Bin	TST_DEST_TST_ADDR(11)	1	0	47290	1
Bin	TST_DEST_TST_ADDR(10)	0	1	645	1
Bin	TST_DEST_TST_ADDR(10)	1	0	47610	1
Bin	TST_DEST_TST_ADDR(9)	0	1	1285	1
Bin	TST_DEST_TST_ADDR(9)	1	0	48250	1
Bin	TST_DEST_TST_ADDR(8)	0	1	2565	1
Bin	TST_DEST_TST_ADDR(8)	1	0	49530	1
Bin	TST_DEST_TST_ADDR(7)	0	1	5125	1
Bin	TST_DEST_TST_ADDR(7)	1	0	52090	1
Bin	TST_DEST_TST_ADDR(6)	0	1	11205	1
Bin	TST_DEST_TST_ADDR(6)	1	0	58077	1
Bin	TST_DEST_TST_ADDR(5)	0	1	22405	1
Bin	TST_DEST_TST_ADDR(5)	1	0	69277	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3615	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5216	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5035	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6636	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10345	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11946	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22457	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24058	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44877	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46478	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	375	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1976	1
Bin	TST_DEST_TST_MTGT(1)	0	1	517	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2118	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1479	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3080	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1508	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3109	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1591	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3192	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1642	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3243	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1637	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3238	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1645	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3246	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1692	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3293	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1558	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3159	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1525	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3126	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1560	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3161	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3255	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3255	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1640	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3241	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1672	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3273	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1556	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3157	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1518	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3119	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3130	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1616	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3217	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1671	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3272	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1638	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3239	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1709	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3310	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1561	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3162	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1564	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3165	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1568	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3169	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1667	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3268	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1663	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3264	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1642	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3243	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1675	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3276	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1719	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3320	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1604	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3205	1

Port:

CC_STAT

	Element	From	To	Count	Threshold
Bin	IS_ERR_ACTIVE	0	1	8426	1
Bin	IS_ERR_ACTIVE	1	0	8415	1
Bin	IS_ERR_PASSIVE	0	1	771	1
Bin	IS_ERR_PASSIVE	1	0	2372	1
Bin	IS_BUS_OFF	0	1	8227	1
Bin	IS_BUS_OFF	1	0	8238	1
Bin	IS_TRANSMITTER	0	1	20560	1
Bin	IS_TRANSMITTER	1	0	22161	1
Bin	IS_RECEIVER	0	1	30873	1
Bin	IS_RECEIVER	1	0	32467	1
Bin	IS_IDLE	0	1	56100	1
Bin	IS_IDLE	1	0	57697	1
Bin	TX_ERR_CTR(8)	0	1	249	1
Bin	TX_ERR_CTR(8)	1	0	1850	1
Bin	TX_ERR_CTR(7)	0	1	517	1
Bin	TX_ERR_CTR(7)	1	0	2118	1
Bin	TX_ERR_CTR(6)	0	1	501	1
Bin	TX_ERR_CTR(6)	1	0	2102	1
Bin	TX_ERR_CTR(5)	0	1	805	1
Bin	TX_ERR_CTR(5)	1	0	2406	1
Bin	TX_ERR_CTR(4)	0	1	1933	1
Bin	TX_ERR_CTR(4)	1	0	3534	1
Bin	TX_ERR_CTR(3)	0	1	12743	1
Bin	TX_ERR_CTR(3)	1	0	14344	1
Bin	TX_ERR_CTR(2)	0	1	2955	1
Bin	TX_ERR_CTR(2)	1	0	4556	1
Bin	TX_ERR_CTR(1)	0	1	3324	1
Bin	TX_ERR_CTR(1)	1	0	4925	1
Bin	TX_ERR_CTR(0)	0	1	3524	1
Bin	TX_ERR_CTR(0)	1	0	5125	1
Bin	RX_ERR_CTR(8)	0	1	130	1
Bin	RX_ERR_CTR(8)	1	0	1731	1
Bin	RX_ERR_CTR(7)	0	1	350	1
Bin	RX_ERR_CTR(7)	1	0	1951	1
Bin	RX_ERR_CTR(6)	0	1	255	1
Bin	RX_ERR_CTR(6)	1	0	1854	1
Bin	RX_ERR_CTR(5)	0	1	363	1
Bin	RX_ERR_CTR(5)	1	0	1963	1
Bin	RX_ERR_CTR(4)	0	1	497	1
Bin	RX_ERR_CTR(4)	1	0	2098	1
Bin	RX_ERR_CTR(3)	0	1	685	1
Bin	RX_ERR_CTR(3)	1	0	2285	1
Bin	RX_ERR_CTR(2)	0	1	617	1
Bin	RX_ERR_CTR(2)	1	0	2218	1
Bin	RX_ERR_CTR(1)	0	1	1191	1
Bin	RX_ERR_CTR(1)	1	0	2792	1
Bin	RX_ERR_CTR(0)	0	1	11216	1
Bin	RX_ERR_CTR(0)	1	0	12809	1
Bin	STATUS_PEXS	0	1	75	1
Bin	STATUS_PEXS	1	0	1676	1
Bin	NORM_ERR_CTR(15)	0	1	69	1
Bin	NORM_ERR_CTR(15)	1	0	1667	1
Bin	NORM_ERR_CTR(14)	0	1	67	1
Bin	NORM_ERR_CTR(14)	1	0	1668	1
Bin	NORM_ERR_CTR(13)	0	1	64	1
Bin	NORM_ERR_CTR(13)	1	0	1661	1
Bin	NORM_ERR_CTR(12)	0	1	62	1
Bin	NORM_ERR_CTR(12)	1	0	1659	1
Bin	NORM_ERR_CTR(11)	0	1	64	1
Bin	NORM_ERR_CTR(11)	1	0	1664	1
Bin	NORM_ERR_CTR(10)	0	1	69	1
Bin	NORM_ERR_CTR(10)	1	0	1668	1
Bin	NORM_ERR_CTR(9)	0	1	63	1
Bin	NORM_ERR_CTR(9)	1	0	1662	1
Bin	NORM_ERR_CTR(8)	0	1	71	1
Bin	NORM_ERR_CTR(8)	1	0	1671	1
Bin	NORM_ERR_CTR(7)	0	1	75	1
Bin	NORM_ERR_CTR(7)	1	0	1673	1
Bin	NORM_ERR_CTR(6)	0	1	97	1
Bin	NORM_ERR_CTR(6)	1	0	1696	1
Bin	NORM_ERR_CTR(5)	0	1	155	1
Bin	NORM_ERR_CTR(5)	1	0	1752	1
Bin	NORM_ERR_CTR(4)	0	1	276	1
Bin	NORM_ERR_CTR(4)	1	0	1876	1
Bin	NORM_ERR_CTR(3)	0	1	608	1
Bin	NORM_ERR_CTR(3)	1	0	2205	1
Bin	NORM_ERR_CTR(2)	0	1	1361	1
Bin	NORM_ERR_CTR(2)	1	0	2958	1
Bin	NORM_ERR_CTR(1)	0	1	3082	1
Bin	NORM_ERR_CTR(1)	1	0	4678	1
Bin	NORM_ERR_CTR(0)	0	1	11727	1
Bin	NORM_ERR_CTR(0)	1	0	13323	1
Bin	DATA_ERR_CTR(15)	0	1	63	1
Bin	DATA_ERR_CTR(15)	1	0	1661	1
Bin	DATA_ERR_CTR(14)	0	1	68	1
Bin	DATA_ERR_CTR(14)	1	0	1667	1
Bin	DATA_ERR_CTR(13)	0	1	67	1
Bin	DATA_ERR_CTR(13)	1	0	1665	1
Bin	DATA_ERR_CTR(12)	0	1	65	1
Bin	DATA_ERR_CTR(12)	1	0	1665	1
Bin	DATA_ERR_CTR(11)	0	1	61	1
Bin	DATA_ERR_CTR(11)	1	0	1658	1
Bin	DATA_ERR_CTR(10)	0	1	64	1
Bin	DATA_ERR_CTR(10)	1	0	1661	1
Bin	DATA_ERR_CTR(9)	0	1	75	1
Bin	DATA_ERR_CTR(9)	1	0	1673	1
Bin	DATA_ERR_CTR(8)	0	1	85	1
Bin	DATA_ERR_CTR(8)	1	0	1682	1
Bin	DATA_ERR_CTR(7)	0	1	98	1
Bin	DATA_ERR_CTR(7)	1	0	1696	1
Bin	DATA_ERR_CTR(6)	0	1	133	1
Bin	DATA_ERR_CTR(6)	1	0	1732	1
Bin	DATA_ERR_CTR(5)	0	1	209	1
Bin	DATA_ERR_CTR(5)	1	0	1805	1
Bin	DATA_ERR_CTR(4)	0	1	352	1
Bin	DATA_ERR_CTR(4)	1	0	1952	1
Bin	DATA_ERR_CTR(3)	0	1	680	1
Bin	DATA_ERR_CTR(3)	1	0	2278	1
Bin	DATA_ERR_CTR(2)	0	1	1295	1
Bin	DATA_ERR_CTR(2)	1	0	2895	1
Bin	DATA_ERR_CTR(1)	0	1	2523	1
Bin	DATA_ERR_CTR(1)	1	0	4120	1
Bin	DATA_ERR_CTR(0)	0	1	5589	1
Bin	DATA_ERR_CTR(0)	1	0	7187	1
Bin	ERR_TYPE(2)	0	1	800	1
Bin	ERR_TYPE(2)	1	0	2399	1
Bin	ERR_TYPE(1)	0	1	1263	1
Bin	ERR_TYPE(1)	1	0	2861	1
Bin	ERR_TYPE(0)	0	1	333	1
Bin	ERR_TYPE(0)	1	0	1933	1
Bin	ERR_ERP	0	1	295	1
Bin	ERR_ERP	1	0	1896	1
Bin	ERR_POS(3)	0	1	4188	1
Bin	ERR_POS(3)	1	0	2595	1
Bin	ERR_POS(2)	0	1	4427	1
Bin	ERR_POS(2)	1	0	2828	1
Bin	ERR_POS(1)	0	1	3627	1
Bin	ERR_POS(1)	1	0	2031	1
Bin	ERR_POS(0)	0	1	3049	1
Bin	ERR_POS(0)	1	0	1449	1
Bin	RETR_CTR(3)	0	1	55	1
Bin	RETR_CTR(3)	1	0	1656	1
Bin	RETR_CTR(2)	0	1	134	1
Bin	RETR_CTR(2)	1	0	1735	1
Bin	RETR_CTR(1)	0	1	265	1
Bin	RETR_CTR(1)	1	0	1866	1
Bin	RETR_CTR(0)	0	1	646	1
Bin	RETR_CTR(0)	1	0	2247	1
Bin	ALC_BIT(4)	0	1	69	1
Bin	ALC_BIT(4)	1	0	1668	1
Bin	ALC_BIT(3)	0	1	90	1
Bin	ALC_BIT(3)	1	0	1689	1
Bin	ALC_BIT(2)	0	1	103	1
Bin	ALC_BIT(2)	1	0	1702	1
Bin	ALC_BIT(1)	0	1	173	1
Bin	ALC_BIT(1)	1	0	1772	1
Bin	ALC_BIT(0)	0	1	299	1
Bin	ALC_BIT(0)	1	0	1898	1
Bin	ALC_ID_FIELD(2)	0	1	33	1
Bin	ALC_ID_FIELD(2)	1	0	1634	1
Bin	ALC_ID_FIELD(1)	0	1	42	1
Bin	ALC_ID_FIELD(1)	1	0	1641	1
Bin	ALC_ID_FIELD(0)	0	1	95	1
Bin	ALC_ID_FIELD(0)	1	0	1696	1
Bin	RX_FRAME_CTR(31)	0	1	50	1
Bin	RX_FRAME_CTR(31)	1	0	1649	1
Bin	RX_FRAME_CTR(30)	0	1	56	1
Bin	RX_FRAME_CTR(30)	1	0	1654	1
Bin	RX_FRAME_CTR(29)	0	1	51	1
Bin	RX_FRAME_CTR(29)	1	0	1648	1
Bin	RX_FRAME_CTR(28)	0	1	53	1
Bin	RX_FRAME_CTR(28)	1	0	1652	1
Bin	RX_FRAME_CTR(27)	0	1	47	1
Bin	RX_FRAME_CTR(27)	1	0	1646	1
Bin	RX_FRAME_CTR(26)	0	1	53	1
Bin	RX_FRAME_CTR(26)	1	0	1653	1
Bin	RX_FRAME_CTR(25)	0	1	51	1
Bin	RX_FRAME_CTR(25)	1	0	1649	1
Bin	RX_FRAME_CTR(24)	0	1	47	1
Bin	RX_FRAME_CTR(24)	1	0	1646	1
Bin	RX_FRAME_CTR(23)	0	1	53	1
Bin	RX_FRAME_CTR(23)	1	0	1651	1
Bin	RX_FRAME_CTR(22)	0	1	56	1
Bin	RX_FRAME_CTR(22)	1	0	1655	1
Bin	RX_FRAME_CTR(21)	0	1	50	1
Bin	RX_FRAME_CTR(21)	1	0	1650	1
Bin	RX_FRAME_CTR(20)	0	1	52	1
Bin	RX_FRAME_CTR(20)	1	0	1651	1
Bin	RX_FRAME_CTR(19)	0	1	50	1
Bin	RX_FRAME_CTR(19)	1	0	1649	1
Bin	RX_FRAME_CTR(18)	0	1	51	1
Bin	RX_FRAME_CTR(18)	1	0	1651	1
Bin	RX_FRAME_CTR(17)	0	1	52	1
Bin	RX_FRAME_CTR(17)	1	0	1652	1
Bin	RX_FRAME_CTR(16)	0	1	60	1
Bin	RX_FRAME_CTR(16)	1	0	1658	1
Bin	RX_FRAME_CTR(15)	0	1	50	1
Bin	RX_FRAME_CTR(15)	1	0	1649	1
Bin	RX_FRAME_CTR(14)	0	1	51	1
Bin	RX_FRAME_CTR(14)	1	0	1651	1
Bin	RX_FRAME_CTR(13)	0	1	46	1
Bin	RX_FRAME_CTR(13)	1	0	1647	1
Bin	RX_FRAME_CTR(12)	0	1	48	1
Bin	RX_FRAME_CTR(12)	1	0	1648	1
Bin	RX_FRAME_CTR(11)	0	1	53	1
Bin	RX_FRAME_CTR(11)	1	0	1651	1
Bin	RX_FRAME_CTR(10)	0	1	62	1
Bin	RX_FRAME_CTR(10)	1	0	1659	1
Bin	RX_FRAME_CTR(9)	0	1	55	1
Bin	RX_FRAME_CTR(9)	1	0	1654	1
Bin	RX_FRAME_CTR(8)	0	1	65	1
Bin	RX_FRAME_CTR(8)	1	0	1665	1
Bin	RX_FRAME_CTR(7)	0	1	79	1
Bin	RX_FRAME_CTR(7)	1	0	1678	1
Bin	RX_FRAME_CTR(6)	0	1	111	1
Bin	RX_FRAME_CTR(6)	1	0	1710	1
Bin	RX_FRAME_CTR(5)	0	1	220	1
Bin	RX_FRAME_CTR(5)	1	0	1820	1
Bin	RX_FRAME_CTR(4)	0	1	354	1
Bin	RX_FRAME_CTR(4)	1	0	1952	1
Bin	RX_FRAME_CTR(3)	0	1	751	1
Bin	RX_FRAME_CTR(3)	1	0	2351	1
Bin	RX_FRAME_CTR(2)	0	1	1498	1
Bin	RX_FRAME_CTR(2)	1	0	3095	1
Bin	RX_FRAME_CTR(1)	0	1	2960	1
Bin	RX_FRAME_CTR(1)	1	0	4559	1
Bin	RX_FRAME_CTR(0)	0	1	5900	1
Bin	RX_FRAME_CTR(0)	1	0	7500	1
Bin	TX_FRAME_CTR(31)	0	1	92	1
Bin	TX_FRAME_CTR(31)	1	0	1693	1
Bin	TX_FRAME_CTR(30)	0	1	102	1
Bin	TX_FRAME_CTR(30)	1	0	1703	1
Bin	TX_FRAME_CTR(29)	0	1	108	1
Bin	TX_FRAME_CTR(29)	1	0	1709	1
Bin	TX_FRAME_CTR(28)	0	1	102	1
Bin	TX_FRAME_CTR(28)	1	0	1703	1
Bin	TX_FRAME_CTR(27)	0	1	99	1
Bin	TX_FRAME_CTR(27)	1	0	1700	1
Bin	TX_FRAME_CTR(26)	0	1	111	1
Bin	TX_FRAME_CTR(26)	1	0	1712	1
Bin	TX_FRAME_CTR(25)	0	1	106	1
Bin	TX_FRAME_CTR(25)	1	0	1707	1
Bin	TX_FRAME_CTR(24)	0	1	108	1
Bin	TX_FRAME_CTR(24)	1	0	1709	1
Bin	TX_FRAME_CTR(23)	0	1	100	1
Bin	TX_FRAME_CTR(23)	1	0	1701	1
Bin	TX_FRAME_CTR(22)	0	1	99	1
Bin	TX_FRAME_CTR(22)	1	0	1700	1
Bin	TX_FRAME_CTR(21)	0	1	104	1
Bin	TX_FRAME_CTR(21)	1	0	1705	1
Bin	TX_FRAME_CTR(20)	0	1	104	1
Bin	TX_FRAME_CTR(20)	1	0	1705	1
Bin	TX_FRAME_CTR(19)	0	1	104	1
Bin	TX_FRAME_CTR(19)	1	0	1705	1
Bin	TX_FRAME_CTR(18)	0	1	95	1
Bin	TX_FRAME_CTR(18)	1	0	1696	1
Bin	TX_FRAME_CTR(17)	0	1	101	1
Bin	TX_FRAME_CTR(17)	1	0	1702	1
Bin	TX_FRAME_CTR(16)	0	1	95	1
Bin	TX_FRAME_CTR(16)	1	0	1696	1
Bin	TX_FRAME_CTR(15)	0	1	106	1
Bin	TX_FRAME_CTR(15)	1	0	1707	1
Bin	TX_FRAME_CTR(14)	0	1	105	1
Bin	TX_FRAME_CTR(14)	1	0	1706	1
Bin	TX_FRAME_CTR(13)	0	1	109	1
Bin	TX_FRAME_CTR(13)	1	0	1710	1
Bin	TX_FRAME_CTR(12)	0	1	110	1
Bin	TX_FRAME_CTR(12)	1	0	1711	1
Bin	TX_FRAME_CTR(11)	0	1	98	1
Bin	TX_FRAME_CTR(11)	1	0	1699	1
Bin	TX_FRAME_CTR(10)	0	1	105	1
Bin	TX_FRAME_CTR(10)	1	0	1706	1
Bin	TX_FRAME_CTR(9)	0	1	102	1
Bin	TX_FRAME_CTR(9)	1	0	1703	1
Bin	TX_FRAME_CTR(8)	0	1	105	1
Bin	TX_FRAME_CTR(8)	1	0	1706	1
Bin	TX_FRAME_CTR(7)	0	1	112	1
Bin	TX_FRAME_CTR(7)	1	0	1713	1
Bin	TX_FRAME_CTR(6)	0	1	110	1
Bin	TX_FRAME_CTR(6)	1	0	1711	1
Bin	TX_FRAME_CTR(5)	0	1	126	1
Bin	TX_FRAME_CTR(5)	1	0	1727	1
Bin	TX_FRAME_CTR(4)	0	1	154	1
Bin	TX_FRAME_CTR(4)	1	0	1755	1
Bin	TX_FRAME_CTR(3)	0	1	261	1
Bin	TX_FRAME_CTR(3)	1	0	1862	1
Bin	TX_FRAME_CTR(2)	0	1	603	1
Bin	TX_FRAME_CTR(2)	1	0	2204	1
Bin	TX_FRAME_CTR(1)	0	1	1075	1
Bin	TX_FRAME_CTR(1)	1	0	2676	1
Bin	TX_FRAME_CTR(0)	0	1	2217	1
Bin	TX_FRAME_CTR(0)	1	0	3818	1
Bin	BST_CTR(2)	0	1	33793	1
Bin	BST_CTR(2)	1	0	35393	1
Bin	BST_CTR(1)	0	1	71746	1
Bin	BST_CTR(1)	1	0	73346	1
Bin	BST_CTR(0)	0	1	142471	1
Bin	BST_CTR(0)	1	0	144071	1
Bin	DST_CTR(2)	0	1	117167	1
Bin	DST_CTR(2)	1	0	118766	1
Bin	DST_CTR(1)	0	1	243244	1
Bin	DST_CTR(1)	1	0	244841	1
Bin	DST_CTR(0)	0	1	487033	1
Bin	DST_CTR(0)	1	0	488629	1
Bin	STATUS_EWL	0	1	780	1
Bin	STATUS_EWL	1	0	2380	1

Port:

PC_DBG

	Element	From	To	Count	Threshold
Bin	IS_SOF	0	1	25148	1
Bin	IS_SOF	1	0	26749	1
Bin	IS_ARBITRATION	0	1	55910	1
Bin	IS_ARBITRATION	1	0	57511	1
Bin	IS_CONTROL	0	1	51266	1
Bin	IS_CONTROL	1	0	52867	1
Bin	IS_DATA	0	1	36655	1
Bin	IS_DATA	1	0	38256	1
Bin	IS_STUFF_COUNT	0	1	13017	1
Bin	IS_STUFF_COUNT	1	0	14618	1
Bin	IS_CRC	0	1	31164	1
Bin	IS_CRC	1	0	32765	1
Bin	IS_CRC_DELIM	0	1	29702	1
Bin	IS_CRC_DELIM	1	0	31303	1
Bin	IS_ACK	0	1	29548	1
Bin	IS_ACK	1	0	31149	1
Bin	IS_ACK_DELIM	0	1	28120	1
Bin	IS_ACK_DELIM	1	0	29721	1
Bin	IS_EOF	0	1	27225	1
Bin	IS_EOF	1	0	28826	1
Bin	IS_OVERLOAD	0	1	529	1
Bin	IS_OVERLOAD	1	0	2130	1
Bin	IS_ERR	0	1	27358	1
Bin	IS_ERR	1	0	28953	1
Bin	IS_INTERMISSION	0	1	51904	1
Bin	IS_INTERMISSION	1	0	53504	1
Bin	IS_SUSPEND	0	1	2849	1
Bin	IS_SUSPEND	1	0	4450	1

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold
Bin	(31)	0	1	61752	1
Bin	(31)	1	0	1036930	1
Bin	(30)	0	1	65395	1
Bin	(30)	1	0	1033287	1
Bin	(29)	0	1	63597	1
Bin	(29)	1	0	1035085	1
Bin	(28)	0	1	89734	1
Bin	(28)	1	0	1008948	1
Bin	(27)	0	1	82551	1
Bin	(27)	1	0	1016131	1
Bin	(26)	0	1	76670	1
Bin	(26)	1	0	1022012	1
Bin	(25)	0	1	85744	1
Bin	(25)	1	0	1012938	1
Bin	(24)	0	1	79509	1
Bin	(24)	1	0	1019173	1
Bin	(23)	0	1	70820	1
Bin	(23)	1	0	1027862	1
Bin	(22)	0	1	106620	1
Bin	(22)	1	0	992062	1
Bin	(21)	0	1	75624	1
Bin	(21)	1	0	1023058	1
Bin	(20)	0	1	81965	1
Bin	(20)	1	0	1016717	1
Bin	(19)	0	1	112715	1
Bin	(19)	1	0	985967	1
Bin	(18)	0	1	132387	1
Bin	(18)	1	0	966295	1
Bin	(17)	0	1	124545	1
Bin	(17)	1	0	974137	1
Bin	(16)	0	1	193609	1
Bin	(16)	1	0	905073	1
Bin	(15)	0	1	74187	1
Bin	(15)	1	0	1024495	1
Bin	(14)	0	1	86222	1
Bin	(14)	1	0	1012460	1
Bin	(13)	0	1	78101	1
Bin	(13)	1	0	1020581	1
Bin	(12)	0	1	78761	1
Bin	(12)	1	0	1019921	1
Bin	(11)	0	1	101401	1
Bin	(11)	1	0	997281	1
Bin	(10)	0	1	118499	1
Bin	(10)	1	0	980183	1
Bin	(9)	0	1	170089	1
Bin	(9)	1	0	928593	1
Bin	(8)	0	1	152135	1
Bin	(8)	1	0	946547	1
Bin	(7)	0	1	127650	1
Bin	(7)	1	0	971032	1
Bin	(6)	0	1	113817	1
Bin	(6)	1	0	984865	1
Bin	(5)	0	1	107012	1
Bin	(5)	1	0	991670	1
Bin	(4)	0	1	164595	1
Bin	(4)	1	0	934087	1
Bin	(3)	0	1	138369	1
Bin	(3)	1	0	960313	1
Bin	(2)	0	1	164416	1
Bin	(2)	1	0	934266	1
Bin	(1)	0	1	237348	1
Bin	(1)	1	0	861334	1
Bin	(0)	0	1	200368	1
Bin	(0)	1	0	898314	1

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold
Bin	(4)	0	1	327597	1
Bin	(4)	1	0	27535839	1
Bin	(3)	0	1	578989	1
Bin	(3)	1	0	27284447	1
Bin	(2)	0	1	439205	1
Bin	(2)	1	0	27424231	1
Bin	(1)	0	1	27080832	1
Bin	(1)	1	0	782604	1
Bin	(0)	0	1	17705660	1
Bin	(0)	1	0	10157776	1

Port:

TXTB_PORT_A_CS

	Element	From	To	Count	Threshold
Bin	(7)	0	1	11201	1
Bin	(7)	1	0	183742	1
Bin	(6)	0	1	11325	1
Bin	(6)	1	0	183618	1
Bin	(5)	0	1	11146	1
Bin	(5)	1	0	183797	1
Bin	(4)	0	1	11287	1
Bin	(4)	1	0	183656	1
Bin	(3)	0	1	45347	1
Bin	(3)	1	0	474437	1
Bin	(2)	0	1	44898	1
Bin	(2)	1	0	474886	1
Bin	(1)	0	1	127926	1
Bin	(1)	1	0	727997	1
Bin	(0)	0	1	164031	1
Bin	(0)	1	0	691892	1

Port:

TXTB_PORT_A_BE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	27823416	1
Bin	(3)	1	0	38419	1
Bin	(2)	0	1	27823798	1
Bin	(2)	1	0	38037	1
Bin	(1)	0	1	27725615	1
Bin	(1)	1	0	136220	1
Bin	(0)	0	1	27726843	1
Bin	(0)	1	0	134992	1

Port:

MR_TX_PRIORITY

	Element	From	To	Count	Threshold
Bin	(7)(2)	0	1	109	1
Bin	(7)(2)	1	0	376	1
Bin	(7)(1)	0	1	114	1
Bin	(7)(1)	1	0	367	1
Bin	(7)(0)	0	1	98	1
Bin	(7)(0)	1	0	363	1
Bin	(6)(2)	0	1	114	1
Bin	(6)(2)	1	0	359	1
Bin	(6)(1)	0	1	103	1
Bin	(6)(1)	1	0	334	1
Bin	(6)(0)	0	1	161	1
Bin	(6)(0)	1	0	408	1
Bin	(5)(2)	0	1	100	1
Bin	(5)(2)	1	0	334	1
Bin	(5)(1)	0	1	133	1
Bin	(5)(1)	1	0	331	1
Bin	(5)(0)	0	1	128	1
Bin	(5)(0)	1	0	356	1
Bin	(4)(2)	0	1	178	1
Bin	(4)(2)	1	0	361	1
Bin	(4)(1)	0	1	161	1
Bin	(4)(1)	1	0	373	1
Bin	(4)(0)	0	1	132	1
Bin	(4)(0)	1	0	317	1
Bin	(3)(2)	0	1	304	1
Bin	(3)(2)	1	0	1149	1
Bin	(3)(1)	0	1	321	1
Bin	(3)(1)	1	0	1174	1
Bin	(3)(0)	0	1	296	1
Bin	(3)(0)	1	0	1092	1
Bin	(2)(2)	0	1	332	1
Bin	(2)(2)	1	0	1070	1
Bin	(2)(1)	0	1	331	1
Bin	(2)(1)	1	0	1129	1
Bin	(2)(0)	0	1	402	1
Bin	(2)(0)	1	0	1109	1
Bin	(1)(2)	0	1	385	1
Bin	(1)(2)	1	0	1923	1
Bin	(1)(1)	0	1	373	1
Bin	(1)(1)	1	0	2008	1
Bin	(1)(0)	0	1	401	1
Bin	(1)(0)	1	0	1977	1
Bin	(0)(2)	0	1	470	1
Bin	(0)(2)	1	0	1944	1
Bin	(0)(1)	0	1	402	1
Bin	(0)(1)	1	0	2030	1
Bin	(0)(0)	0	1	2052	1
Bin	(0)(0)	1	0	468	1

Port:

MR_TX_COMMAND_TXBI

	Element	From	To	Count	Threshold
Bin	(7)	0	1	78	1
Bin	(7)	1	0	1128	1
Bin	(6)	0	1	76	1
Bin	(6)	1	0	1130	1
Bin	(5)	0	1	78	1
Bin	(5)	1	0	1128	1
Bin	(4)	0	1	84	1
Bin	(4)	1	0	1122	1
Bin	(3)	0	1	396	1
Bin	(3)	1	0	4047	1
Bin	(2)	0	1	319	1
Bin	(2)	1	0	4124	1
Bin	(1)	0	1	5639	1
Bin	(1)	1	0	10512	1
Bin	(0)	0	1	6554	1
Bin	(0)	1	0	9597	1

Signal:

MR_CTRL_OUT_I

	Element	From	To	Count	Threshold
Bin	MODE_RST	0	1	868	1
Bin	MODE_RST	1	0	32877	1
Bin	MODE_BMM	0	1	15	1
Bin	MODE_BMM	1	0	1616	1
Bin	MODE_STM	0	1	160	1
Bin	MODE_STM	1	0	1761	1
Bin	MODE_AFM	0	1	68	1
Bin	MODE_AFM	1	0	1669	1
Bin	MODE_FDE	0	1	1801	1
Bin	MODE_FDE	1	0	200	1
Bin	MODE_TTTM	0	1	55	1
Bin	MODE_TTTM	1	0	1656	1
Bin	MODE_ROM	0	1	51	1
Bin	MODE_ROM	1	0	1652	1
Bin	MODE_ACF	0	1	19	1
Bin	MODE_ACF	1	0	1620	1
Bin	MODE_TSTM	0	1	1027	1
Bin	MODE_TSTM	1	0	2627	1
Bin	MODE_RXBAM	0	1	1731	1
Bin	MODE_RXBAM	1	0	130	1
Bin	MODE_TXBBM	0	1	33	1
Bin	MODE_TXBBM	1	0	1634	1
Bin	MODE_SAM	0	1	55	1
Bin	MODE_SAM	1	0	1656	1
Bin	MODE_ERFM	0	1	153	1
Bin	MODE_ERFM	1	0	1754	1
Bin	SETTINGS_RTRLE	0	1	2454	1
Bin	SETTINGS_RTRLE	1	0	4055	1
Bin	SETTINGS_RTRTH(3)	0	1	22	1
Bin	SETTINGS_RTRTH(3)	1	0	1623	1
Bin	SETTINGS_RTRTH(2)	0	1	54	1
Bin	SETTINGS_RTRTH(2)	1	0	1655	1
Bin	SETTINGS_RTRTH(1)	0	1	22	1
Bin	SETTINGS_RTRTH(1)	1	0	1623	1
Bin	SETTINGS_RTRTH(0)	0	1	53	1
Bin	SETTINGS_RTRTH(0)	1	0	1654	1
Bin	SETTINGS_ILBP	0	1	130	1
Bin	SETTINGS_ILBP	1	0	1731	1
Bin	SETTINGS_ENA	0	1	6483	1
Bin	SETTINGS_ENA	1	0	8072	1
Bin	SETTINGS_NISOFD	0	1	130	1
Bin	SETTINGS_NISOFD	1	0	1731	1
Bin	SETTINGS_PEX	0	1	72	1
Bin	SETTINGS_PEX	1	0	1673	1
Bin	SETTINGS_TBFBO	0	1	2533	1
Bin	SETTINGS_TBFBO	1	0	944	1
Bin	SETTINGS_FDRF	0	1	4	1
Bin	SETTINGS_FDRF	1	0	1605	1
Bin	SETTINGS_PCHKE	0	1	124	1
Bin	SETTINGS_PCHKE	1	0	1725	1
Bin	COMMAND_RXRPMV	0	1	21	1
Bin	COMMAND_RXRPMV	1	0	3064	1
Bin	COMMAND_RRB	0	1	460	1
Bin	COMMAND_RRB	1	0	3064	1
Bin	COMMAND_CDO	0	1	20	1
Bin	COMMAND_CDO	1	0	3064	1
Bin	COMMAND_ERCRST	0	1	170	1
Bin	COMMAND_ERCRST	1	0	3064	1
Bin	COMMAND_RXFCRST	0	1	124	1
Bin	COMMAND_RXFCRST	1	0	3064	1
Bin	COMMAND_TXFCRST	0	1	124	1
Bin	COMMAND_TXFCRST	1	0	3064	1
Bin	COMMAND_CPEXS	0	1	60	1
Bin	COMMAND_CPEXS	1	0	3064	1
Bin	COMMAND_CRXPE	0	1	40	1
Bin	COMMAND_CRXPE	1	0	3064	1
Bin	COMMAND_CTXPE	0	1	440	1
Bin	COMMAND_CTXPE	1	0	3064	1
Bin	COMMAND_CTXDPE	0	1	40	1
Bin	COMMAND_CTXDPE	1	0	3064	1
Bin	INT_STAT_RXI	0	1	40	1
Bin	INT_STAT_RXI	1	0	1748	1
Bin	INT_STAT_TXI	0	1	42	1
Bin	INT_STAT_TXI	1	0	1748	1
Bin	INT_STAT_EWLI	0	1	30	1
Bin	INT_STAT_EWLI	1	0	1748	1
Bin	INT_STAT_DOI	0	1	16	1
Bin	INT_STAT_DOI	1	0	1748	1
Bin	INT_STAT_FCSI	0	1	80	1
Bin	INT_STAT_FCSI	1	0	1748	1
Bin	INT_STAT_ALI	0	1	5	1
Bin	INT_STAT_ALI	1	0	1748	1
Bin	INT_STAT_BEI	0	1	15	1
Bin	INT_STAT_BEI	1	0	1748	1
Bin	INT_STAT_OFI	0	1	5	1
Bin	INT_STAT_OFI	1	0	1748	1
Bin	INT_STAT_RXFI	0	1	15	1
Bin	INT_STAT_RXFI	1	0	1748	1
Bin	INT_STAT_BSI	0	1	43	1
Bin	INT_STAT_BSI	1	0	1748	1
Bin	INT_STAT_RBNEI	0	1	50	1
Bin	INT_STAT_RBNEI	1	0	1748	1
Bin	INT_STAT_TXBHCI	0	1	52	1
Bin	INT_STAT_TXBHCI	1	0	1748	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	2143	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	0	1	476	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	0	1	512	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	0	1	492	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	1	0	2143	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	66	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	40	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	50	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	15	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	2076	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	0	1	409	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	0	1	435	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	0	1	425	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	0	1	460	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	1	0	2076	1
Bin	BTR_PROP(6)	0	1	205	1
Bin	BTR_PROP(6)	1	0	1804	1
Bin	BTR_PROP(5)	0	1	313	1
Bin	BTR_PROP(5)	1	0	1911	1
Bin	BTR_PROP(4)	0	1	228	1
Bin	BTR_PROP(4)	1	0	1826	1
Bin	BTR_PROP(3)	0	1	272	1
Bin	BTR_PROP(3)	1	0	1870	1
Bin	BTR_PROP(2)	0	1	3820	1
Bin	BTR_PROP(2)	1	0	2220	1
Bin	BTR_PROP(1)	0	1	265	1
Bin	BTR_PROP(1)	1	0	1863	1
Bin	BTR_PROP(0)	0	1	1795	1
Bin	BTR_PROP(0)	1	0	195	1
Bin	BTR_PH1(5)	0	1	317	1
Bin	BTR_PH1(5)	1	0	1916	1
Bin	BTR_PH1(4)	0	1	253	1
Bin	BTR_PH1(4)	1	0	1852	1
Bin	BTR_PH1(3)	0	1	263	1
Bin	BTR_PH1(3)	1	0	1862	1
Bin	BTR_PH1(2)	0	1	1305	1
Bin	BTR_PH1(2)	1	0	2896	1
Bin	BTR_PH1(1)	0	1	1925	1
Bin	BTR_PH1(1)	1	0	325	1
Bin	BTR_PH1(0)	0	1	2091	1
Bin	BTR_PH1(0)	1	0	492	1
Bin	BTR_PH2(5)	0	1	206	1
Bin	BTR_PH2(5)	1	0	1805	1
Bin	BTR_PH2(4)	0	1	346	1
Bin	BTR_PH2(4)	1	0	1944	1
Bin	BTR_PH2(3)	0	1	315	1
Bin	BTR_PH2(3)	1	0	1914	1
Bin	BTR_PH2(2)	0	1	3874	1
Bin	BTR_PH2(2)	1	0	2275	1
Bin	BTR_PH2(1)	0	1	3412	1
Bin	BTR_PH2(1)	1	0	5003	1
Bin	BTR_PH2(0)	0	1	2158	1
Bin	BTR_PH2(0)	1	0	557	1
Bin	BTR_BRP(7)	0	1	14	1
Bin	BTR_BRP(7)	1	0	1615	1
Bin	BTR_BRP(6)	0	1	12	1
Bin	BTR_BRP(6)	1	0	1613	1
Bin	BTR_BRP(5)	0	1	12	1
Bin	BTR_BRP(5)	1	0	1613	1
Bin	BTR_BRP(4)	0	1	16	1
Bin	BTR_BRP(4)	1	0	1617	1
Bin	BTR_BRP(3)	0	1	4831	1
Bin	BTR_BRP(3)	1	0	3242	1
Bin	BTR_BRP(2)	0	1	929	1
Bin	BTR_BRP(2)	1	0	2523	1
Bin	BTR_BRP(1)	0	1	4762	1
Bin	BTR_BRP(1)	1	0	3170	1
Bin	BTR_BRP(0)	0	1	2316	1
Bin	BTR_BRP(0)	1	0	3914	1
Bin	BTR_SJW(4)	0	1	209	1
Bin	BTR_SJW(4)	1	0	1807	1
Bin	BTR_SJW(3)	0	1	266	1
Bin	BTR_SJW(3)	1	0	1864	1
Bin	BTR_SJW(2)	0	1	965	1
Bin	BTR_SJW(2)	1	0	2563	1
Bin	BTR_SJW(1)	0	1	2623	1
Bin	BTR_SJW(1)	1	0	1031	1
Bin	BTR_SJW(0)	0	1	3116	1
Bin	BTR_SJW(0)	1	0	4714	1
Bin	BTR_FD_PROP_FD(5)	0	1	243	1
Bin	BTR_FD_PROP_FD(5)	1	0	1841	1
Bin	BTR_FD_PROP_FD(4)	0	1	291	1
Bin	BTR_FD_PROP_FD(4)	1	0	1889	1
Bin	BTR_FD_PROP_FD(3)	0	1	273	1
Bin	BTR_FD_PROP_FD(3)	1	0	1871	1
Bin	BTR_FD_PROP_FD(2)	0	1	1195	1
Bin	BTR_FD_PROP_FD(2)	1	0	2784	1
Bin	BTR_FD_PROP_FD(1)	0	1	4706	1
Bin	BTR_FD_PROP_FD(1)	1	0	3114	1
Bin	BTR_FD_PROP_FD(0)	0	1	3890	1
Bin	BTR_FD_PROP_FD(0)	1	0	2289	1
Bin	BTR_FD_PH1_FD(4)	0	1	253	1
Bin	BTR_FD_PH1_FD(4)	1	0	1852	1
Bin	BTR_FD_PH1_FD(3)	0	1	299	1
Bin	BTR_FD_PH1_FD(3)	1	0	1898	1
Bin	BTR_FD_PH1_FD(2)	0	1	1176	1
Bin	BTR_FD_PH1_FD(2)	1	0	2766	1
Bin	BTR_FD_PH1_FD(1)	0	1	1704	1
Bin	BTR_FD_PH1_FD(1)	1	0	104	1
Bin	BTR_FD_PH1_FD(0)	0	1	3847	1
Bin	BTR_FD_PH1_FD(0)	1	0	2247	1
Bin	BTR_FD_PH2_FD(4)	0	1	281	1
Bin	BTR_FD_PH2_FD(4)	1	0	1880	1
Bin	BTR_FD_PH2_FD(3)	0	1	317	1
Bin	BTR_FD_PH2_FD(3)	1	0	1916	1
Bin	BTR_FD_PH2_FD(2)	0	1	1209	1
Bin	BTR_FD_PH2_FD(2)	1	0	2799	1
Bin	BTR_FD_PH2_FD(1)	0	1	1725	1
Bin	BTR_FD_PH2_FD(1)	1	0	125	1
Bin	BTR_FD_PH2_FD(0)	0	1	3868	1
Bin	BTR_FD_PH2_FD(0)	1	0	2267	1
Bin	BTR_FD_BRP_FD(7)	0	1	18	1
Bin	BTR_FD_BRP_FD(7)	1	0	1619	1
Bin	BTR_FD_BRP_FD(6)	0	1	30	1
Bin	BTR_FD_BRP_FD(6)	1	0	1631	1
Bin	BTR_FD_BRP_FD(5)	0	1	17	1
Bin	BTR_FD_BRP_FD(5)	1	0	1618	1
Bin	BTR_FD_BRP_FD(4)	0	1	27	1
Bin	BTR_FD_BRP_FD(4)	1	0	1628	1
Bin	BTR_FD_BRP_FD(3)	0	1	28	1
Bin	BTR_FD_BRP_FD(3)	1	0	1629	1
Bin	BTR_FD_BRP_FD(2)	0	1	4843	1
Bin	BTR_FD_BRP_FD(2)	1	0	3254	1
Bin	BTR_FD_BRP_FD(1)	0	1	764	1
Bin	BTR_FD_BRP_FD(1)	1	0	2363	1
Bin	BTR_FD_BRP_FD(0)	0	1	2598	1
Bin	BTR_FD_BRP_FD(0)	1	0	4189	1
Bin	BTR_FD_SJW_FD(4)	0	1	238	1
Bin	BTR_FD_SJW_FD(4)	1	0	1836	1
Bin	BTR_FD_SJW_FD(3)	0	1	282	1
Bin	BTR_FD_SJW_FD(3)	1	0	1880	1
Bin	BTR_FD_SJW_FD(2)	0	1	924	1
Bin	BTR_FD_SJW_FD(2)	1	0	2522	1
Bin	BTR_FD_SJW_FD(1)	0	1	2557	1
Bin	BTR_FD_SJW_FD(1)	1	0	965	1
Bin	BTR_FD_SJW_FD(0)	0	1	959	1
Bin	BTR_FD_SJW_FD(0)	1	0	2557	1
Bin	EWL_EW_LIMIT(7)	0	1	89	1
Bin	EWL_EW_LIMIT(7)	1	0	1690	1
Bin	EWL_EW_LIMIT(6)	0	1	1680	1
Bin	EWL_EW_LIMIT(6)	1	0	79	1
Bin	EWL_EW_LIMIT(5)	0	1	1672	1
Bin	EWL_EW_LIMIT(5)	1	0	71	1
Bin	EWL_EW_LIMIT(4)	0	1	78	1
Bin	EWL_EW_LIMIT(4)	1	0	1679	1
Bin	EWL_EW_LIMIT(3)	0	1	82	1
Bin	EWL_EW_LIMIT(3)	1	0	1683	1
Bin	EWL_EW_LIMIT(2)	0	1	85	1
Bin	EWL_EW_LIMIT(2)	1	0	1686	1
Bin	EWL_EW_LIMIT(1)	0	1	86	1
Bin	EWL_EW_LIMIT(1)	1	0	1687	1
Bin	EWL_EW_LIMIT(0)	0	1	87	1
Bin	EWL_EW_LIMIT(0)	1	0	1688	1
Bin	ERP_ERP_LIMIT(7)	0	1	1743	1
Bin	ERP_ERP_LIMIT(7)	1	0	142	1
Bin	ERP_ERP_LIMIT(6)	0	1	24	1
Bin	ERP_ERP_LIMIT(6)	1	0	1625	1
Bin	ERP_ERP_LIMIT(5)	0	1	21	1
Bin	ERP_ERP_LIMIT(5)	1	0	1622	1
Bin	ERP_ERP_LIMIT(4)	0	1	27	1
Bin	ERP_ERP_LIMIT(4)	1	0	1628	1
Bin	ERP_ERP_LIMIT(3)	0	1	21	1
Bin	ERP_ERP_LIMIT(3)	1	0	1622	1
Bin	ERP_ERP_LIMIT(2)	0	1	25	1
Bin	ERP_ERP_LIMIT(2)	1	0	1626	1
Bin	ERP_ERP_LIMIT(1)	0	1	23	1
Bin	ERP_ERP_LIMIT(1)	1	0	1624	1
Bin	ERP_ERP_LIMIT(0)	0	1	21	1
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Bin	CTR_PRES_CTPV(8)	0	1	256	1
Bin	CTR_PRES_CTPV(8)	1	0	1857	1
Bin	CTR_PRES_CTPV(7)	0	1	2687	1
Bin	CTR_PRES_CTPV(7)	1	0	4288	1
Bin	CTR_PRES_CTPV(6)	0	1	703	1
Bin	CTR_PRES_CTPV(6)	1	0	2304	1
Bin	CTR_PRES_CTPV(5)	0	1	2728	1
Bin	CTR_PRES_CTPV(5)	1	0	4329	1
Bin	CTR_PRES_CTPV(4)	0	1	2839	1
Bin	CTR_PRES_CTPV(4)	1	0	4440	1
Bin	CTR_PRES_CTPV(3)	0	1	919	1
Bin	CTR_PRES_CTPV(3)	1	0	2520	1
Bin	CTR_PRES_CTPV(2)	0	1	2891	1
Bin	CTR_PRES_CTPV(2)	1	0	4492	1
Bin	CTR_PRES_CTPV(1)	0	1	1003	1
Bin	CTR_PRES_CTPV(1)	1	0	2604	1
Bin	CTR_PRES_CTPV(0)	0	1	750	1
Bin	CTR_PRES_CTPV(0)	1	0	2351	1
Bin	CTR_PRES_PTX	0	1	19364	1
Bin	CTR_PRES_PTX	1	0	45544	1
Bin	CTR_PRES_PRX	0	1	19759	1
Bin	CTR_PRES_PRX	1	0	45544	1
Bin	CTR_PRES_ENORM	0	1	6608	1
Bin	CTR_PRES_ENORM	1	0	45544	1
Bin	CTR_PRES_EFD	0	1	6608	1
Bin	CTR_PRES_EFD	1	0	45544	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	0	1	390	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	1	0	1991	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	0	1	365	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	1	0	1966	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	0	1	342	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	1	0	1943	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	0	1	328	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	1	0	1929	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	0	1	399	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	1	0	2000	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	0	1	362	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	1	0	1963	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	0	1	367	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	1	0	1968	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	0	1	345	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	1	0	1946	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	0	1	394	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	1	0	1995	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	0	1	380	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	1	0	1981	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	0	1	388	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	1	0	1989	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	0	1	104	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	1	0	1705	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	0	1	98	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	1	0	1699	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	0	1	98	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	1	0	1699	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	0	1	130	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	1	0	1731	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	0	1	90	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	1	0	1691	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	0	1	101	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	1	0	1702	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	0	1	77	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	1	0	1678	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	0	1	246	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	1	0	1847	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	0	1	285	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	1	0	1886	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	0	1	238	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	1	0	1839	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	0	1	257	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	1	0	1858	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	0	1	257	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	1	0	1858	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	0	1	251	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	1	0	1852	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	0	1	275	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	1	0	1876	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	0	1	286	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	1	0	1887	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	0	1	264	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	1	0	1865	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	0	1	244	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	1	0	1845	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	0	1	282	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	1	0	1883	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	0	1	764	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	1	0	2365	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	0	1	799	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	1	0	2400	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	0	1	820	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	1	0	2421	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	0	1	809	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	1	0	2410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	0	1	766	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	1	0	2367	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	0	1	806	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	1	0	2407	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	0	1	808	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	1	0	2409	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	0	1	794	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	1	0	2395	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	0	1	833	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	1	0	2434	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	0	1	823	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	1	0	2424	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	0	1	823	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	1	0	2424	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	1	0	2011	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	0	1	385	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	1	0	1986	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	0	1	391	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	1	0	1992	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	0	1	449	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	1	0	2050	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	1	0	1998	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	0	1	380	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	1	0	1981	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	0	1	442	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	1	0	2043	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	0	1	394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	1	0	1995	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	0	1	398	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	1	0	1999	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	0	1	377	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	1	0	1978	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	0	1	360	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	1	0	1961	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	0	1	393	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	1	0	1994	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	0	1	403	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	1	0	2004	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	1	0	1998	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	1	0	2011	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	0	1	402	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	1	0	2003	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	0	1	422	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	1	0	2023	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	0	1	95	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	1	0	1696	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	0	1	103	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	1	0	1704	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	0	1	101	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	1	0	1702	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	0	1	104	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	1	0	1705	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	0	1	90	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	1	0	1691	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	0	1	92	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	1	0	1693	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	0	1	81	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	1	0	1682	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	0	1	107	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	1	0	1708	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	0	1	16	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	1	0	1617	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	0	1	19	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	1	0	1620	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	0	1	28	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	1	0	1629	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	0	1	37	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	1	0	1638	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	0	1	35	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	1	0	1636	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	0	1	23	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	1	0	1624	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	0	1	21	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	1	0	1622	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	0	1	60	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	1	0	1661	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	1	0	1671	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	1	0	1668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	1	0	1671	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	0	1	63	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	1	0	1664	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	1	0	1671	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	1	0	1668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	0	1	70	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	1	0	1671	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	0	1	196	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	1	0	1797	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	0	1	196	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	1	0	1797	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	0	1	217	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	1	0	1818	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	0	1	183	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	1	0	1784	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	0	1	218	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	1	0	1819	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	0	1	206	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	1	0	1807	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	0	1	200	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	1	0	1801	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	0	1	225	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	1	0	1826	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	0	1	229	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	1	0	1830	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	0	1	201	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	1	0	1802	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	0	1	209	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	1	0	1810	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	0	1	87	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	1	0	1688	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	0	1	104	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	1	0	1705	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	0	1	91	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	1	0	1692	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	0	1	103	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	1	0	1704	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	0	1	108	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	1	0	1709	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	0	1	107	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	1	0	1708	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	0	1	93	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	1	0	1694	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	0	1	98	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	1	0	1699	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	0	1	96	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	1	0	1697	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	0	1	86	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	1	0	1687	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	0	1	114	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	1	0	1715	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	0	1	92	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	1	0	1693	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	0	1	115	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	1	0	1716	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	0	1	93	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	1	0	1694	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	0	1	108	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	1	0	1709	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	0	1	85	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	1	0	1686	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	0	1	95	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	1	0	1696	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	0	1	89	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	1	0	1690	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	0	1	82	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	1	0	1683	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	0	1	108	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	1	0	1709	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	0	1	79	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	1	0	1680	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	0	1	101	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	1	0	1702	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	0	1	105	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	1	0	1706	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	0	1	92	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	1	0	1693	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	0	1	85	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	1	0	1686	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	0	1	99	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	1	0	1700	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	0	1	19	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	1	0	1620	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	0	1	20	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	1	0	1621	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	0	1	27	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	1	0	1628	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	0	1	28	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	1	0	1629	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	0	1	22	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	1	0	1623	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	0	1	14	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	1	0	1615	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	1	0	1668	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	1	0	1668	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	0	1	68	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	1	0	1669	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	1	0	1664	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	1	0	1664	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	0	1	68	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	1	0	1669	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	0	1	60	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	1	0	1661	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	0	1	77	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	1	0	1678	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	1	0	1668	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	0	1	184	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	1	0	1785	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	0	1	188	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	1	0	1789	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	0	1	201	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	1	0	1802	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	0	1	196	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	1	0	1797	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	0	1	193	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	1	0	1794	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	0	1	190	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	1	0	1791	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	0	1	204	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	1	0	1805	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	0	1	225	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	1	0	1826	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	0	1	201	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	1	0	1802	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	0	1	206	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	1	0	1807	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	0	1	94	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	1	0	1695	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	0	1	97	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	1	0	1698	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	1	0	1705	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	0	1	93	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	1	0	1694	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	0	1	107	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	1	0	1708	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	1	0	1705	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	0	1	113	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	1	0	1714	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	0	1	96	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	1	0	1697	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	0	1	91	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	1	0	1692	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	0	1	90	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	1	0	1691	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	0	1	99	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	1	0	1700	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	0	1	89	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	1	0	1690	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	0	1	107	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	1	0	1708	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	1	0	1711	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	1	0	1711	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	1	0	1602	1
Bin	FILTER_CONTROL_FANB	0	1	2052	1
Bin	FILTER_CONTROL_FANB	1	0	451	1
Bin	FILTER_CONTROL_FANE	0	1	2029	1
Bin	FILTER_CONTROL_FANE	1	0	428	1
Bin	FILTER_CONTROL_FAFB	0	1	2060	1
Bin	FILTER_CONTROL_FAFB	1	0	459	1
Bin	FILTER_CONTROL_FAFE	0	1	2029	1
Bin	FILTER_CONTROL_FAFE	1	0	428	1
Bin	FILTER_CONTROL_FBNB	0	1	106	1
Bin	FILTER_CONTROL_FBNB	1	0	1707	1
Bin	FILTER_CONTROL_FBNE	0	1	105	1
Bin	FILTER_CONTROL_FBNE	1	0	1706	1
Bin	FILTER_CONTROL_FBFB	0	1	107	1
Bin	FILTER_CONTROL_FBFB	1	0	1708	1
Bin	FILTER_CONTROL_FBFE	0	1	105	1
Bin	FILTER_CONTROL_FBFE	1	0	1706	1
Bin	FILTER_CONTROL_FCNB	0	1	106	1
Bin	FILTER_CONTROL_FCNB	1	0	1707	1
Bin	FILTER_CONTROL_FCNE	0	1	105	1
Bin	FILTER_CONTROL_FCNE	1	0	1706	1
Bin	FILTER_CONTROL_FCFB	0	1	107	1
Bin	FILTER_CONTROL_FCFB	1	0	1708	1
Bin	FILTER_CONTROL_FCFE	0	1	105	1
Bin	FILTER_CONTROL_FCFE	1	0	1706	1
Bin	FILTER_CONTROL_FRNB	0	1	6	1
Bin	FILTER_CONTROL_FRNB	1	0	1607	1
Bin	FILTER_CONTROL_FRNE	0	1	5	1
Bin	FILTER_CONTROL_FRNE	1	0	1606	1
Bin	FILTER_CONTROL_FRFB	0	1	6	1
Bin	FILTER_CONTROL_FRFB	1	0	1607	1
Bin	FILTER_CONTROL_FRFE	0	1	5	1
Bin	FILTER_CONTROL_FRFE	1	0	1606	1
Bin	RX_SETTINGS_RTSOP	0	1	5	1
Bin	RX_SETTINGS_RTSOP	1	0	1606	1
Bin	RX_DATA_READ	0	1	51013	1
Bin	RX_DATA_READ	1	0	52614	1
Bin	TX_COMMAND_TXCE	0	1	354	1
Bin	TX_COMMAND_TXCE	1	0	25291	1
Bin	TX_COMMAND_TXCR	0	1	21602	1
Bin	TX_COMMAND_TXCR	1	0	25291	1
Bin	TX_COMMAND_TXCA	0	1	1734	1
Bin	TX_COMMAND_TXCA	1	0	25291	1
Bin	TX_COMMAND_TXB1	0	1	6554	1
Bin	TX_COMMAND_TXB1	1	0	8151	1
Bin	TX_COMMAND_TXB2	0	1	5585	1
Bin	TX_COMMAND_TXB2	1	0	7186	1
Bin	TX_COMMAND_TXB3	0	1	319	1
Bin	TX_COMMAND_TXB3	1	0	1920	1
Bin	TX_COMMAND_TXB4	0	1	348	1
Bin	TX_COMMAND_TXB4	1	0	1949	1
Bin	TX_COMMAND_TXB5	0	1	84	1
Bin	TX_COMMAND_TXB5	1	0	1685	1
Bin	TX_COMMAND_TXB6	0	1	64	1
Bin	TX_COMMAND_TXB6	1	0	1665	1
Bin	TX_COMMAND_TXB7	0	1	76	1
Bin	TX_COMMAND_TXB7	1	0	1677	1
Bin	TX_COMMAND_TXB8	0	1	68	1
Bin	TX_COMMAND_TXB8	1	0	1669	1
Bin	TX_PRIORITY_TXT1P(2)	0	1	111	1
Bin	TX_PRIORITY_TXT1P(2)	1	0	1712	1
Bin	TX_PRIORITY_TXT1P(1)	0	1	113	1
Bin	TX_PRIORITY_TXT1P(1)	1	0	1714	1
Bin	TX_PRIORITY_TXT1P(0)	0	1	1721	1
Bin	TX_PRIORITY_TXT1P(0)	1	0	120	1
Bin	TX_PRIORITY_TXT2P(2)	0	1	93	1
Bin	TX_PRIORITY_TXT2P(2)	1	0	1694	1
Bin	TX_PRIORITY_TXT2P(1)	0	1	121	1
Bin	TX_PRIORITY_TXT2P(1)	1	0	1722	1
Bin	TX_PRIORITY_TXT2P(0)	0	1	119	1
Bin	TX_PRIORITY_TXT2P(0)	1	0	1720	1
Bin	TX_PRIORITY_TXT3P(2)	0	1	84	1
Bin	TX_PRIORITY_TXT3P(2)	1	0	1685	1
Bin	TX_PRIORITY_TXT3P(1)	0	1	92	1
Bin	TX_PRIORITY_TXT3P(1)	1	0	1693	1
Bin	TX_PRIORITY_TXT3P(0)	0	1	102	1
Bin	TX_PRIORITY_TXT3P(0)	1	0	1703	1
Bin	TX_PRIORITY_TXT4P(2)	0	1	85	1
Bin	TX_PRIORITY_TXT4P(2)	1	0	1686	1
Bin	TX_PRIORITY_TXT4P(1)	0	1	100	1
Bin	TX_PRIORITY_TXT4P(1)	1	0	1701	1
Bin	TX_PRIORITY_TXT4P(0)	0	1	87	1
Bin	TX_PRIORITY_TXT4P(0)	1	0	1688	1
Bin	TX_PRIORITY_TXT5P(2)	0	1	27	1
Bin	TX_PRIORITY_TXT5P(2)	1	0	1628	1
Bin	TX_PRIORITY_TXT5P(1)	0	1	29	1
Bin	TX_PRIORITY_TXT5P(1)	1	0	1630	1
Bin	TX_PRIORITY_TXT5P(0)	0	1	22	1
Bin	TX_PRIORITY_TXT5P(0)	1	0	1623	1
Bin	TX_PRIORITY_TXT6P(2)	0	1	17	1
Bin	TX_PRIORITY_TXT6P(2)	1	0	1618	1
Bin	TX_PRIORITY_TXT6P(1)	0	1	19	1
Bin	TX_PRIORITY_TXT6P(1)	1	0	1620	1
Bin	TX_PRIORITY_TXT6P(0)	0	1	23	1
Bin	TX_PRIORITY_TXT6P(0)	1	0	1624	1
Bin	TX_PRIORITY_TXT7P(2)	0	1	23	1
Bin	TX_PRIORITY_TXT7P(2)	1	0	1624	1
Bin	TX_PRIORITY_TXT7P(1)	0	1	22	1
Bin	TX_PRIORITY_TXT7P(1)	1	0	1623	1
Bin	TX_PRIORITY_TXT7P(0)	0	1	30	1
Bin	TX_PRIORITY_TXT7P(0)	1	0	1631	1
Bin	TX_PRIORITY_TXT8P(2)	0	1	25	1
Bin	TX_PRIORITY_TXT8P(2)	1	0	1626	1
Bin	TX_PRIORITY_TXT8P(1)	0	1	25	1
Bin	TX_PRIORITY_TXT8P(1)	1	0	1626	1
Bin	TX_PRIORITY_TXT8P(0)	0	1	20	1
Bin	TX_PRIORITY_TXT8P(0)	1	0	1621	1
Bin	SSP_CFG_SSP_OFFSET(7)	0	1	25	1
Bin	SSP_CFG_SSP_OFFSET(7)	1	0	1626	1
Bin	SSP_CFG_SSP_OFFSET(6)	0	1	27	1
Bin	SSP_CFG_SSP_OFFSET(6)	1	0	1628	1
Bin	SSP_CFG_SSP_OFFSET(5)	0	1	46	1
Bin	SSP_CFG_SSP_OFFSET(5)	1	0	1647	1
Bin	SSP_CFG_SSP_OFFSET(4)	0	1	53	1
Bin	SSP_CFG_SSP_OFFSET(4)	1	0	1654	1
Bin	SSP_CFG_SSP_OFFSET(3)	0	1	4303	1
Bin	SSP_CFG_SSP_OFFSET(3)	1	0	2714	1
Bin	SSP_CFG_SSP_OFFSET(2)	0	1	527	1
Bin	SSP_CFG_SSP_OFFSET(2)	1	0	2128	1
Bin	SSP_CFG_SSP_OFFSET(1)	0	1	2900	1
Bin	SSP_CFG_SSP_OFFSET(1)	1	0	1311	1
Bin	SSP_CFG_SSP_OFFSET(0)	0	1	2397	1
Bin	SSP_CFG_SSP_OFFSET(0)	1	0	3998	1
Bin	SSP_CFG_SSP_SRC(1)	0	1	45	1
Bin	SSP_CFG_SSP_SRC(1)	1	0	1646	1
Bin	SSP_CFG_SSP_SRC(0)	0	1	814	1
Bin	SSP_CFG_SSP_SRC(0)	1	0	2403	1

Signal:

MR_CTRL_IN

	Element	From	To	Count	Threshold
Bin	DEVICE_ID_DEVICE_ID(15)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(14)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(13)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(12)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(11)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(10)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(9)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(8)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(7)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(6)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(5)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(4)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(3)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(2)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(1)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(0)	0	1	1601	1
Bin	VERSION_VER_MINOR(7)	1	0	1601	1
Bin	VERSION_VER_MINOR(6)	1	0	1601	1
Bin	VERSION_VER_MINOR(5)	1	0	1601	1
Bin	VERSION_VER_MINOR(4)	1	0	1601	1
Bin	VERSION_VER_MINOR(3)	1	0	1601	1
Bin	VERSION_VER_MINOR(2)	0	1	1601	1
Bin	VERSION_VER_MINOR(1)	0	1	1601	1
Bin	VERSION_VER_MINOR(0)	0	1	1601	1
Bin	VERSION_VER_MAJOR(7)	1	0	1601	1
Bin	VERSION_VER_MAJOR(6)	1	0	1601	1
Bin	VERSION_VER_MAJOR(5)	1	0	1601	1
Bin	VERSION_VER_MAJOR(4)	1	0	1601	1
Bin	VERSION_VER_MAJOR(3)	1	0	1601	1
Bin	VERSION_VER_MAJOR(2)	1	0	1601	1
Bin	VERSION_VER_MAJOR(1)	0	1	1601	1
Bin	VERSION_VER_MAJOR(0)	1	0	1601	1
Bin	STATUS_RXNE	0	1	8952	1
Bin	STATUS_RXNE	1	0	8950	1
Bin	STATUS_DOR	0	1	31	1
Bin	STATUS_DOR	1	0	1632	1
Bin	STATUS_TXNF	0	1	2478	1
Bin	STATUS_TXNF	1	0	2478	1
Bin	STATUS_EFT	0	1	27358	1
Bin	STATUS_EFT	1	0	28953	1
Bin	STATUS_RXS	0	1	30873	1
Bin	STATUS_RXS	1	0	32467	1
Bin	STATUS_TXS	0	1	20560	1
Bin	STATUS_TXS	1	0	22161	1
Bin	STATUS_EWL	0	1	780	1
Bin	STATUS_EWL	1	0	2380	1
Bin	STATUS_IDLE	0	1	51661	1
Bin	STATUS_IDLE	1	0	51668	1
Bin	STATUS_PEXS	0	1	75	1
Bin	STATUS_PEXS	1	0	1676	1
Bin	STATUS_RXPE	0	1	13	1
Bin	STATUS_RXPE	1	0	1614	1
Bin	STATUS_TXPE	0	1	301	1
Bin	STATUS_TXPE	1	0	1902	1
Bin	STATUS_TXDPE	0	1	44	1
Bin	STATUS_TXDPE	1	0	1645	1
Bin	STATUS_STCNT	0	1	660	1
Bin	STATUS_STCNT	1	0	941	1
Bin	STATUS_STRGS	0	1	1601	1
Bin	STATUS_SPRT	0	1	660	1
Bin	STATUS_SPRT	1	0	941	1
Bin	INT_STAT_RXI	0	1	806	1
Bin	INT_STAT_RXI	1	0	2405	1
Bin	INT_STAT_TXI	0	1	1214	1
Bin	INT_STAT_TXI	1	0	2811	1
Bin	INT_STAT_EWLI	0	1	594	1
Bin	INT_STAT_EWLI	1	0	2194	1
Bin	INT_STAT_DOI	0	1	21	1
Bin	INT_STAT_DOI	1	0	1622	1
Bin	INT_STAT_FCSI	0	1	3304	1
Bin	INT_STAT_FCSI	1	0	4893	1
Bin	INT_STAT_ALI	0	1	100	1
Bin	INT_STAT_ALI	1	0	1699	1
Bin	INT_STAT_BEI	0	1	1417	1
Bin	INT_STAT_BEI	1	0	3010	1
Bin	INT_STAT_OFI	0	1	152	1
Bin	INT_STAT_OFI	1	0	1753	1
Bin	INT_STAT_RXFI	0	1	20	1
Bin	INT_STAT_RXFI	1	0	1621	1
Bin	INT_STAT_BSI	0	1	1311	1
Bin	INT_STAT_BSI	1	0	2905	1
Bin	INT_STAT_RBNEI	0	1	934	1
Bin	INT_STAT_RBNEI	1	0	2533	1
Bin	INT_STAT_TXBHCI	0	1	1679	1
Bin	INT_STAT_TXBHCI	1	0	3276	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	1667	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	1631	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	1651	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	1621	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	1616	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	22	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	1623	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	20	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	1621	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	20	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	1621	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	1611	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	1611	1
Bin	FAULT_STATE_ERA	0	1	8426	1
Bin	FAULT_STATE_ERA	1	0	8415	1
Bin	FAULT_STATE_ERP	0	1	771	1
Bin	FAULT_STATE_ERP	1	0	2372	1
Bin	FAULT_STATE_BOF	0	1	8227	1
Bin	FAULT_STATE_BOF	1	0	8238	1
Bin	REC_REC_VAL(8)	0	1	130	1
Bin	REC_REC_VAL(8)	1	0	1731	1
Bin	REC_REC_VAL(7)	0	1	350	1
Bin	REC_REC_VAL(7)	1	0	1951	1
Bin	REC_REC_VAL(6)	0	1	255	1
Bin	REC_REC_VAL(6)	1	0	1854	1
Bin	REC_REC_VAL(5)	0	1	363	1
Bin	REC_REC_VAL(5)	1	0	1963	1
Bin	REC_REC_VAL(4)	0	1	497	1
Bin	REC_REC_VAL(4)	1	0	2098	1
Bin	REC_REC_VAL(3)	0	1	685	1
Bin	REC_REC_VAL(3)	1	0	2285	1
Bin	REC_REC_VAL(2)	0	1	617	1
Bin	REC_REC_VAL(2)	1	0	2218	1
Bin	REC_REC_VAL(1)	0	1	1191	1
Bin	REC_REC_VAL(1)	1	0	2792	1
Bin	REC_REC_VAL(0)	0	1	11216	1
Bin	REC_REC_VAL(0)	1	0	12809	1
Bin	TEC_TEC_VAL(8)	0	1	249	1
Bin	TEC_TEC_VAL(8)	1	0	1850	1
Bin	TEC_TEC_VAL(7)	0	1	517	1
Bin	TEC_TEC_VAL(7)	1	0	2118	1
Bin	TEC_TEC_VAL(6)	0	1	501	1
Bin	TEC_TEC_VAL(6)	1	0	2102	1
Bin	TEC_TEC_VAL(5)	0	1	805	1
Bin	TEC_TEC_VAL(5)	1	0	2406	1
Bin	TEC_TEC_VAL(4)	0	1	1933	1
Bin	TEC_TEC_VAL(4)	1	0	3534	1
Bin	TEC_TEC_VAL(3)	0	1	12743	1
Bin	TEC_TEC_VAL(3)	1	0	14344	1
Bin	TEC_TEC_VAL(2)	0	1	2955	1
Bin	TEC_TEC_VAL(2)	1	0	4556	1
Bin	TEC_TEC_VAL(1)	0	1	3324	1
Bin	TEC_TEC_VAL(1)	1	0	4925	1
Bin	TEC_TEC_VAL(0)	0	1	3524	1
Bin	TEC_TEC_VAL(0)	1	0	5125	1
Bin	ERR_NORM_ERR_NORM_VAL(15)	0	1	69	1
Bin	ERR_NORM_ERR_NORM_VAL(15)	1	0	1667	1
Bin	ERR_NORM_ERR_NORM_VAL(14)	0	1	67	1
Bin	ERR_NORM_ERR_NORM_VAL(14)	1	0	1668	1
Bin	ERR_NORM_ERR_NORM_VAL(13)	0	1	64	1
Bin	ERR_NORM_ERR_NORM_VAL(13)	1	0	1661	1
Bin	ERR_NORM_ERR_NORM_VAL(12)	0	1	62	1
Bin	ERR_NORM_ERR_NORM_VAL(12)	1	0	1659	1
Bin	ERR_NORM_ERR_NORM_VAL(11)	0	1	64	1
Bin	ERR_NORM_ERR_NORM_VAL(11)	1	0	1664	1
Bin	ERR_NORM_ERR_NORM_VAL(10)	0	1	69	1
Bin	ERR_NORM_ERR_NORM_VAL(10)	1	0	1668	1
Bin	ERR_NORM_ERR_NORM_VAL(9)	0	1	63	1
Bin	ERR_NORM_ERR_NORM_VAL(9)	1	0	1662	1
Bin	ERR_NORM_ERR_NORM_VAL(8)	0	1	71	1
Bin	ERR_NORM_ERR_NORM_VAL(8)	1	0	1671	1
Bin	ERR_NORM_ERR_NORM_VAL(7)	0	1	75	1
Bin	ERR_NORM_ERR_NORM_VAL(7)	1	0	1673	1
Bin	ERR_NORM_ERR_NORM_VAL(6)	0	1	97	1
Bin	ERR_NORM_ERR_NORM_VAL(6)	1	0	1696	1
Bin	ERR_NORM_ERR_NORM_VAL(5)	0	1	155	1
Bin	ERR_NORM_ERR_NORM_VAL(5)	1	0	1752	1
Bin	ERR_NORM_ERR_NORM_VAL(4)	0	1	276	1
Bin	ERR_NORM_ERR_NORM_VAL(4)	1	0	1876	1
Bin	ERR_NORM_ERR_NORM_VAL(3)	0	1	608	1
Bin	ERR_NORM_ERR_NORM_VAL(3)	1	0	2205	1
Bin	ERR_NORM_ERR_NORM_VAL(2)	0	1	1361	1
Bin	ERR_NORM_ERR_NORM_VAL(2)	1	0	2958	1
Bin	ERR_NORM_ERR_NORM_VAL(1)	0	1	3082	1
Bin	ERR_NORM_ERR_NORM_VAL(1)	1	0	4678	1
Bin	ERR_NORM_ERR_NORM_VAL(0)	0	1	11727	1
Bin	ERR_NORM_ERR_NORM_VAL(0)	1	0	13323	1
Bin	ERR_FD_ERR_FD_VAL(15)	0	1	63	1
Bin	ERR_FD_ERR_FD_VAL(15)	1	0	1661	1
Bin	ERR_FD_ERR_FD_VAL(14)	0	1	68	1
Bin	ERR_FD_ERR_FD_VAL(14)	1	0	1667	1
Bin	ERR_FD_ERR_FD_VAL(13)	0	1	67	1
Bin	ERR_FD_ERR_FD_VAL(13)	1	0	1665	1
Bin	ERR_FD_ERR_FD_VAL(12)	0	1	65	1
Bin	ERR_FD_ERR_FD_VAL(12)	1	0	1665	1
Bin	ERR_FD_ERR_FD_VAL(11)	0	1	61	1
Bin	ERR_FD_ERR_FD_VAL(11)	1	0	1658	1
Bin	ERR_FD_ERR_FD_VAL(10)	0	1	64	1
Bin	ERR_FD_ERR_FD_VAL(10)	1	0	1661	1
Bin	ERR_FD_ERR_FD_VAL(9)	0	1	75	1
Bin	ERR_FD_ERR_FD_VAL(9)	1	0	1673	1
Bin	ERR_FD_ERR_FD_VAL(8)	0	1	85	1
Bin	ERR_FD_ERR_FD_VAL(8)	1	0	1682	1
Bin	ERR_FD_ERR_FD_VAL(7)	0	1	98	1
Bin	ERR_FD_ERR_FD_VAL(7)	1	0	1696	1
Bin	ERR_FD_ERR_FD_VAL(6)	0	1	133	1
Bin	ERR_FD_ERR_FD_VAL(6)	1	0	1732	1
Bin	ERR_FD_ERR_FD_VAL(5)	0	1	209	1
Bin	ERR_FD_ERR_FD_VAL(5)	1	0	1805	1
Bin	ERR_FD_ERR_FD_VAL(4)	0	1	352	1
Bin	ERR_FD_ERR_FD_VAL(4)	1	0	1952	1
Bin	ERR_FD_ERR_FD_VAL(3)	0	1	680	1
Bin	ERR_FD_ERR_FD_VAL(3)	1	0	2278	1
Bin	ERR_FD_ERR_FD_VAL(2)	0	1	1295	1
Bin	ERR_FD_ERR_FD_VAL(2)	1	0	2895	1
Bin	ERR_FD_ERR_FD_VAL(1)	0	1	2523	1
Bin	ERR_FD_ERR_FD_VAL(1)	1	0	4120	1
Bin	ERR_FD_ERR_FD_VAL(0)	0	1	5589	1
Bin	ERR_FD_ERR_FD_VAL(0)	1	0	7187	1
Bin	FILTER_STATUS_SFA	0	1	660	1
Bin	FILTER_STATUS_SFA	1	0	941	1
Bin	FILTER_STATUS_SFB	0	1	165	1
Bin	FILTER_STATUS_SFB	1	0	1436	1
Bin	FILTER_STATUS_SFC	0	1	165	1
Bin	FILTER_STATUS_SFC	1	0	1436	1
Bin	FILTER_STATUS_SFR	0	1	165	1
Bin	FILTER_STATUS_SFR	1	0	1436	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(12)	0	1	165	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(12)	1	0	1436	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(11)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(10)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(9)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(8)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(7)	0	1	495	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(7)	1	0	1106	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(6)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(5)	0	1	941	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(5)	1	0	660	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(4)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(3)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(2)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(1)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(0)	1	0	1601	1
Bin	RX_MEM_INFO_RX_MEM_FREE(12)	0	1	1206	1
Bin	RX_MEM_INFO_RX_MEM_FREE(12)	1	0	48788	1
Bin	RX_MEM_INFO_RX_MEM_FREE(11)	0	1	1043	1
Bin	RX_MEM_INFO_RX_MEM_FREE(11)	1	0	48955	1
Bin	RX_MEM_INFO_RX_MEM_FREE(10)	0	1	1050	1
Bin	RX_MEM_INFO_RX_MEM_FREE(10)	1	0	48962	1
Bin	RX_MEM_INFO_RX_MEM_FREE(9)	0	1	1064	1
Bin	RX_MEM_INFO_RX_MEM_FREE(9)	1	0	48976	1
Bin	RX_MEM_INFO_RX_MEM_FREE(8)	0	1	1092	1
Bin	RX_MEM_INFO_RX_MEM_FREE(8)	1	0	49004	1
Bin	RX_MEM_INFO_RX_MEM_FREE(7)	0	1	4484	1
Bin	RX_MEM_INFO_RX_MEM_FREE(7)	1	0	30134	1
Bin	RX_MEM_INFO_RX_MEM_FREE(6)	0	1	4111	1
Bin	RX_MEM_INFO_RX_MEM_FREE(6)	1	0	30751	1
Bin	RX_MEM_INFO_RX_MEM_FREE(5)	0	1	8775	1
Bin	RX_MEM_INFO_RX_MEM_FREE(5)	1	0	8496	1
Bin	RX_MEM_INFO_RX_MEM_FREE(4)	0	1	8358	1
Bin	RX_MEM_INFO_RX_MEM_FREE(4)	1	0	9957	1
Bin	RX_MEM_INFO_RX_MEM_FREE(3)	0	1	9825	1
Bin	RX_MEM_INFO_RX_MEM_FREE(3)	1	0	11424	1
Bin	RX_MEM_INFO_RX_MEM_FREE(2)	0	1	12159	1
Bin	RX_MEM_INFO_RX_MEM_FREE(2)	1	0	13758	1
Bin	RX_MEM_INFO_RX_MEM_FREE(1)	0	1	15624	1
Bin	RX_MEM_INFO_RX_MEM_FREE(1)	1	0	17225	1
Bin	RX_MEM_INFO_RX_MEM_FREE(0)	0	1	26860	1
Bin	RX_MEM_INFO_RX_MEM_FREE(0)	1	0	28461	1
Bin	RX_POINTERS_RX_WPP(11)	0	1	6	1
Bin	RX_POINTERS_RX_WPP(11)	1	0	11710	1
Bin	RX_POINTERS_RX_WPP(10)	0	1	11	1
Bin	RX_POINTERS_RX_WPP(10)	1	0	11715	1
Bin	RX_POINTERS_RX_WPP(9)	0	1	23	1
Bin	RX_POINTERS_RX_WPP(9)	1	0	11727	1
Bin	RX_POINTERS_RX_WPP(8)	0	1	46	1
Bin	RX_POINTERS_RX_WPP(8)	1	0	11750	1
Bin	RX_POINTERS_RX_WPP(7)	0	1	91	1
Bin	RX_POINTERS_RX_WPP(7)	1	0	11795	1
Bin	RX_POINTERS_RX_WPP(6)	0	1	304	1
Bin	RX_POINTERS_RX_WPP(6)	1	0	6954	1
Bin	RX_POINTERS_RX_WPP(5)	0	1	663	1
Bin	RX_POINTERS_RX_WPP(5)	1	0	7313	1
Bin	RX_POINTERS_RX_WPP(4)	0	1	1946	1
Bin	RX_POINTERS_RX_WPP(4)	1	0	3547	1
Bin	RX_POINTERS_RX_WPP(3)	0	1	3727	1
Bin	RX_POINTERS_RX_WPP(3)	1	0	5328	1
Bin	RX_POINTERS_RX_WPP(2)	0	1	6176	1
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Bin	ALC_ALC_ID_FIELD(0)	0	1	95	1
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Bin	TS_INFO_TS_BITS(4)	0	1	1601	1
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Bin	TS_INFO_TS_BITS(0)	0	1	1601	1
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Bin	TRV_DELAY_TRV_DELAY_VALUE(5)	0	1	69	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(5)	1	0	1670	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(4)	0	1	86	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(4)	1	0	1687	1
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Bin	TRV_DELAY_TRV_DELAY_VALUE(3)	1	0	1678	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(2)	0	1	85	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(2)	1	0	1686	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(1)	0	1	2178	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(1)	1	0	3779	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(0)	0	1	67	1
Bin	TRV_DELAY_TRV_DELAY_VALUE(0)	1	0	1668	1
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Bin	RX_FR_CTR_RX_FR_CTR_VAL(31)	1	0	1649	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(30)	0	1	56	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(30)	1	0	1654	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(29)	0	1	51	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(29)	1	0	1648	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(28)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(28)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(27)	0	1	47	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(27)	1	0	1646	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(26)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(26)	1	0	1653	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(25)	0	1	51	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(25)	1	0	1649	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(24)	0	1	47	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(24)	1	0	1646	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(23)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(23)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(22)	0	1	56	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(22)	1	0	1655	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(21)	0	1	50	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(21)	1	0	1650	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(20)	0	1	52	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(20)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(19)	0	1	50	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(19)	1	0	1649	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(18)	0	1	51	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(18)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(17)	0	1	52	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(17)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(16)	0	1	60	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(16)	1	0	1658	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(15)	0	1	50	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(15)	1	0	1649	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(14)	0	1	51	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(14)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(13)	0	1	46	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(13)	1	0	1647	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(12)	0	1	48	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(12)	1	0	1648	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(11)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(11)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(10)	0	1	62	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(10)	1	0	1659	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(9)	0	1	55	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(9)	1	0	1654	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(8)	0	1	65	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(8)	1	0	1665	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(7)	0	1	79	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(7)	1	0	1678	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(6)	0	1	111	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(6)	1	0	1710	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(5)	0	1	220	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(5)	1	0	1820	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(4)	0	1	354	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(4)	1	0	1952	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(3)	0	1	751	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(3)	1	0	2351	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(2)	0	1	1498	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(2)	1	0	3095	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(1)	0	1	2960	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(1)	1	0	4559	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(0)	0	1	5900	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(0)	1	0	7500	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(31)	0	1	92	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(31)	1	0	1693	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(30)	0	1	102	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(30)	1	0	1703	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(29)	0	1	108	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(29)	1	0	1709	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(28)	0	1	102	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(28)	1	0	1703	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(27)	0	1	99	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(27)	1	0	1700	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(26)	0	1	111	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(26)	1	0	1712	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(25)	0	1	106	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(25)	1	0	1707	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(24)	0	1	108	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(24)	1	0	1709	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(23)	0	1	100	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(23)	1	0	1701	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(22)	0	1	99	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(22)	1	0	1700	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(21)	0	1	104	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(21)	1	0	1705	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(20)	0	1	104	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(20)	1	0	1705	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(19)	0	1	104	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(19)	1	0	1705	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(18)	0	1	95	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(18)	1	0	1696	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(17)	0	1	101	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(17)	1	0	1702	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(16)	0	1	95	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(16)	1	0	1696	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(15)	0	1	106	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(15)	1	0	1707	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(14)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(14)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(13)	0	1	109	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(13)	1	0	1710	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(12)	0	1	110	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(12)	1	0	1711	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(11)	0	1	98	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(11)	1	0	1699	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(10)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(10)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(9)	0	1	102	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(9)	1	0	1703	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(8)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(8)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(7)	0	1	112	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(7)	1	0	1713	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(6)	0	1	110	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(6)	1	0	1711	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(5)	0	1	126	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(5)	1	0	1727	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(4)	0	1	154	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(4)	1	0	1755	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(3)	0	1	261	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(3)	1	0	1862	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(2)	0	1	603	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(2)	1	0	2204	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(1)	0	1	1075	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(1)	1	0	2676	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(0)	0	1	2217	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(0)	1	0	3818	1
Bin	DEBUG_REGISTER_STUFF_COUNT(2)	0	1	33793	1
Bin	DEBUG_REGISTER_STUFF_COUNT(2)	1	0	35393	1
Bin	DEBUG_REGISTER_STUFF_COUNT(1)	0	1	71746	1
Bin	DEBUG_REGISTER_STUFF_COUNT(1)	1	0	73346	1
Bin	DEBUG_REGISTER_STUFF_COUNT(0)	0	1	142471	1
Bin	DEBUG_REGISTER_STUFF_COUNT(0)	1	0	144071	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(2)	0	1	117167	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(2)	1	0	118766	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(1)	0	1	243244	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(1)	1	0	244841	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(0)	0	1	487033	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(0)	1	0	488629	1
Bin	DEBUG_REGISTER_PC_ARB	0	1	55910	1
Bin	DEBUG_REGISTER_PC_ARB	1	0	57511	1
Bin	DEBUG_REGISTER_PC_CON	0	1	51266	1
Bin	DEBUG_REGISTER_PC_CON	1	0	52867	1
Bin	DEBUG_REGISTER_PC_DAT	0	1	36655	1
Bin	DEBUG_REGISTER_PC_DAT	1	0	38256	1
Bin	DEBUG_REGISTER_PC_STC	0	1	13017	1
Bin	DEBUG_REGISTER_PC_STC	1	0	14618	1
Bin	DEBUG_REGISTER_PC_CRC	0	1	31164	1
Bin	DEBUG_REGISTER_PC_CRC	1	0	32765	1
Bin	DEBUG_REGISTER_PC_CRCD	0	1	29702	1
Bin	DEBUG_REGISTER_PC_CRCD	1	0	31303	1
Bin	DEBUG_REGISTER_PC_ACK	0	1	29548	1
Bin	DEBUG_REGISTER_PC_ACK	1	0	31149	1
Bin	DEBUG_REGISTER_PC_ACKD	0	1	28120	1
Bin	DEBUG_REGISTER_PC_ACKD	1	0	29721	1
Bin	DEBUG_REGISTER_PC_EOF	0	1	27225	1
Bin	DEBUG_REGISTER_PC_EOF	1	0	28826	1
Bin	DEBUG_REGISTER_PC_INT	0	1	51904	1
Bin	DEBUG_REGISTER_PC_INT	1	0	53504	1
Bin	DEBUG_REGISTER_PC_SUSP	0	1	2849	1
Bin	DEBUG_REGISTER_PC_SUSP	1	0	4450	1
Bin	DEBUG_REGISTER_PC_OVR	0	1	529	1
Bin	DEBUG_REGISTER_PC_OVR	1	0	2130	1
Bin	DEBUG_REGISTER_PC_SOF	0	1	25148	1
Bin	DEBUG_REGISTER_PC_SOF	1	0	26749	1
Bin	YOLO_REG_YOLO_VAL(31)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(30)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(29)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(28)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(27)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(26)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(25)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(24)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(23)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(22)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(21)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(20)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(19)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(18)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(17)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(16)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(15)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(14)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(13)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(12)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(11)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(10)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(9)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(8)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(7)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(6)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(5)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(4)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(3)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(2)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(1)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(0)	0	1	1601	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(31)	0	1	38	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(31)	1	0	1636	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(30)	0	1	61	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(30)	1	0	1651	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(29)	0	1	59	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(29)	1	0	1654	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(28)	0	1	61	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(28)	1	0	1655	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(27)	0	1	65	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(27)	1	0	1656	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(26)	0	1	65	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(26)	1	0	1658	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(25)	0	1	63	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(25)	1	0	1655	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(24)	0	1	69	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(24)	1	0	1656	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(23)	0	1	77	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(23)	1	0	1660	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(22)	0	1	110	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(22)	1	0	1675	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(21)	0	1	156	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(21)	1	0	1719	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(20)	0	1	257	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(20)	1	0	1806	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(19)	0	1	554	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(19)	1	0	2000	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(18)	0	1	1008	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(18)	1	0	2483	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(17)	0	1	2083	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(17)	1	0	3434	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(16)	0	1	4194	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(16)	1	0	5456	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(15)	0	1	8321	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(15)	1	0	9580	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(14)	0	1	16718	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(14)	1	0	17846	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(13)	0	1	33448	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(13)	1	0	34513	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(12)	0	1	66941	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(12)	1	0	67907	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(11)	0	1	133890	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(11)	1	0	134789	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(10)	0	1	267819	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(10)	1	0	268629	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(9)	0	1	535562	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(9)	1	0	536378	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(8)	0	1	1071138	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(8)	1	0	1071905	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(7)	0	1	2142151	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(7)	1	0	2142981	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(6)	0	1	4284253	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(6)	1	0	4285090	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(5)	0	1	8568494	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(5)	1	0	8569288	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(4)	0	1	17136945	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(4)	1	0	17137726	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(3)	0	1	34273776	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(3)	1	0	34274622	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(2)	0	1	68547550	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(2)	1	0	68548333	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(1)	0	1	137095031	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(1)	1	0	137095833	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(0)	0	1	274190040	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(0)	1	0	274190818	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(31)	0	1	17	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(31)	1	0	1616	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(30)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(30)	1	0	1657	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(29)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(29)	1	0	1661	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(28)	0	1	72	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(28)	1	0	1661	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(27)	0	1	71	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(27)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(26)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(26)	1	0	1663	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(25)	0	1	63	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(25)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(24)	0	1	77	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(24)	1	0	1665	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(23)	0	1	64	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(23)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(22)	0	1	72	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(22)	1	0	1663	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(21)	0	1	71	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(21)	1	0	1665	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(20)	0	1	69	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(20)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(19)	0	1	67	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(19)	1	0	1656	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(18)	0	1	68	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(18)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(17)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(17)	1	0	1654	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(16)	0	1	68	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(16)	1	0	1661	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(15)	0	1	64	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(15)	1	0	1654	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(14)	0	1	70	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(14)	1	0	1660	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(13)	0	1	57	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(13)	1	0	1651	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(12)	0	1	71	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(12)	1	0	1666	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(11)	0	1	63	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(11)	1	0	1653	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(10)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(10)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(9)	0	1	75	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(9)	1	0	1666	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(8)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(8)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(7)	0	1	63	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(7)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(6)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(6)	1	0	1654	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(5)	0	1	67	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(5)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(4)	0	1	59	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(4)	1	0	1651	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(3)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(3)	1	0	1657	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(2)	0	1	68	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(2)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(1)	0	1	67	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(1)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(0)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(0)	1	0	1667	1

Signal:

MR_TST_OUT_I

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32324	1
Bin	TST_CONTROL_TWRSTB	1	0	35216	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(11)	0	1	15	1
Bin	TST_DEST_TST_ADDR(11)	1	0	1616	1
Bin	TST_DEST_TST_ADDR(10)	0	1	25	1
Bin	TST_DEST_TST_ADDR(10)	1	0	1626	1
Bin	TST_DEST_TST_ADDR(9)	0	1	45	1
Bin	TST_DEST_TST_ADDR(9)	1	0	1646	1
Bin	TST_DEST_TST_ADDR(8)	0	1	85	1
Bin	TST_DEST_TST_ADDR(8)	1	0	1686	1
Bin	TST_DEST_TST_ADDR(7)	0	1	165	1
Bin	TST_DEST_TST_ADDR(7)	1	0	1766	1
Bin	TST_DEST_TST_ADDR(6)	0	1	355	1
Bin	TST_DEST_TST_ADDR(6)	1	0	1956	1
Bin	TST_DEST_TST_ADDR(5)	0	1	705	1
Bin	TST_DEST_TST_ADDR(5)	1	0	2306	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3615	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5216	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5035	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6636	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10345	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11946	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22457	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24058	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44877	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46478	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	375	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1976	1
Bin	TST_DEST_TST_MTGT(1)	0	1	517	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2118	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1479	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3080	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1508	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3109	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1591	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3192	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1642	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3243	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1637	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3238	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1645	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3246	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1692	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3293	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1558	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3159	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1525	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3126	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1560	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3161	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3255	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3255	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1640	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3241	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1672	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3273	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1556	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3157	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1518	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3119	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3130	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1616	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3217	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1671	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3272	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1638	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3239	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1709	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3310	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1561	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3162	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1564	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3165	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1568	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3169	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1667	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3268	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1663	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3264	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1642	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3243	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1675	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3276	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1719	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3320	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1604	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3205	1

Signal:

MR_TST_IN

	Element	From	To	Count	Threshold
Bin	TST_RDATA_TST_RDATA(31)	0	1	23972	1
Bin	TST_RDATA_TST_RDATA(31)	1	0	21066	1
Bin	TST_RDATA_TST_RDATA(30)	0	1	15049	1
Bin	TST_RDATA_TST_RDATA(30)	1	0	21162	1
Bin	TST_RDATA_TST_RDATA(29)	0	1	19510	1
Bin	TST_RDATA_TST_RDATA(29)	1	0	16604	1
Bin	TST_RDATA_TST_RDATA(28)	0	1	19954	1
Bin	TST_RDATA_TST_RDATA(28)	1	0	26067	1
Bin	TST_RDATA_TST_RDATA(27)	0	1	19841	1
Bin	TST_RDATA_TST_RDATA(27)	1	0	16935	1
Bin	TST_RDATA_TST_RDATA(26)	0	1	19833	1
Bin	TST_RDATA_TST_RDATA(26)	1	0	25946	1
Bin	TST_RDATA_TST_RDATA(25)	0	1	24479	1
Bin	TST_RDATA_TST_RDATA(25)	1	0	21573	1
Bin	TST_RDATA_TST_RDATA(24)	0	1	15192	1
Bin	TST_RDATA_TST_RDATA(24)	1	0	21305	1
Bin	TST_RDATA_TST_RDATA(23)	0	1	24304	1
Bin	TST_RDATA_TST_RDATA(23)	1	0	21398	1
Bin	TST_RDATA_TST_RDATA(22)	0	1	15397	1
Bin	TST_RDATA_TST_RDATA(22)	1	0	21510	1
Bin	TST_RDATA_TST_RDATA(21)	0	1	19868	1
Bin	TST_RDATA_TST_RDATA(21)	1	0	16962	1
Bin	TST_RDATA_TST_RDATA(20)	0	1	19941	1
Bin	TST_RDATA_TST_RDATA(20)	1	0	26054	1
Bin	TST_RDATA_TST_RDATA(19)	0	1	19868	1
Bin	TST_RDATA_TST_RDATA(19)	1	0	16962	1
Bin	TST_RDATA_TST_RDATA(18)	0	1	19858	1
Bin	TST_RDATA_TST_RDATA(18)	1	0	25971	1
Bin	TST_RDATA_TST_RDATA(17)	0	1	24354	1
Bin	TST_RDATA_TST_RDATA(17)	1	0	21448	1
Bin	TST_RDATA_TST_RDATA(16)	0	1	15073	1
Bin	TST_RDATA_TST_RDATA(16)	1	0	21186	1
Bin	TST_RDATA_TST_RDATA(15)	0	1	24182	1
Bin	TST_RDATA_TST_RDATA(15)	1	0	21276	1
Bin	TST_RDATA_TST_RDATA(14)	0	1	15247	1
Bin	TST_RDATA_TST_RDATA(14)	1	0	21360	1
Bin	TST_RDATA_TST_RDATA(13)	0	1	19700	1
Bin	TST_RDATA_TST_RDATA(13)	1	0	16794	1
Bin	TST_RDATA_TST_RDATA(12)	0	1	19883	1
Bin	TST_RDATA_TST_RDATA(12)	1	0	25996	1
Bin	TST_RDATA_TST_RDATA(11)	0	1	19769	1
Bin	TST_RDATA_TST_RDATA(11)	1	0	16863	1
Bin	TST_RDATA_TST_RDATA(10)	0	1	19708	1
Bin	TST_RDATA_TST_RDATA(10)	1	0	25821	1
Bin	TST_RDATA_TST_RDATA(9)	0	1	24435	1
Bin	TST_RDATA_TST_RDATA(9)	1	0	21529	1
Bin	TST_RDATA_TST_RDATA(8)	0	1	15098	1
Bin	TST_RDATA_TST_RDATA(8)	1	0	21211	1
Bin	TST_RDATA_TST_RDATA(7)	0	1	24352	1
Bin	TST_RDATA_TST_RDATA(7)	1	0	21446	1
Bin	TST_RDATA_TST_RDATA(6)	0	1	15389	1
Bin	TST_RDATA_TST_RDATA(6)	1	0	21502	1
Bin	TST_RDATA_TST_RDATA(5)	0	1	19757	1
Bin	TST_RDATA_TST_RDATA(5)	1	0	16851	1
Bin	TST_RDATA_TST_RDATA(4)	0	1	19852	1
Bin	TST_RDATA_TST_RDATA(4)	1	0	25965	1
Bin	TST_RDATA_TST_RDATA(3)	0	1	19797	1
Bin	TST_RDATA_TST_RDATA(3)	1	0	16891	1
Bin	TST_RDATA_TST_RDATA(2)	0	1	19796	1
Bin	TST_RDATA_TST_RDATA(2)	1	0	25909	1
Bin	TST_RDATA_TST_RDATA(1)	0	1	24433	1
Bin	TST_RDATA_TST_RDATA(1)	1	0	21527	1
Bin	TST_RDATA_TST_RDATA(0)	0	1	15201	1
Bin	TST_RDATA_TST_RDATA(0)	1	0	21314	1

Signal:

MR_TST_RDATA_TST_RDATA_TXB_I

	Element	From	To	Count	Threshold
Bin	(7)(31)	0	1	113	1
Bin	(7)(31)	1	0	14573	1
Bin	(7)(30)	0	1	109	1
Bin	(7)(30)	1	0	14569	1
Bin	(7)(29)	0	1	117	1
Bin	(7)(29)	1	0	14577	1
Bin	(7)(28)	0	1	126	1
Bin	(7)(28)	1	0	14586	1
Bin	(7)(27)	0	1	120	1
Bin	(7)(27)	1	0	14580	1
Bin	(7)(26)	0	1	132	1
Bin	(7)(26)	1	0	14592	1
Bin	(7)(25)	0	1	123	1
Bin	(7)(25)	1	0	14583	1
Bin	(7)(24)	0	1	115	1
Bin	(7)(24)	1	0	14575	1
Bin	(7)(23)	0	1	117	1
Bin	(7)(23)	1	0	14577	1
Bin	(7)(22)	0	1	118	1
Bin	(7)(22)	1	0	14578	1
Bin	(7)(21)	0	1	122	1
Bin	(7)(21)	1	0	14582	1
Bin	(7)(20)	0	1	120	1
Bin	(7)(20)	1	0	14580	1
Bin	(7)(19)	0	1	117	1
Bin	(7)(19)	1	0	14577	1
Bin	(7)(18)	0	1	124	1
Bin	(7)(18)	1	0	14584	1
Bin	(7)(17)	0	1	120	1
Bin	(7)(17)	1	0	14580	1
Bin	(7)(16)	0	1	125	1
Bin	(7)(16)	1	0	14626	1
Bin	(7)(15)	0	1	127	1
Bin	(7)(15)	1	0	14587	1
Bin	(7)(14)	0	1	111	1
Bin	(7)(14)	1	0	14571	1
Bin	(7)(13)	0	1	122	1
Bin	(7)(13)	1	0	14582	1
Bin	(7)(12)	0	1	118	1
Bin	(7)(12)	1	0	14578	1
Bin	(7)(11)	0	1	124	1
Bin	(7)(11)	1	0	14584	1
Bin	(7)(10)	0	1	122	1
Bin	(7)(10)	1	0	14582	1
Bin	(7)(9)	0	1	125	1
Bin	(7)(9)	1	0	14894	1
Bin	(7)(8)	0	1	122	1
Bin	(7)(8)	1	0	14582	1
Bin	(7)(7)	0	1	128	1
Bin	(7)(7)	1	0	14897	1
Bin	(7)(6)	0	1	125	1
Bin	(7)(6)	1	0	14585	1
Bin	(7)(5)	0	1	112	1
Bin	(7)(5)	1	0	14572	1
Bin	(7)(4)	0	1	124	1
Bin	(7)(4)	1	0	14584	1
Bin	(7)(3)	0	1	119	1
Bin	(7)(3)	1	0	14579	1
Bin	(7)(2)	0	1	123	1
Bin	(7)(2)	1	0	14892	1
Bin	(7)(1)	0	1	122	1
Bin	(7)(1)	1	0	14582	1
Bin	(7)(0)	0	1	120	1
Bin	(7)(0)	1	0	14580	1
Bin	(6)(31)	0	1	121	1
Bin	(6)(31)	1	0	14363	1
Bin	(6)(30)	0	1	111	1
Bin	(6)(30)	1	0	13908	1
Bin	(6)(29)	0	1	123	1
Bin	(6)(29)	1	0	14433	1
Bin	(6)(28)	0	1	146	1
Bin	(6)(28)	1	0	13940	1
Bin	(6)(27)	0	1	127	1
Bin	(6)(27)	1	0	14437	1
Bin	(6)(26)	0	1	146	1
Bin	(6)(26)	1	0	14388	1
Bin	(6)(25)	0	1	127	1
Bin	(6)(25)	1	0	13921	1
Bin	(6)(24)	0	1	117	1
Bin	(6)(24)	1	0	13911	1
Bin	(6)(23)	0	1	129	1
Bin	(6)(23)	1	0	14371	1
Bin	(6)(22)	0	1	129	1
Bin	(6)(22)	1	0	14410	1
Bin	(6)(21)	0	1	136	1
Bin	(6)(21)	1	0	14417	1
Bin	(6)(20)	0	1	140	1
Bin	(6)(20)	1	0	14382	1
Bin	(6)(19)	0	1	130	1
Bin	(6)(19)	1	0	13924	1
Bin	(6)(18)	0	1	134	1
Bin	(6)(18)	1	0	13967	1
Bin	(6)(17)	0	1	127	1
Bin	(6)(17)	1	0	14369	1
Bin	(6)(16)	0	1	128	1
Bin	(6)(16)	1	0	14007	1
Bin	(6)(15)	0	1	124	1
Bin	(6)(15)	1	0	14405	1
Bin	(6)(14)	0	1	123	1
Bin	(6)(14)	1	0	13917	1
Bin	(6)(13)	0	1	130	1
Bin	(6)(13)	1	0	14372	1
Bin	(6)(12)	0	1	127	1
Bin	(6)(12)	1	0	14369	1
Bin	(6)(11)	0	1	119	1
Bin	(6)(11)	1	0	13913	1
Bin	(6)(10)	0	1	134	1
Bin	(6)(10)	1	0	13928	1
Bin	(6)(9)	0	1	133	1
Bin	(6)(9)	1	0	13966	1
Bin	(6)(8)	0	1	127	1
Bin	(6)(8)	1	0	13960	1
Bin	(6)(7)	0	1	135	1
Bin	(6)(7)	1	0	13957	1
Bin	(6)(6)	0	1	133	1
Bin	(6)(6)	1	0	14237	1
Bin	(6)(5)	0	1	131	1
Bin	(6)(5)	1	0	14401	1
Bin	(6)(4)	0	1	131	1
Bin	(6)(4)	1	0	13925	1
Bin	(6)(3)	0	1	138	1
Bin	(6)(3)	1	0	14408	1
Bin	(6)(2)	0	1	139	1
Bin	(6)(2)	1	0	14692	1
Bin	(6)(1)	0	1	128	1
Bin	(6)(1)	1	0	14244	1
Bin	(6)(0)	0	1	130	1
Bin	(6)(0)	1	0	13991	1
Bin	(5)(31)	0	1	113	1
Bin	(5)(31)	1	0	13587	1
Bin	(5)(30)	0	1	115	1
Bin	(5)(30)	1	0	13589	1
Bin	(5)(29)	0	1	120	1
Bin	(5)(29)	1	0	14500	1
Bin	(5)(28)	0	1	132	1
Bin	(5)(28)	1	0	14535	1
Bin	(5)(27)	0	1	128	1
Bin	(5)(27)	1	0	13608	1
Bin	(5)(26)	0	1	123	1
Bin	(5)(26)	1	0	13614	1
Bin	(5)(25)	0	1	141	1
Bin	(5)(25)	1	0	14544	1
Bin	(5)(24)	0	1	122	1
Bin	(5)(24)	1	0	13596	1
Bin	(5)(23)	0	1	131	1
Bin	(5)(23)	1	0	14528	1
Bin	(5)(22)	0	1	119	1
Bin	(5)(22)	1	0	13593	1
Bin	(5)(21)	0	1	132	1
Bin	(5)(21)	1	0	14565	1
Bin	(5)(20)	0	1	128	1
Bin	(5)(20)	1	0	14514	1
Bin	(5)(19)	0	1	126	1
Bin	(5)(19)	1	0	13617	1
Bin	(5)(18)	0	1	126	1
Bin	(5)(18)	1	0	13600	1
Bin	(5)(17)	0	1	120	1
Bin	(5)(17)	1	0	13611	1
Bin	(5)(16)	0	1	123	1
Bin	(5)(16)	1	0	13603	1
Bin	(5)(15)	0	1	119	1
Bin	(5)(15)	1	0	14516	1
Bin	(5)(14)	0	1	119	1
Bin	(5)(14)	1	0	13593	1
Bin	(5)(13)	0	1	125	1
Bin	(5)(13)	1	0	14522	1
Bin	(5)(12)	0	1	121	1
Bin	(5)(12)	1	0	13595	1
Bin	(5)(11)	0	1	125	1
Bin	(5)(11)	1	0	14522	1
Bin	(5)(10)	0	1	117	1
Bin	(5)(10)	1	0	14503	1
Bin	(5)(9)	0	1	126	1
Bin	(5)(9)	1	0	13960	1
Bin	(5)(8)	0	1	127	1
Bin	(5)(8)	1	0	14513	1
Bin	(5)(7)	0	1	127	1
Bin	(5)(7)	1	0	13963	1
Bin	(5)(6)	0	1	112	1
Bin	(5)(6)	1	0	13676	1
Bin	(5)(5)	0	1	124	1
Bin	(5)(5)	1	0	14527	1
Bin	(5)(4)	0	1	127	1
Bin	(5)(4)	1	0	14513	1
Bin	(5)(3)	0	1	122	1
Bin	(5)(3)	1	0	14763	1
Bin	(5)(2)	0	1	127	1
Bin	(5)(2)	1	0	13624	1
Bin	(5)(1)	0	1	121	1
Bin	(5)(1)	1	0	14501	1
Bin	(5)(0)	0	1	119	1
Bin	(5)(0)	1	0	13694	1
Bin	(4)(31)	0	1	109	1
Bin	(4)(31)	1	0	12902	1
Bin	(4)(30)	0	1	120	1
Bin	(4)(30)	1	0	12902	1
Bin	(4)(29)	0	1	123	1
Bin	(4)(29)	1	0	12905	1
Bin	(4)(28)	0	1	133	1
Bin	(4)(28)	1	0	12995	1
Bin	(4)(27)	0	1	140	1
Bin	(4)(27)	1	0	14344	1
Bin	(4)(26)	0	1	138	1
Bin	(4)(26)	1	0	12997	1
Bin	(4)(25)	0	1	139	1
Bin	(4)(25)	1	0	12940	1
Bin	(4)(24)	0	1	144	1
Bin	(4)(24)	1	0	14576	1
Bin	(4)(23)	0	1	137	1
Bin	(4)(23)	1	0	14427	1
Bin	(4)(22)	0	1	149	1
Bin	(4)(22)	1	0	14683	1
Bin	(4)(21)	0	1	144	1
Bin	(4)(21)	1	0	14495	1
Bin	(4)(20)	0	1	142	1
Bin	(4)(20)	1	0	13341	1
Bin	(4)(19)	0	1	149	1
Bin	(4)(19)	1	0	14759	1
Bin	(4)(18)	0	1	136	1
Bin	(4)(18)	1	0	14657	1
Bin	(4)(17)	0	1	138	1
Bin	(4)(17)	1	0	14534	1
Bin	(4)(16)	0	1	128	1
Bin	(4)(16)	1	0	13141	1
Bin	(4)(15)	0	1	122	1
Bin	(4)(15)	1	0	13154	1
Bin	(4)(14)	0	1	141	1
Bin	(4)(14)	1	0	13199	1
Bin	(4)(13)	0	1	128	1
Bin	(4)(13)	1	0	14539	1
Bin	(4)(12)	0	1	127	1
Bin	(4)(12)	1	0	14538	1
Bin	(4)(11)	0	1	137	1
Bin	(4)(11)	1	0	13338	1
Bin	(4)(10)	0	1	132	1
Bin	(4)(10)	1	0	13270	1
Bin	(4)(9)	0	1	143	1
Bin	(4)(9)	1	0	14694	1
Bin	(4)(8)	0	1	136	1
Bin	(4)(8)	1	0	13073	1
Bin	(4)(7)	0	1	136	1
Bin	(4)(7)	1	0	12945	1
Bin	(4)(6)	0	1	137	1
Bin	(4)(6)	1	0	14639	1
Bin	(4)(5)	0	1	133	1
Bin	(4)(5)	1	0	13165	1
Bin	(4)(4)	0	1	132	1
Bin	(4)(4)	1	0	13054	1
Bin	(4)(3)	0	1	134	1
Bin	(4)(3)	1	0	13272	1
Bin	(4)(2)	0	1	133	1
Bin	(4)(2)	1	0	13305	1
Bin	(4)(1)	0	1	140	1
Bin	(4)(1)	1	0	12954	1
Bin	(4)(0)	0	1	139	1
Bin	(4)(0)	1	0	14535	1
Bin	(3)(31)	0	1	470	1
Bin	(3)(31)	1	0	10362	1
Bin	(3)(30)	0	1	463	1
Bin	(3)(30)	1	0	12177	1
Bin	(3)(29)	0	1	468	1
Bin	(3)(29)	1	0	10360	1
Bin	(3)(28)	0	1	522	1
Bin	(3)(28)	1	0	10595	1
Bin	(3)(27)	0	1	484	1
Bin	(3)(27)	1	0	10397	1
Bin	(3)(26)	0	1	524	1
Bin	(3)(26)	1	0	10585	1
Bin	(3)(25)	0	1	504	1
Bin	(3)(25)	1	0	10440	1
Bin	(3)(24)	0	1	511	1
Bin	(3)(24)	1	0	10439	1
Bin	(3)(23)	0	1	506	1
Bin	(3)(23)	1	0	10614	1
Bin	(3)(22)	0	1	498	1
Bin	(3)(22)	1	0	10434	1
Bin	(3)(21)	0	1	507	1
Bin	(3)(21)	1	0	12470	1
Bin	(3)(20)	0	1	494	1
Bin	(3)(20)	1	0	12221	1
Bin	(3)(19)	0	1	521	1
Bin	(3)(19)	1	0	12465	1
Bin	(3)(18)	0	1	517	1
Bin	(3)(18)	1	0	10597	1
Bin	(3)(17)	0	1	491	1
Bin	(3)(17)	1	0	12420	1
Bin	(3)(16)	0	1	495	1
Bin	(3)(16)	1	0	10643	1
Bin	(3)(15)	0	1	504	1
Bin	(3)(15)	1	0	10736	1
Bin	(3)(14)	0	1	496	1
Bin	(3)(14)	1	0	10764	1
Bin	(3)(13)	0	1	495	1
Bin	(3)(13)	1	0	10763	1
Bin	(3)(12)	0	1	503	1
Bin	(3)(12)	1	0	10748	1
Bin	(3)(11)	0	1	492	1
Bin	(3)(11)	1	0	10523	1
Bin	(3)(10)	0	1	490	1
Bin	(3)(10)	1	0	12544	1
Bin	(3)(9)	0	1	496	1
Bin	(3)(9)	1	0	12844	1
Bin	(3)(8)	0	1	486	1
Bin	(3)(8)	1	0	10718	1
Bin	(3)(7)	0	1	519	1
Bin	(3)(7)	1	0	12544	1
Bin	(3)(6)	0	1	498	1
Bin	(3)(6)	1	0	11068	1
Bin	(3)(5)	0	1	514	1
Bin	(3)(5)	1	0	12502	1
Bin	(3)(4)	0	1	497	1
Bin	(3)(4)	1	0	12254	1
Bin	(3)(3)	0	1	492	1
Bin	(3)(3)	1	0	12582	1
Bin	(3)(2)	0	1	502	1
Bin	(3)(2)	1	0	10569	1
Bin	(3)(1)	0	1	510	1
Bin	(3)(1)	1	0	11047	1
Bin	(3)(0)	0	1	503	1
Bin	(3)(0)	1	0	12834	1
Bin	(2)(31)	0	1	482	1
Bin	(2)(31)	1	0	10859	1
Bin	(2)(30)	0	1	457	1
Bin	(2)(30)	1	0	9046	1
Bin	(2)(29)	0	1	492	1
Bin	(2)(29)	1	0	11621	1
Bin	(2)(28)	0	1	524	1
Bin	(2)(28)	1	0	11808	1
Bin	(2)(27)	0	1	557	1
Bin	(2)(27)	1	0	11826	1
Bin	(2)(26)	0	1	527	1
Bin	(2)(26)	1	0	10873	1
Bin	(2)(25)	0	1	557	1
Bin	(2)(25)	1	0	8485	1
Bin	(2)(24)	0	1	535	1
Bin	(2)(24)	1	0	9306	1
Bin	(2)(23)	0	1	556	1
Bin	(2)(23)	1	0	10642	1
Bin	(2)(22)	0	1	539	1
Bin	(2)(22)	1	0	11113	1
Bin	(2)(21)	0	1	563	1
Bin	(2)(21)	1	0	9239	1
Bin	(2)(20)	0	1	558	1
Bin	(2)(20)	1	0	12145	1
Bin	(2)(19)	0	1	546	1
Bin	(2)(19)	1	0	10816	1
Bin	(2)(18)	0	1	565	1
Bin	(2)(18)	1	0	11366	1
Bin	(2)(17)	0	1	503	1
Bin	(2)(17)	1	0	10935	1
Bin	(2)(16)	0	1	519	1
Bin	(2)(16)	1	0	10728	1
Bin	(2)(15)	0	1	525	1
Bin	(2)(15)	1	0	11587	1
Bin	(2)(14)	0	1	504	1
Bin	(2)(14)	1	0	11185	1
Bin	(2)(13)	0	1	517	1
Bin	(2)(13)	1	0	10483	1
Bin	(2)(12)	0	1	524	1
Bin	(2)(12)	1	0	11338	1
Bin	(2)(11)	0	1	529	1
Bin	(2)(11)	1	0	8547	1
Bin	(2)(10)	0	1	520	1
Bin	(2)(10)	1	0	9579	1
Bin	(2)(9)	0	1	525	1
Bin	(2)(9)	1	0	10850	1
Bin	(2)(8)	0	1	521	1
Bin	(2)(8)	1	0	11324	1
Bin	(2)(7)	0	1	543	1
Bin	(2)(7)	1	0	8941	1
Bin	(2)(6)	0	1	517	1
Bin	(2)(6)	1	0	9383	1
Bin	(2)(5)	0	1	536	1
Bin	(2)(5)	1	0	9672	1
Bin	(2)(4)	0	1	521	1
Bin	(2)(4)	1	0	10887	1
Bin	(2)(3)	0	1	506	1
Bin	(2)(3)	1	0	10895	1
Bin	(2)(2)	0	1	527	1
Bin	(2)(2)	1	0	9680	1
Bin	(2)(1)	0	1	517	1
Bin	(2)(1)	1	0	11350	1
Bin	(2)(0)	0	1	541	1
Bin	(2)(0)	1	0	11624	1
Bin	(1)(31)	0	1	587	1
Bin	(1)(31)	1	0	9835	1
Bin	(1)(30)	0	1	601	1
Bin	(1)(30)	1	0	10110	1
Bin	(1)(29)	0	1	591	1
Bin	(1)(29)	1	0	7947	1
Bin	(1)(28)	0	1	632	1
Bin	(1)(28)	1	0	7657	1
Bin	(1)(27)	0	1	638	1
Bin	(1)(27)	1	0	10431	1
Bin	(1)(26)	0	1	619	1
Bin	(1)(26)	1	0	9907	1
Bin	(1)(25)	0	1	627	1
Bin	(1)(25)	1	0	6398	1
Bin	(1)(24)	0	1	617	1
Bin	(1)(24)	1	0	7638	1
Bin	(1)(23)	0	1	644	1
Bin	(1)(23)	1	0	7395	1
Bin	(1)(22)	0	1	634	1
Bin	(1)(22)	1	0	7322	1
Bin	(1)(21)	0	1	649	1
Bin	(1)(21)	1	0	9201	1
Bin	(1)(20)	0	1	638	1
Bin	(1)(20)	1	0	7676	1
Bin	(1)(19)	0	1	643	1
Bin	(1)(19)	1	0	8561	1
Bin	(1)(18)	0	1	637	1
Bin	(1)(18)	1	0	6598	1
Bin	(1)(17)	0	1	622	1
Bin	(1)(17)	1	0	9885	1
Bin	(1)(16)	0	1	584	1
Bin	(1)(16)	1	0	7931	1
Bin	(1)(15)	0	1	617	1
Bin	(1)(15)	1	0	7642	1
Bin	(1)(14)	0	1	599	1
Bin	(1)(14)	1	0	6290	1
Bin	(1)(13)	0	1	604	1
Bin	(1)(13)	1	0	10282	1
Bin	(1)(12)	0	1	611	1
Bin	(1)(12)	1	0	7551	1
Bin	(1)(11)	0	1	608	1
Bin	(1)(11)	1	0	6226	1
Bin	(1)(10)	0	1	607	1
Bin	(1)(10)	1	0	7462	1
Bin	(1)(9)	0	1	628	1
Bin	(1)(9)	1	0	9228	1
Bin	(1)(8)	0	1	601	1
Bin	(1)(8)	1	0	7279	1
Bin	(1)(7)	0	1	631	1
Bin	(1)(7)	1	0	11477	1
Bin	(1)(6)	0	1	633	1
Bin	(1)(6)	1	0	7324	1
Bin	(1)(5)	0	1	613	1
Bin	(1)(5)	1	0	8481	1
Bin	(1)(4)	0	1	624	1
Bin	(1)(4)	1	0	9888	1
Bin	(1)(3)	0	1	624	1
Bin	(1)(3)	1	0	8233	1
Bin	(1)(2)	0	1	628	1
Bin	(1)(2)	1	0	7615	1
Bin	(1)(1)	0	1	621	1
Bin	(1)(1)	1	0	8054	1
Bin	(1)(0)	0	1	618	1
Bin	(1)(0)	1	0	8633	1
Bin	(0)(31)	0	1	586	1
Bin	(0)(31)	1	0	5549	1
Bin	(0)(30)	0	1	587	1
Bin	(0)(30)	1	0	10586	1
Bin	(0)(29)	0	1	583	1
Bin	(0)(29)	1	0	6506	1
Bin	(0)(28)	0	1	671	1
Bin	(0)(28)	1	0	4483	1
Bin	(0)(27)	0	1	643	1
Bin	(0)(27)	1	0	6098	1
Bin	(0)(26)	0	1	642	1
Bin	(0)(26)	1	0	7320	1
Bin	(0)(25)	0	1	656	1
Bin	(0)(25)	1	0	4674	1
Bin	(0)(24)	0	1	650	1
Bin	(0)(24)	1	0	8903	1
Bin	(0)(23)	0	1	676	1
Bin	(0)(23)	1	0	4472	1
Bin	(0)(22)	0	1	660	1
Bin	(0)(22)	1	0	3748	1
Bin	(0)(21)	0	1	662	1
Bin	(0)(21)	1	0	8926	1
Bin	(0)(20)	0	1	654	1
Bin	(0)(20)	1	0	6035	1
Bin	(0)(19)	0	1	645	1
Bin	(0)(19)	1	0	7435	1
Bin	(0)(18)	0	1	666	1
Bin	(0)(18)	1	0	9201	1
Bin	(0)(17)	0	1	648	1
Bin	(0)(17)	1	0	9079	1
Bin	(0)(16)	0	1	610	1
Bin	(0)(16)	1	0	5742	1
Bin	(0)(15)	0	1	631	1
Bin	(0)(15)	1	0	6085	1
Bin	(0)(14)	0	1	626	1
Bin	(0)(14)	1	0	7613	1
Bin	(0)(13)	0	1	605	1
Bin	(0)(13)	1	0	7443	1
Bin	(0)(12)	0	1	629	1
Bin	(0)(12)	1	0	8429	1
Bin	(0)(11)	0	1	609	1
Bin	(0)(11)	1	0	2475	1
Bin	(0)(10)	0	1	618	1
Bin	(0)(10)	1	0	3783	1
Bin	(0)(9)	0	1	629	1
Bin	(0)(9)	1	0	8099	1
Bin	(0)(8)	0	1	616	1
Bin	(0)(8)	1	0	5784	1
Bin	(0)(7)	0	1	647	1
Bin	(0)(7)	1	0	4514	1
Bin	(0)(6)	0	1	644	1
Bin	(0)(6)	1	0	10153	1
Bin	(0)(5)	0	1	637	1
Bin	(0)(5)	1	0	7853	1
Bin	(0)(4)	0	1	616	1
Bin	(0)(4)	1	0	3741	1
Bin	(0)(3)	0	1	642	1
Bin	(0)(3)	1	0	8904	1
Bin	(0)(2)	0	1	634	1
Bin	(0)(2)	1	0	8959	1
Bin	(0)(1)	0	1	650	1
Bin	(0)(1)	1	0	8603	1
Bin	(0)(0)	0	1	621	1
Bin	(0)(0)	1	0	7553	1

Signal:

CONTROL_REGISTERS_CS

	From	To	Count	Threshold
Bin	0	1	19663072	1
Bin	1	0	19664673	1

Signal:

CONTROL_REGISTERS_CS_REG

	From	To	Count	Threshold
Bin	0	1	10352322	1
Bin	1	0	10353923	1

Signal:

TEST_REGISTERS_CS

	From	To	Count	Threshold
Bin	0	1	313081	1
Bin	1	0	314682	1

Signal:

TEST_REGISTERS_CS_REG

	From	To	Count	Threshold
Bin	0	1	96135	1
Bin	1	0	97736	1

Signal:

CONTROL_REGISTERS_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	4947	1
Bin	(31)	1	0	6548	1
Bin	(30)	0	1	6039	1
Bin	(30)	1	0	7640	1
Bin	(29)	0	1	5842	1
Bin	(29)	1	0	7443	1
Bin	(28)	0	1	11453	1
Bin	(28)	1	0	13054	1
Bin	(27)	0	1	13493	1
Bin	(27)	1	0	15094	1
Bin	(26)	0	1	11357	1
Bin	(26)	1	0	12958	1
Bin	(25)	0	1	17809	1
Bin	(25)	1	0	19410	1
Bin	(24)	0	1	16800	1
Bin	(24)	1	0	18401	1
Bin	(23)	0	1	19873	1
Bin	(23)	1	0	21474	1
Bin	(22)	0	1	28337	1
Bin	(22)	1	0	29937	1
Bin	(21)	0	1	17044	1
Bin	(21)	1	0	18645	1
Bin	(20)	0	1	21998	1
Bin	(20)	1	0	23599	1
Bin	(19)	0	1	22597	1
Bin	(19)	1	0	24198	1
Bin	(18)	0	1	74954	1
Bin	(18)	1	0	76555	1
Bin	(17)	0	1	63221	1
Bin	(17)	1	0	64822	1
Bin	(16)	0	1	63571	1
Bin	(16)	1	0	65162	1
Bin	(15)	0	1	30505	1
Bin	(15)	1	0	32096	1
Bin	(14)	0	1	22315	1
Bin	(14)	1	0	23916	1
Bin	(13)	0	1	24640	1
Bin	(13)	1	0	26241	1
Bin	(12)	0	1	31814	1
Bin	(12)	1	0	33415	1
Bin	(11)	0	1	32927	1
Bin	(11)	1	0	34528	1
Bin	(10)	0	1	33440	1
Bin	(10)	1	0	35041	1
Bin	(9)	0	1	34469	1
Bin	(9)	1	0	36068	1
Bin	(8)	0	1	32823	1
Bin	(8)	1	0	34423	1
Bin	(7)	0	1	58228	1
Bin	(7)	1	0	59829	1
Bin	(6)	0	1	55433	1
Bin	(6)	1	0	57024	1
Bin	(5)	0	1	67719	1
Bin	(5)	1	0	69310	1
Bin	(4)	0	1	67162	1
Bin	(4)	1	0	68761	1
Bin	(3)	0	1	77075	1
Bin	(3)	1	0	78676	1
Bin	(2)	0	1	61410	1
Bin	(2)	1	0	63011	1
Bin	(1)	0	1	43651	1
Bin	(1)	1	0	45252	1
Bin	(0)	0	1	49506	1
Bin	(0)	1	0	51107	1

Signal:

TEST_REGISTERS_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1297	1
Bin	(31)	1	0	2898	1
Bin	(30)	0	1	1321	1
Bin	(30)	1	0	2922	1
Bin	(29)	0	1	1403	1
Bin	(29)	1	0	3004	1
Bin	(28)	0	1	1455	1
Bin	(28)	1	0	3056	1
Bin	(27)	0	1	1464	1
Bin	(27)	1	0	3065	1
Bin	(26)	0	1	1468	1
Bin	(26)	1	0	3069	1
Bin	(25)	0	1	1509	1
Bin	(25)	1	0	3110	1
Bin	(24)	0	1	1375	1
Bin	(24)	1	0	2976	1
Bin	(23)	0	1	1343	1
Bin	(23)	1	0	2944	1
Bin	(22)	0	1	1380	1
Bin	(22)	1	0	2981	1
Bin	(21)	0	1	1458	1
Bin	(21)	1	0	3059	1
Bin	(20)	0	1	1479	1
Bin	(20)	1	0	3080	1
Bin	(19)	0	1	1469	1
Bin	(19)	1	0	3070	1
Bin	(18)	0	1	1470	1
Bin	(18)	1	0	3071	1
Bin	(17)	0	1	1494	1
Bin	(17)	1	0	3095	1
Bin	(16)	0	1	1385	1
Bin	(16)	1	0	2986	1
Bin	(15)	0	1	1342	1
Bin	(15)	1	0	2943	1
Bin	(14)	0	1	1366	1
Bin	(14)	1	0	2967	1
Bin	(13)	0	1	1460	1
Bin	(13)	1	0	3061	1
Bin	(12)	0	1	1505	1
Bin	(12)	1	0	3106	1
Bin	(11)	0	1	1470	1
Bin	(11)	1	0	3071	1
Bin	(10)	0	1	1456	1
Bin	(10)	1	0	3057	1
Bin	(9)	0	1	1540	1
Bin	(9)	1	0	3141	1
Bin	(8)	0	1	1385	1
Bin	(8)	1	0	2986	1
Bin	(7)	0	1	1398	1
Bin	(7)	1	0	2999	1
Bin	(6)	0	1	1410	1
Bin	(6)	1	0	3011	1
Bin	(5)	0	1	1495	1
Bin	(5)	1	0	3096	1
Bin	(4)	0	1	1480	1
Bin	(4)	1	0	3081	1
Bin	(3)	0	1	1476	1
Bin	(3)	1	0	3077	1
Bin	(2)	0	1	1507	1
Bin	(2)	1	0	3108	1
Bin	(1)	0	1	1549	1
Bin	(1)	1	0	3150	1
Bin	(0)	0	1	1433	1
Bin	(0)	1	0	3034	1

Signal:

REG_LOCK_1_ACTIVE

	From	To	Count	Threshold
Bin	0	1	2627	1
Bin	1	0	1027	1

Signal:

REG_LOCK_2_ACTIVE

	From	To	Count	Threshold
Bin	0	1	6483	1
Bin	1	0	8072	1

Signal:

SOFT_RES_D_N

	From	To	Count	Threshold
Bin	0	1	32877	1
Bin	1	0	868	1

Signal:

SOFT_RES_Q_N

	From	To	Count	Threshold
Bin	0	1	9645	1
Bin	1	0	8044	1

Signal:

RES_CORE_D_N

	From	To	Count	Threshold
Bin	0	1	8084	1
Bin	1	0	8072	1

Signal:

CONTROL_REGS_CLK_EN

	From	To	Count	Threshold
Bin	0	1	19663072	1
Bin	1	0	19664673	1

Signal:

TEST_REGS_CLK_EN

	From	To	Count	Threshold
Bin	0	1	313081	1
Bin	1	0	314682	1

Signal:

CLK_CONTROL_REGS

	From	To	Count	Threshold
Bin	0	1	30962985	1
Bin	1	0	30964586	1

Signal:

CLK_TEST_REGS

	From	To	Count	Threshold
Bin	0	1	13404187	1
Bin	1	0	13405788	1

Signal:

SCS_AND_SWR

	From	To	Count	Threshold
Bin	0	1	802432	1
Bin	1	0	804033	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

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Signal assignment statement on line 592:

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Signal assignment statement on line 682:

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Loop statement on lines 693 to 697:

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If statement on lines 727 to 729: