NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_CLK_GATE_TXTB_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
I_TXTB_RAM	100.0 % (52/52)	100.0 % (38/38)	100.0 % (2160/2160)	93.1 % (54/58)	N.A.	N.A.	99.8 % (2304/2308)
I_TXTB_FSM	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_CLK_GATE_TXTB_RAM_COMP

100.0 % (5/5)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (25/25)

I_TXTB_RAM

100.0 % (52/52)

100.0 % (38/38)

100.0 % (2160/2160)

93.1 % (54/58)

N.A.

99.8 % (2304/2308)

I_TXTB_FSM

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(3).G_TXT_BUF_ODD.I_TXTB_ODD_TOP	100.0 % (38/38)	100.0 % (24/24)	100.0 % (468/468)	100.0 % (75/75)	N.A.	N.A.	100.0 % (605/605)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(3).G_TXT_BUF_ODD.I_TXTB_ODD_TOP

100.0 % (38/38)

100.0 % (24/24)

100.0 % (468/468)

100.0 % (75/75)

N.A.

100.0 % (605/605)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

253:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
254:                             else 
255:                         '0';

Count: 93812
Threshold: 1

Signal assignment statement on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 45107
Threshold: 1

Signal assignment statement on line 255:

255: '0';
Count: 48705
Threshold: 1

If statement on lines 266 to 268:

266:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
267:                                                   else 
268:                                    (others => '0');

Count: 18380
Threshold: 1

Signal assignment statement on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 6404
Threshold: 1

Signal assignment statement on line 268:

268: (others => '0');
Count: 11976
Threshold: 1

If statement on lines 276 to 280:

276:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
277:                           else 
278:                       '1' when (mr_tst_control_tmaena = '1') 
279:                           else 
280:                       '0';

Count: 153738
Threshold: 1

Signal assignment statement on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 74913
Threshold: 1

Signal assignment statement on line 278:

278: '1' when (mr_tst_control_tmaena = '1')
Count: 636
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 78189
Threshold: 1

If statement on lines 287 to 291:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID) 
290:                                     else 
291:                                 '0';

Count: 150316
Threshold: 1

Signal assignment statement on line 287:

287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 300
Threshold: 1

Signal assignment statement on line 291:

291: '0';
Count: 150016
Threshold: 1

Signal assignment statement on line 293:

293: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 1920
Threshold: 1

If statement on lines 301 to 309:

301:        if (rst_n = '0') then 
302:            mr_tx_command_txce_q <= '0'; 
...
308:            mr_tx_command_txca_q <= mr_tx_command_txca; 
309:        end if;

Count: 165249974
Threshold: 1

Signal assignment statement on line 302:

302: mr_tx_command_txce_q <= '0';
Count: 1737636
Threshold: 1

Signal assignment statement on line 303:

303: mr_tx_command_txcr_q <= '0';
Count: 1737636
Threshold: 1

Signal assignment statement on line 304:

304: mr_tx_command_txca_q <= '0';
Count: 1737636
Threshold: 1

Signal assignment statement on line 306:

306: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 81754417
Threshold: 1

Signal assignment statement on line 307:

307: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 81754417
Threshold: 1

Signal assignment statement on line 308:

308: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 81754417
Threshold: 1

If statement on lines 312 to 314:

312:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
313:                                 else 
314:                             '0';

Count: 3428
Threshold: 1

Signal assignment statement on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 93
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 3335
Threshold: 1

If statement on lines 315 to 317:

315:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
316:                                 else 
317:                             '0';

Count: 22448
Threshold: 1

Signal assignment statement on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 1017
Threshold: 1

Signal assignment statement on line 317:

317: '0';
Count: 21431
Threshold: 1

If statement on lines 319 to 321:

319:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
320:                         else 
321:                     '0';

Count: 5740
Threshold: 1

Signal assignment statement on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 181
Threshold: 1

Signal assignment statement on line 321:

321: '0';
Count: 5559
Threshold: 1

If statement on lines 323 to 326:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1')) 
325:                        else 
326:                    '0';

Count: 20364
Threshold: 1

Signal assignment statement on line 323:

323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
Count: 20
Threshold: 1

Signal assignment statement on line 326:

326: '0';
Count: 20344
Threshold: 1

Signal assignment statement on line 328:

328: abort_or_skipped <= abort_applied or buffer_skipped;
Count: 1722
Threshold: 1

If statement on lines 333 to 335:

333:    txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') 
334:                                else 
335:                            '0';

Count: 2636
Threshold: 1

Signal assignment statement on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
Count: 125
Threshold: 1

Signal assignment statement on line 335:

335: '0';
Count: 2511
Threshold: 1

Signal assignment statement on line 423:

423: txtb_parity_mismatch <= parity_mismatch;
Count: 3900
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	45107	1
Bin	False	48705	1

"if" / "when" / "else" condition on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	6404	1
Bin	False	11976	1

"if" / "when" / "else" condition on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	74913	1
Bin	False	78825	1

"if" / "when" / "else" condition on line 278:

278: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	636	1
Bin	False	78189	1

"if" / "when" / "else" condition on lines 287 to 289:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	300	1
Bin	False	150016	1

"if" / "when" / "else" condition on line 301:

301: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	1737636	1
Bin	False	163512338	1

"if" / "when" / "else" condition on line 305:

305: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	81754417	1
Bin	False	81757921	1

"if" / "when" / "else" condition on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	93	1
Bin	False	3335	1

"if" / "when" / "else" condition on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	1017	1
Bin	False	21431	1

"if" / "when" / "else" condition on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	181	1
Bin	False	5559	1

"if" / "when" / "else" condition on lines 323 to 324:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1'))

	Evaluated to	Count	Threshold
Bin	True	20	1
Bin	False	20344	1

"if" / "when" / "else" condition on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')

	Evaluated to	Count	Threshold
Bin	True	125	1
Bin	False	2511	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_IS_BB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	470	1
Bin	(31)	1	0	1130	1
Bin	(30)	0	1	463	1
Bin	(30)	1	0	1123	1
Bin	(29)	0	1	468	1
Bin	(29)	1	0	1128	1
Bin	(28)	0	1	522	1
Bin	(28)	1	0	1182	1
Bin	(27)	0	1	484	1
Bin	(27)	1	0	1144	1
Bin	(26)	0	1	524	1
Bin	(26)	1	0	1184	1
Bin	(25)	0	1	504	1
Bin	(25)	1	0	1164	1
Bin	(24)	0	1	511	1
Bin	(24)	1	0	1171	1
Bin	(23)	0	1	506	1
Bin	(23)	1	0	1166	1
Bin	(22)	0	1	498	1
Bin	(22)	1	0	1158	1
Bin	(21)	0	1	507	1
Bin	(21)	1	0	1167	1
Bin	(20)	0	1	494	1
Bin	(20)	1	0	1154	1
Bin	(19)	0	1	521	1
Bin	(19)	1	0	1181	1
Bin	(18)	0	1	517	1
Bin	(18)	1	0	1177	1
Bin	(17)	0	1	491	1
Bin	(17)	1	0	1151	1
Bin	(16)	0	1	495	1
Bin	(16)	1	0	1155	1
Bin	(15)	0	1	504	1
Bin	(15)	1	0	1164	1
Bin	(14)	0	1	496	1
Bin	(14)	1	0	1156	1
Bin	(13)	0	1	495	1
Bin	(13)	1	0	1155	1
Bin	(12)	0	1	503	1
Bin	(12)	1	0	1163	1
Bin	(11)	0	1	492	1
Bin	(11)	1	0	1152	1
Bin	(10)	0	1	490	1
Bin	(10)	1	0	1150	1
Bin	(9)	0	1	496	1
Bin	(9)	1	0	1156	1
Bin	(8)	0	1	486	1
Bin	(8)	1	0	1146	1
Bin	(7)	0	1	519	1
Bin	(7)	1	0	1179	1
Bin	(6)	0	1	498	1
Bin	(6)	1	0	1158	1
Bin	(5)	0	1	514	1
Bin	(5)	1	0	1174	1
Bin	(4)	0	1	497	1
Bin	(4)	1	0	1157	1
Bin	(3)	0	1	492	1
Bin	(3)	1	0	1152	1
Bin	(2)	0	1	502	1
Bin	(2)	1	0	1162	1
Bin	(1)	0	1	510	1
Bin	(1)	1	0	1170	1
Bin	(0)	0	1	503	1
Bin	(0)	1	0	1163	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1122	1
Bin	(3)	1	0	462	1
Bin	(2)	0	1	858	1
Bin	(2)	1	0	1518	1
Bin	(1)	0	1	1035	1
Bin	(1)	1	0	1695	1
Bin	(0)	0	1	963	1
Bin	(0)	1	0	1623	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	731	1
Bin	1	0	1391	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	10332	1
Bin	LOCK	1	0	10992	1
Bin	VALID	0	1	3834	1
Bin	VALID	1	0	4494	1
Bin	ERR	0	1	1123	1
Bin	ERR	1	0	1783	1
Bin	ARBL	0	1	44	1
Bin	ARBL	1	0	704	1
Bin	FAILED	0	1	5322	1
Bin	FAILED	1	0	5982	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	359	1
Bin	(31)	1	0	1019	1
Bin	(30)	0	1	314	1
Bin	(30)	1	0	974	1
Bin	(29)	0	1	285	1
Bin	(29)	1	0	945	1
Bin	(28)	0	1	1041	1
Bin	(28)	1	0	1701	1
Bin	(27)	0	1	981	1
Bin	(27)	1	0	1641	1
Bin	(26)	0	1	1157	1
Bin	(26)	1	0	1817	1
Bin	(25)	0	1	1127	1
Bin	(25)	1	0	1787	1
Bin	(24)	0	1	1173	1
Bin	(24)	1	0	1833	1
Bin	(23)	0	1	1073	1
Bin	(23)	1	0	1733	1
Bin	(22)	0	1	1243	1
Bin	(22)	1	0	1903	1
Bin	(21)	0	1	1184	1
Bin	(21)	1	0	1844	1
Bin	(20)	0	1	1051	1
Bin	(20)	1	0	1711	1
Bin	(19)	0	1	1237	1
Bin	(19)	1	0	1897	1
Bin	(18)	0	1	1289	1
Bin	(18)	1	0	1949	1
Bin	(17)	0	1	721	1
Bin	(17)	1	0	1381	1
Bin	(16)	0	1	684	1
Bin	(16)	1	0	1344	1
Bin	(15)	0	1	852	1
Bin	(15)	1	0	1512	1
Bin	(14)	0	1	748	1
Bin	(14)	1	0	1408	1
Bin	(13)	0	1	763	1
Bin	(13)	1	0	1423	1
Bin	(12)	0	1	734	1
Bin	(12)	1	0	1394	1
Bin	(11)	0	1	887	1
Bin	(11)	1	0	1547	1
Bin	(10)	0	1	802	1
Bin	(10)	1	0	1462	1
Bin	(9)	0	1	1232	1
Bin	(9)	1	0	1892	1
Bin	(8)	0	1	727	1
Bin	(8)	1	0	1387	1
Bin	(7)	0	1	1562	1
Bin	(7)	1	0	2222	1
Bin	(6)	0	1	1214	1
Bin	(6)	1	0	1874	1
Bin	(5)	0	1	1140	1
Bin	(5)	1	0	1800	1
Bin	(4)	0	1	815	1
Bin	(4)	1	0	1475	1
Bin	(3)	0	1	1286	1
Bin	(3)	1	0	1946	1
Bin	(2)	0	1	1091	1
Bin	(2)	1	0	1751	1
Bin	(1)	0	1	1149	1
Bin	(1)	1	0	1809	1
Bin	(0)	0	1	1474	1
Bin	(0)	1	0	2134	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	1055	1
Bin	1	0	1715	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	899	1
Bin	1	0	1559	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1290	1
Bin	1	0	1950	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	300	1
Bin	1	0	960	1

Port:

TXTB_BB_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	785	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	1559	1
Bin	1	0	899	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	899	1
Bin	1	0	1559	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1072	1
Bin	(31)	1	0	1692	1
Bin	(30)	0	1	1058	1
Bin	(30)	1	0	1678	1
Bin	(29)	0	1	1077	1
Bin	(29)	1	0	1697	1
Bin	(28)	0	1	2372	1
Bin	(28)	1	0	2982	1
Bin	(27)	0	1	2186	1
Bin	(27)	1	0	2795	1
Bin	(26)	0	1	2422	1
Bin	(26)	1	0	3033	1
Bin	(25)	0	1	2336	1
Bin	(25)	1	0	2946	1
Bin	(24)	0	1	2230	1
Bin	(24)	1	0	2834	1
Bin	(23)	0	1	2554	1
Bin	(23)	1	0	3165	1
Bin	(22)	0	1	2351	1
Bin	(22)	1	0	2955	1
Bin	(21)	0	1	2638	1
Bin	(21)	1	0	3241	1
Bin	(20)	0	1	2094	1
Bin	(20)	1	0	2697	1
Bin	(19)	0	1	2536	1
Bin	(19)	1	0	3136	1
Bin	(18)	0	1	2733	1
Bin	(18)	1	0	3337	1
Bin	(17)	0	1	1853	1
Bin	(17)	1	0	2466	1
Bin	(16)	0	1	1639	1
Bin	(16)	1	0	2252	1
Bin	(15)	0	1	1932	1
Bin	(15)	1	0	2542	1
Bin	(14)	0	1	2041	1
Bin	(14)	1	0	2651	1
Bin	(13)	0	1	2017	1
Bin	(13)	1	0	2631	1
Bin	(12)	0	1	1894	1
Bin	(12)	1	0	2505	1
Bin	(11)	0	1	2157	1
Bin	(11)	1	0	2768	1
Bin	(10)	0	1	2057	1
Bin	(10)	1	0	2668	1
Bin	(9)	0	1	3108	1
Bin	(9)	1	0	3706	1
Bin	(8)	0	1	2117	1
Bin	(8)	1	0	2734	1
Bin	(7)	0	1	3436	1
Bin	(7)	1	0	4013	1
Bin	(6)	0	1	2743	1
Bin	(6)	1	0	3331	1
Bin	(5)	0	1	2843	1
Bin	(5)	1	0	3449	1
Bin	(4)	0	1	1814	1
Bin	(4)	1	0	2424	1
Bin	(3)	0	1	2911	1
Bin	(3)	1	0	3509	1
Bin	(2)	0	1	2685	1
Bin	(2)	1	0	3280	1
Bin	(1)	0	1	2812	1
Bin	(1)	1	0	3400	1
Bin	(0)	0	1	3267	1
Bin	(0)	1	0	3863	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	300	1
Bin	1	0	960	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	1000	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	9850	1
Bin	1	0	10510	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	1496	1
Bin	1	0	2156	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	753	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	1017	1
Bin	1	0	1677	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	841	1

Signal:

BUFFER_SKIPPED

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	680	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	861	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	45107	1
Bin	1	0	45767	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	75549	1
Bin	1	0	76209	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	13808872	1
Bin	1	0	13809532	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1290	1
Bin	1	0	1950	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 253:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	46666	1
Bin	True	False	240	1
Bin	True	True	45107	1

"=" expression on line 253:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	48465	1
Bin	True	45347	1

"=" expression on line 253:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	2039	1
Bin	True	91773	1

"=" expression on line 266:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	11976	1
Bin	True	6404	1

"or" expression on line 276:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	78825	1
Bin	False	True	45107	1
Bin	True	False	29806	1

"=" expression on line 276:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	123932	1
Bin	True	29806	1

"=" expression on line 276:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	108631	1
Bin	True	45107	1

"=" expression on line 278:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	78189	1
Bin	True	636	1

"and" expression on lines 287 to 289:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	22121	1
Bin	True	False	1956	1
Bin	True	True	300	1

"and" expression on lines 287 to 288:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	61317	1
Bin	True	False	2773	1
Bin	True	True	2256	1

"=" expression on line 287:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	145287	1
Bin	True	5029	1

"=" expression on line 288:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	86743	1
Bin	True	63573	1

"=" expression on line 289:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	127895	1
Bin	True	22421	1

"=" expression on line 301:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	163512338	1
Bin	True	1737636	1

"and" expression on line 312:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	464	1
Bin	True	False	260	1
Bin	True	True	93	1

"=" expression on line 312:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	3075	1
Bin	True	353	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	2871	1
Bin	True	557	1

"and" expression on line 315:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	902	1
Bin	True	False	9332	1
Bin	True	True	1017	1

"=" expression on line 315:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	12099	1
Bin	True	10349	1

"=" expression on line 315:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	20529	1
Bin	True	1919	1

"and" expression on line 319:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	565	1
Bin	True	False	1315	1
Bin	True	True	181	1

"=" expression on line 319:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	4244	1
Bin	True	1496	1

"=" expression on line 319:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	4994	1
Bin	True	746	1

"and" expression on lines 323 to 324:

 (txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and (txtb_is_bb = '1') 
  <-----------------------LHS----------------------->       <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	56	1
Bin	True	False	9136	1
Bin	True	True	20	1

"or" expression on line 323:

 txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	11208	1
Bin	False	True	3834	1
Bin	True	False	5322	1

"=" expression on line 323:

txtb_hw_cmd.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	15042	1
Bin	True	5322	1

"=" expression on line 323:

txtb_hw_cmd.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	16530	1
Bin	True	3834	1

"=" expression on line 324:

txtb_is_bb = '1'

	Evaluated to	Count	Threshold
Bin	False	20288	1
Bin	True	76	1

"or" expression on line 328:

 abort_applied or buffer_skipped 
 <----LHS---->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	861	1
Bin	'0'	'1'	20	1
Bin	'1'	'0'	181	1

"and" expression on line 333:

 txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1' 
 <-------------LHS------------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	153	1
Bin	True	False	175	1
Bin	True	True	125	1

"=" expression on line 333:

txtb_parity_error_valid_i = '1'

	Evaluated to	Count	Threshold
Bin	False	2336	1
Bin	True	300	1

"=" expression on line 333:

mr_mode_txbbm = '1'

	Evaluated to	Count	Threshold
Bin	False	2358	1
Bin	True	278	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(3).G_TXT_BUF_ODD.I_TXTB_ODD_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

Signal assignment statement on line 253:

Signal assignment statement on line 255:

If statement on lines 266 to 268:

Signal assignment statement on line 266:

Signal assignment statement on line 268:

If statement on lines 276 to 280:

Signal assignment statement on line 276:

Signal assignment statement on line 278:

Signal assignment statement on line 280:

If statement on lines 287 to 291:

Signal assignment statement on line 287:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 301 to 309:

Signal assignment statement on line 302:

Signal assignment statement on line 303:

Signal assignment statement on line 304:

Signal assignment statement on line 306:

Signal assignment statement on line 307:

Signal assignment statement on line 308:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

If statement on lines 315 to 317:

Signal assignment statement on line 315:

Signal assignment statement on line 317:

If statement on lines 319 to 321:

Signal assignment statement on line 319:

Signal assignment statement on line 321:

If statement on lines 323 to 326:

Signal assignment statement on line 323:

Signal assignment statement on line 326:

Signal assignment statement on line 328:

If statement on lines 333 to 335:

Signal assignment statement on line 333:

Signal assignment statement on line 335:

Signal assignment statement on line 423:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

"if" / "when" / "else" condition on line 266:

"if" / "when" / "else" condition on line 276:

"if" / "when" / "else" condition on line 278:

"if" / "when" / "else" condition on lines 287 to 289:

"if" / "when" / "else" condition on line 301:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 312:

"if" / "when" / "else" condition on line 315:

"if" / "when" / "else" condition on line 319:

"if" / "when" / "else" condition on lines 323 to 324:

"if" / "when" / "else" condition on line 333:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: