NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_CLK_GATE_TXTB_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
I_TXTB_RAM	100.0 % (56/56)	100.0 % (38/38)	100.0 % (2160/2160)	94.8 % (55/58)	N.A.	N.A.	99.8 % (2309/2312)
I_TXTB_FSM	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_CLK_GATE_TXTB_RAM_COMP

100.0 % (5/5)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (25/25)

I_TXTB_RAM

100.0 % (56/56)

100.0 % (38/38)

100.0 % (2160/2160)

94.8 % (55/58)

N.A.

99.8 % (2309/2312)

I_TXTB_FSM

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(0).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP	100.0 % (32/32)	100.0 % (20/20)	100.0 % (462/462)	100.0 % (53/53)	N.A.	N.A.	100.0 % (567/567)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(0).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP

100.0 % (32/32)

100.0 % (20/20)

100.0 % (462/462)

100.0 % (53/53)

N.A.

100.0 % (567/567)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

246:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
247:                             else 
248:                         '0';

Count: 357440
Threshold: 1

Signal assignment statement on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 163731
Threshold: 1

Signal assignment statement on line 248:

248: '0';
Count: 193709
Threshold: 1

If statement on lines 259 to 261:

259:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
260:                                                   else 
261:                                    (others => '0');

Count: 167772
Threshold: 1

Signal assignment statement on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 80838
Threshold: 1

Signal assignment statement on line 261:

261: (others => '0');
Count: 86934
Threshold: 1

If statement on lines 269 to 273:

269:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
270:                           else 
271:                       '1' when (mr_tst_control_tmaena = '1') 
272:                           else 
273:                       '0';

Count: 550070
Threshold: 1

Signal assignment statement on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 271185
Threshold: 1

Signal assignment statement on line 271:

271: '1' when (mr_tst_control_tmaena = '1')
Count: 648
Threshold: 1

Signal assignment statement on line 273:

273: '0';
Count: 278237
Threshold: 1

If statement on lines 280 to 284:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID) 
283:                                     else 
284:                                 '0';

Count: 418264
Threshold: 1

Signal assignment statement on line 280:

280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 390
Threshold: 1

Signal assignment statement on line 284:

284: '0';
Count: 417874
Threshold: 1

Signal assignment statement on line 286:

286: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 3982
Threshold: 1

If statement on lines 294 to 302:

294:        if (rst_n = '0') then 
295:            mr_tx_command_txce_q <= '0'; 
...
301:            mr_tx_command_txca_q <= mr_tx_command_txca; 
302:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 295:

295: mr_tx_command_txce_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 296:

296: mr_tx_command_txcr_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 297:

297: mr_tx_command_txca_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 299:

299: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 547174334
Threshold: 1

Signal assignment statement on line 300:

300: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 547174334
Threshold: 1

Signal assignment statement on line 301:

301: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 547174334
Threshold: 1

If statement on lines 305 to 307:

305:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
306:                                 else 
307:                             '0';

Count: 18615
Threshold: 1

Signal assignment statement on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 105
Threshold: 1

Signal assignment statement on line 307:

307: '0';
Count: 18510
Threshold: 1

If statement on lines 308 to 310:

308:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
309:                                 else 
310:                             '0';

Count: 60991
Threshold: 1

Signal assignment statement on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 18585
Threshold: 1

Signal assignment statement on line 310:

310: '0';
Count: 42406
Threshold: 1

If statement on lines 312 to 314:

312:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
313:                         else 
314:                     '0';

Count: 21375
Threshold: 1

Signal assignment statement on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 984
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 20391
Threshold: 1

Signal assignment statement on line 317:

317: abort_or_skipped <= abort_applied;
Count: 5170
Threshold: 1

Signal assignment statement on line 405:

405: txtb_parity_mismatch <= parity_mismatch;
Count: 6854
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	163731	1
Bin	False	193709	1

"if" / "when" / "else" condition on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	80838	1
Bin	False	86934	1

"if" / "when" / "else" condition on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	271185	1
Bin	False	278885	1

"if" / "when" / "else" condition on line 271:

271: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	648	1
Bin	False	278237	1

"if" / "when" / "else" condition on lines 280 to 282:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	390	1
Bin	False	417874	1

"if" / "when" / "else" condition on line 294:

294: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 298:

298: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	105	1
Bin	False	18510	1

"if" / "when" / "else" condition on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	18585	1
Bin	False	42406	1

"if" / "when" / "else" condition on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	984	1
Bin	False	20391	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	586	1
Bin	(31)	1	0	2187	1
Bin	(30)	0	1	587	1
Bin	(30)	1	0	2188	1
Bin	(29)	0	1	583	1
Bin	(29)	1	0	2184	1
Bin	(28)	0	1	671	1
Bin	(28)	1	0	2272	1
Bin	(27)	0	1	643	1
Bin	(27)	1	0	2244	1
Bin	(26)	0	1	642	1
Bin	(26)	1	0	2243	1
Bin	(25)	0	1	656	1
Bin	(25)	1	0	2257	1
Bin	(24)	0	1	650	1
Bin	(24)	1	0	2251	1
Bin	(23)	0	1	676	1
Bin	(23)	1	0	2277	1
Bin	(22)	0	1	660	1
Bin	(22)	1	0	2261	1
Bin	(21)	0	1	662	1
Bin	(21)	1	0	2263	1
Bin	(20)	0	1	654	1
Bin	(20)	1	0	2255	1
Bin	(19)	0	1	645	1
Bin	(19)	1	0	2246	1
Bin	(18)	0	1	666	1
Bin	(18)	1	0	2267	1
Bin	(17)	0	1	648	1
Bin	(17)	1	0	2249	1
Bin	(16)	0	1	610	1
Bin	(16)	1	0	2211	1
Bin	(15)	0	1	631	1
Bin	(15)	1	0	2232	1
Bin	(14)	0	1	626	1
Bin	(14)	1	0	2227	1
Bin	(13)	0	1	605	1
Bin	(13)	1	0	2206	1
Bin	(12)	0	1	629	1
Bin	(12)	1	0	2230	1
Bin	(11)	0	1	609	1
Bin	(11)	1	0	2210	1
Bin	(10)	0	1	618	1
Bin	(10)	1	0	2219	1
Bin	(9)	0	1	629	1
Bin	(9)	1	0	2230	1
Bin	(8)	0	1	616	1
Bin	(8)	1	0	2217	1
Bin	(7)	0	1	647	1
Bin	(7)	1	0	2248	1
Bin	(6)	0	1	644	1
Bin	(6)	1	0	2245	1
Bin	(5)	0	1	637	1
Bin	(5)	1	0	2238	1
Bin	(4)	0	1	616	1
Bin	(4)	1	0	2217	1
Bin	(3)	0	1	642	1
Bin	(3)	1	0	2243	1
Bin	(2)	0	1	634	1
Bin	(2)	1	0	2235	1
Bin	(1)	0	1	650	1
Bin	(1)	1	0	2251	1
Bin	(0)	0	1	621	1
Bin	(0)	1	0	2222	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	4873	1
Bin	(3)	1	0	3275	1
Bin	(2)	0	1	12944	1
Bin	(2)	1	0	14542	1
Bin	(1)	0	1	15017	1
Bin	(1)	1	0	16618	1
Bin	(0)	0	1	15536	1
Bin	(0)	1	0	17137	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	12686	1
Bin	1	0	14287	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	25501	1
Bin	LOCK	1	0	27102	1
Bin	VALID	0	1	11115	1
Bin	VALID	1	0	12716	1
Bin	ERR	0	1	4269	1
Bin	ERR	1	0	5870	1
Bin	ARBL	0	1	455	1
Bin	ARBL	1	0	2056	1
Bin	FAILED	0	1	9651	1
Bin	FAILED	1	0	11252	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	5387	1
Bin	(31)	1	0	6988	1
Bin	(30)	0	1	5258	1
Bin	(30)	1	0	6859	1
Bin	(29)	0	1	5105	1
Bin	(29)	1	0	6706	1
Bin	(28)	0	1	13857	1
Bin	(28)	1	0	15458	1
Bin	(27)	0	1	10557	1
Bin	(27)	1	0	12158	1
Bin	(26)	0	1	13583	1
Bin	(26)	1	0	15184	1
Bin	(25)	0	1	10896	1
Bin	(25)	1	0	12497	1
Bin	(24)	0	1	14502	1
Bin	(24)	1	0	16103	1
Bin	(23)	0	1	12066	1
Bin	(23)	1	0	13667	1
Bin	(22)	0	1	13678	1
Bin	(22)	1	0	15279	1
Bin	(21)	0	1	12068	1
Bin	(21)	1	0	13669	1
Bin	(20)	0	1	13934	1
Bin	(20)	1	0	15535	1
Bin	(19)	0	1	11916	1
Bin	(19)	1	0	13517	1
Bin	(18)	0	1	14668	1
Bin	(18)	1	0	16269	1
Bin	(17)	0	1	8368	1
Bin	(17)	1	0	9969	1
Bin	(16)	0	1	8696	1
Bin	(16)	1	0	10297	1
Bin	(15)	0	1	8534	1
Bin	(15)	1	0	10135	1
Bin	(14)	0	1	8636	1
Bin	(14)	1	0	10237	1
Bin	(13)	0	1	8438	1
Bin	(13)	1	0	10039	1
Bin	(12)	0	1	8129	1
Bin	(12)	1	0	9730	1
Bin	(11)	0	1	8621	1
Bin	(11)	1	0	10222	1
Bin	(10)	0	1	9790	1
Bin	(10)	1	0	11391	1
Bin	(9)	0	1	14539	1
Bin	(9)	1	0	16140	1
Bin	(8)	0	1	8614	1
Bin	(8)	1	0	10215	1
Bin	(7)	0	1	19965	1
Bin	(7)	1	0	21566	1
Bin	(6)	0	1	16714	1
Bin	(6)	1	0	18315	1
Bin	(5)	0	1	11755	1
Bin	(5)	1	0	13356	1
Bin	(4)	0	1	10149	1
Bin	(4)	1	0	11750	1
Bin	(3)	0	1	14704	1
Bin	(3)	1	0	16305	1
Bin	(2)	0	1	16290	1
Bin	(2)	1	0	17891	1
Bin	(1)	0	1	16192	1
Bin	(1)	1	0	17793	1
Bin	(0)	0	1	18856	1
Bin	(0)	1	0	20457	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	15113	1
Bin	1	0	16714	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	13088	1
Bin	1	0	14689	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1826	1
Bin	1	0	3427	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1991	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	14689	1
Bin	1	0	13088	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	13088	1
Bin	1	0	14689	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8555	1
Bin	(31)	1	0	10106	1
Bin	(30)	0	1	8640	1
Bin	(30)	1	0	10190	1
Bin	(29)	0	1	8500	1
Bin	(29)	1	0	10051	1
Bin	(28)	0	1	22118	1
Bin	(28)	1	0	23588	1
Bin	(27)	0	1	17855	1
Bin	(27)	1	0	19312	1
Bin	(26)	0	1	22616	1
Bin	(26)	1	0	24093	1
Bin	(25)	0	1	18683	1
Bin	(25)	1	0	20151	1
Bin	(24)	0	1	22987	1
Bin	(24)	1	0	24455	1
Bin	(23)	0	1	19961	1
Bin	(23)	1	0	21424	1
Bin	(22)	0	1	22219	1
Bin	(22)	1	0	23678	1
Bin	(21)	0	1	20540	1
Bin	(21)	1	0	21992	1
Bin	(20)	0	1	21997	1
Bin	(20)	1	0	23466	1
Bin	(19)	0	1	20213	1
Bin	(19)	1	0	21644	1
Bin	(18)	0	1	23145	1
Bin	(18)	1	0	24595	1
Bin	(17)	0	1	13812	1
Bin	(17)	1	0	15316	1
Bin	(16)	0	1	13978	1
Bin	(16)	1	0	15483	1
Bin	(15)	0	1	13781	1
Bin	(15)	1	0	15293	1
Bin	(14)	0	1	13704	1
Bin	(14)	1	0	15206	1
Bin	(13)	0	1	13584	1
Bin	(13)	1	0	15097	1
Bin	(12)	0	1	13460	1
Bin	(12)	1	0	14966	1
Bin	(11)	0	1	14036	1
Bin	(11)	1	0	15546	1
Bin	(10)	0	1	15251	1
Bin	(10)	1	0	16708	1
Bin	(9)	0	1	25386	1
Bin	(9)	1	0	26719	1
Bin	(8)	0	1	14561	1
Bin	(8)	1	0	16067	1
Bin	(7)	0	1	34598	1
Bin	(7)	1	0	35793	1
Bin	(6)	0	1	24876	1
Bin	(6)	1	0	26166	1
Bin	(5)	0	1	19434	1
Bin	(5)	1	0	20895	1
Bin	(4)	0	1	15976	1
Bin	(4)	1	0	17472	1
Bin	(3)	0	1	26324	1
Bin	(3)	1	0	27687	1
Bin	(2)	0	1	28069	1
Bin	(2)	1	0	29388	1
Bin	(1)	0	1	26825	1
Bin	(1)	1	0	28189	1
Bin	(0)	0	1	35216	1
Bin	(0)	1	0	36410	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1991	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	1955	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	21542	1
Bin	1	0	23143	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	1734	1
Bin	1	0	3335	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1706	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	18585	1
Bin	1	0	20186	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	984	1
Bin	1	0	2585	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	984	1
Bin	1	0	2585	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	163731	1
Bin	1	0	165332	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	271833	1
Bin	1	0	273434	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	14238364	1
Bin	1	0	14239965	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1826	1
Bin	1	0	3427	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 246:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	178420	1
Bin	True	False	300	1
Bin	True	True	163731	1

"=" expression on line 246:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	193409	1
Bin	True	164031	1

"=" expression on line 246:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	15289	1
Bin	True	342151	1

"=" expression on line 259:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	86934	1
Bin	True	80838	1

"or" expression on line 269:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	278885	1
Bin	False	True	163731	1
Bin	True	False	107454	1

"=" expression on line 269:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	442616	1
Bin	True	107454	1

"=" expression on line 269:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	386339	1
Bin	True	163731	1

"=" expression on line 271:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	278237	1
Bin	True	648	1

"and" expression on lines 280 to 282:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	227488	1
Bin	True	False	1940	1
Bin	True	True	390	1

"and" expression on lines 280 to 281:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	185139	1
Bin	True	False	2579	1
Bin	True	True	2330	1

"=" expression on line 280:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	413355	1
Bin	True	4909	1

"=" expression on line 281:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	230795	1
Bin	True	187469	1

"=" expression on line 282:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	190386	1
Bin	True	227878	1

"=" expression on line 294:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"and" expression on line 305:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	6639	1
Bin	True	False	269	1
Bin	True	True	105	1

"=" expression on line 305:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	18241	1
Bin	True	374	1

"=" expression on line 305:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	11871	1
Bin	True	6744	1

"and" expression on line 308:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	13076	1
Bin	True	False	15020	1
Bin	True	True	18585	1

"=" expression on line 308:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	27386	1
Bin	True	33605	1

"=" expression on line 308:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	29330	1
Bin	True	31661	1

"and" expression on line 312:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	7533	1
Bin	True	False	755	1
Bin	True	True	984	1

"=" expression on line 312:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	19636	1
Bin	True	1739	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	12858	1
Bin	True	8517	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(0).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

Signal assignment statement on line 246:

Signal assignment statement on line 248:

If statement on lines 259 to 261:

Signal assignment statement on line 259:

Signal assignment statement on line 261:

If statement on lines 269 to 273:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 273:

If statement on lines 280 to 284:

Signal assignment statement on line 280:

Signal assignment statement on line 284:

Signal assignment statement on line 286:

If statement on lines 294 to 302:

Signal assignment statement on line 295:

Signal assignment statement on line 296:

Signal assignment statement on line 297:

Signal assignment statement on line 299:

Signal assignment statement on line 300:

Signal assignment statement on line 301:

If statement on lines 305 to 307:

Signal assignment statement on line 305:

Signal assignment statement on line 307:

If statement on lines 308 to 310:

Signal assignment statement on line 308:

Signal assignment statement on line 310:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

Signal assignment statement on line 317:

Signal assignment statement on line 405:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

"if" / "when" / "else" condition on line 259:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on line 271:

"if" / "when" / "else" condition on lines 280 to 282:

"if" / "when" / "else" condition on line 294:

"if" / "when" / "else" condition on line 298:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 308:

"if" / "when" / "else" condition on line 312:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: