| Current Instance | Statement | Branch | Toggle | Expression | FSM state | Functional | Average |
|---|---|---|---|---|---|---|---|
| CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(1).G_TXT_BUF_ODD.I_TXTB_ODD_TOP.I_TXTB_FSM | 100.0 % (80/80) | 100.0 % (94/94) | 100.0 % (70/70) | 100.0 % (151/151) | 100.0 % (16/16) | N.A. | 100.0 % (411/411) |
| Statement | Branch | Toggle | Expression | FSM state | Functional |
|---|
175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or
176: (curr_state = s_txt_tx_prog) or
177: (curr_state = s_txt_ready))
178: else
179: '0'; 175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 179: '0'; 181: go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or
182: mr_mode_bmm = BMM_ENABLED or
183: mr_mode_rom = ROM_ENABLED)
184: else
185: '0'; 181: go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 185: '0'; 187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')
188: else
189: (others => '0'); 187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1') 189: (others => '0'); 191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else
192: '0'; 191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 192: '0'; 194: txtb_allow_bb <= transient_state; 203: next_state <= curr_state; 205: case curr_state is
206:
...
360:
361: end case; 213: if (tx_command_txcr_valid = '1') then
214: next_state <= s_txt_ready;
215: end if; 214: next_state <= s_txt_ready; 223: if (go_to_failed = '1') then
224: next_state <= s_txt_failed;
...
242: next_state <= s_txt_aborted;
243: end if; 224: next_state <= s_txt_failed; 228: next_state <= s_txt_parity_err; 234: if (abort_applied = '1') then
235: next_state <= s_txt_ab_prog;
236: else
237: next_state <= s_txt_tx_prog;
238: end if; 235: next_state <= s_txt_ab_prog; 237: next_state <= s_txt_tx_prog; 242: next_state <= s_txt_aborted; 251: if (go_to_failed = '1') then
252: next_state <= s_txt_failed;
...
276: next_state <= s_txt_ab_prog;
277: end if; 252: next_state <= s_txt_failed; 256: next_state <= s_txt_parity_err; 260: next_state <= s_txt_failed; 264: next_state <= s_txt_ok; 268: if (abort_applied = '1') then
269: next_state <= s_txt_aborted;
270: else
271: next_state <= s_txt_ready;
272: end if; 269: next_state <= s_txt_aborted; 271: next_state <= s_txt_ready; 276: next_state <= s_txt_ab_prog; 285: if (go_to_failed = '1') then
286: next_state <= s_txt_failed;
...
302: next_state <= s_txt_aborted;
303: end if; 286: next_state <= s_txt_failed; 290: next_state <= s_txt_parity_err; 294: next_state <= s_txt_failed; 298: next_state <= s_txt_ok; 302: next_state <= s_txt_aborted; 311: if (tx_command_txcr_valid = '1') then
312: next_state <= s_txt_ready;
...
316: next_state <= s_txt_empty;
317: end if; 312: next_state <= s_txt_ready; 316: next_state <= s_txt_empty; 325: if (tx_command_txcr_valid = '1') then
326: next_state <= s_txt_ready;
...
330: next_state <= s_txt_empty;
331: end if; 326: next_state <= s_txt_ready; 330: next_state <= s_txt_empty; 339: if (tx_command_txcr_valid = '1') then
340: next_state <= s_txt_ready;
...
344: next_state <= s_txt_empty;
345: end if; 340: next_state <= s_txt_ready; 344: next_state <= s_txt_empty; 353: if (tx_command_txcr_valid = '1') then
354: next_state <= s_txt_ready;
...
358: next_state <= s_txt_empty;
359: end if; 354: next_state <= s_txt_ready; 358: next_state <= s_txt_empty; 368: txt_fsm_ce <= '1' when (next_state /= curr_state) else
369: '0'; 368: txt_fsm_ce <= '1' when (next_state /= curr_state) else 369: '0'; 376: if (rst_n = '0') then
377: curr_state <= s_txt_empty;
...
381: end if;
382: end if; 377: curr_state <= s_txt_empty; 379: if (txt_fsm_ce = '1') then
380: curr_state <= next_state;
381: end if; 380: curr_state <= next_state; 389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or
390: (curr_state = s_txt_tx_prog) or
391: (curr_state = s_txt_ab_prog))
392: else
393: '1'; 389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or 393: '1'; 396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely
397: (txtb_hw_cmd_i.valid = '1') or -- Finish transition OK
...
406: else
407: '0'; 396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely 404: '1' when (is_bus_off = '1' and next_state = s_txt_failed and 407: '0'; 411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))
412: else
413: '0'; 411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 413: '0'; 416: with curr_state select txtb_state <=
417: TXT_RDY when s_txt_ready,
...
423: TXT_ETY when s_txt_empty,
424: TXT_PER when s_txt_parity_err; 417: TXT_RDY when s_txt_ready, 418: TXT_TRAN when s_txt_tx_prog, 419: TXT_ABTP when s_txt_ab_prog, 420: TXT_TOK when s_txt_ok, 421: TXT_ERR when s_txt_failed, 422: TXT_ABT when s_txt_aborted, 423: TXT_ETY when s_txt_empty, 424: TXT_PER when s_txt_parity_err; 432: txtb_unmask_data_ram <= '1' when (transient_state = '1')
433: else
434: '0'; 432: txtb_unmask_data_ram <= '1' when (transient_state = '1') 434: '0'; 175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or
176: (curr_state = s_txt_tx_prog) or
177: (curr_state = s_txt_ready)) | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 17025 | 1 |
| Bin | False | 10565 | 1 |
181: go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or
182: mr_mode_bmm = BMM_ENABLED or
183: mr_mode_rom = ROM_ENABLED) | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 5365 | 1 |
| Bin | False | 16284 | 1 |
187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1') | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 39013 | 1 |
| Bin | False | 78969 | 1 |
191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 2092 | 1 |
| Bin | False | 5294 | 1 |
210: when s_txt_empty => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_empty | 21753 | 1 |
213: if (tx_command_txcr_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 4018 | 1 |
| Bin | False | 17735 | 1 |
220: when s_txt_ready => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_ready | 28736 | 1 |
223: if (go_to_failed = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 37 | 1 |
| Bin | False | 28699 | 1 |
227: elsif (txtb_parity_error_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 206 | 1 |
| Bin | False | 28493 | 1 |
231: elsif (txtb_hw_cmd_i.lock = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 8361 | 1 |
| Bin | False | 20132 | 1 |
234: if (abort_applied = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 5 | 1 |
| Bin | False | 8356 | 1 |
241: elsif (abort_or_skipped = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 202 | 1 |
| Bin | False | 19930 | 1 |
248: when s_txt_tx_prog => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_tx_prog | 27545 | 1 |
251: if (go_to_failed = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 10 | 1 |
| Bin | False | 27535 | 1 |
255: elsif (txtb_parity_error_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 115 | 1 |
| Bin | False | 27420 | 1 |
259: elsif (txtb_hw_cmd_i.failed = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 1854 | 1 |
| Bin | False | 25566 | 1 |
263: elsif (txtb_hw_cmd_i.valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 4348 | 1 |
| Bin | False | 21218 | 1 |
267: elsif (arbl_or_err = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 2056 | 1 |
| Bin | False | 19162 | 1 |
268: if (abort_applied = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 5 | 1 |
| Bin | False | 2051 | 1 |
275: elsif (abort_applied = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 138 | 1 |
| Bin | False | 19024 | 1 |
282: when s_txt_ab_prog => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_ab_prog | 309 | 1 |
285: if (go_to_failed = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 5 | 1 |
| Bin | False | 304 | 1 |
289: elsif (txtb_parity_error_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 5 | 1 |
| Bin | False | 299 | 1 |
293: elsif (txtb_hw_cmd_i.failed = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 19 | 1 |
| Bin | False | 280 | 1 |
297: elsif (txtb_hw_cmd_i.valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 15 | 1 |
| Bin | False | 265 | 1 |
301: elsif (arbl_or_err = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 31 | 1 |
| Bin | False | 234 | 1 |
308: when s_txt_failed => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_failed | 8767 | 1 |
311: if (tx_command_txcr_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 3341 | 1 |
| Bin | False | 5426 | 1 |
315: elsif (tx_command_txce_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 25 | 1 |
| Bin | False | 5401 | 1 |
322: when s_txt_aborted => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_aborted | 863 | 1 |
325: if (tx_command_txcr_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 210 | 1 |
| Bin | False | 653 | 1 |
329: elsif (tx_command_txce_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 5 | 1 |
| Bin | False | 648 | 1 |
336: when s_txt_ok => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_ok | 14150 | 1 |
339: if (tx_command_txcr_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 3758 | 1 |
| Bin | False | 10392 | 1 |
343: elsif (tx_command_txce_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 53 | 1 |
| Bin | False | 10339 | 1 |
350: when s_txt_parity_err => | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_parity_err | 251 | 1 |
353: if (tx_command_txcr_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 46 | 1 |
| Bin | False | 205 | 1 |
357: elsif (tx_command_txce_valid = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 12 | 1 |
| Bin | False | 193 | 1 |
368: txt_fsm_ce <= '1' when (next_state /= curr_state) else | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 31091 | 1 |
| Bin | False | 32687 | 1 |
376: if (rst_n = '0') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 2422674 | 1 |
| Bin | False | 1094358647 | 1 |
378: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 547174334 | 1 |
| Bin | False | 547184313 | 1 |
379: if (txt_fsm_ce = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 23664 | 1 |
| Bin | False | 547150670 | 1 |
389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or
390: (curr_state = s_txt_tx_prog) or
391: (curr_state = s_txt_ab_prog)) | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 17025 | 1 |
| Bin | False | 10565 | 1 |
396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely
397: (txtb_hw_cmd_i.valid = '1') or -- Finish transition OK
398: ((txtb_hw_cmd_i.arbl = '1' or
399: txtb_hw_cmd_i.err = '1') and
400: (curr_state = s_txt_ab_prog)) -- Not failed completely, but already in | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 25029 | 1 |
| Bin | False | 86585 | 1 |
404: '1' when (is_bus_off = '1' and next_state = s_txt_failed and
405: transient_state = '1') | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 44 | 1 |
| Bin | False | 86541 | 1 |
411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 8610 | 1 |
| Bin | False | 21039 | 1 |
417: TXT_RDY when s_txt_ready, | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_ready | 8605 | 1 |
418: TXT_TRAN when s_txt_tx_prog, | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_tx_prog | 8351 | 1 |
419: TXT_ABTP when s_txt_ab_prog, | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_ab_prog | 69 | 1 |
420: TXT_TOK when s_txt_ok, | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_ok | 4363 | 1 |
421: TXT_ERR when s_txt_failed, | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_failed | 1905 | 1 |
422: TXT_ABT when s_txt_aborted, | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_aborted | 223 | 1 |
423: TXT_ETY when s_txt_empty, | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_empty | 4016 | 1 |
424: TXT_PER when s_txt_parity_err; | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | s_txt_parity_err | 58 | 1 |
432: txtb_unmask_data_ram <= '1' when (transient_state = '1') | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 6554 | 1 |
| Bin | False | 9756 | 1 |
CLK_SYS| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
RST_N| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
MR_MODE_BMM| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
MR_MODE_ROM| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
MR_SETTINGS_TBFBO| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
TX_COMMAND_TXCE_VALID| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
TX_COMMAND_TXCR_VALID| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
ABORT_APPLIED| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
ABORT_OR_SKIPPED| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
TXTB_HW_CMD_CS| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
IS_BUS_OFF| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
TXTB_PARITY_ERROR_VALID| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
TXTB_HW_CMD| Element | From | To | Count | Threshold | |
|---|---|---|---|---|---|
| Bin | LOCK | 0 | 1 | 25501 | 1 |
| Bin | LOCK | 1 | 0 | 27102 | 1 |
| Bin | VALID | 0 | 1 | 11115 | 1 |
| Bin | VALID | 1 | 0 | 12716 | 1 |
| Bin | ERR | 0 | 1 | 4269 | 1 |
| Bin | ERR | 1 | 0 | 5870 | 1 |
| Bin | ARBL | 0 | 1 | 455 | 1 |
| Bin | ARBL | 1 | 0 | 2056 | 1 |
| Bin | FAILED | 0 | 1 | 9651 | 1 |
| Bin | FAILED | 1 | 0 | 11252 | 1 |
TXTB_USER_ACCESSIBLE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8155 | 1 |
| Bin | 1 | 0 | 6554 | 1 |
TXTB_ALLOW_BB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6554 | 1 |
| Bin | 1 | 0 | 8155 | 1 |
TXTB_HW_CMD_INT| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6312 | 1 |
| Bin | 1 | 0 | 7913 | 1 |
TXTB_STATE| Element | From | To | Count | Threshold | |
|---|---|---|---|---|---|
| Bin | (3) | 0 | 1 | 4054 | 1 |
| Bin | (3) | 1 | 0 | 2453 | 1 |
| Bin | (2) | 0 | 1 | 6491 | 1 |
| Bin | (2) | 1 | 0 | 8092 | 1 |
| Bin | (1) | 0 | 1 | 8570 | 1 |
| Bin | (1) | 1 | 0 | 10171 | 1 |
| Bin | (0) | 0 | 1 | 8461 | 1 |
| Bin | (0) | 1 | 0 | 10062 | 1 |
TXTB_AVAILABLE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8610 | 1 |
| Bin | 1 | 0 | 10211 | 1 |
TXTB_UNMASK_DATA_RAM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6554 | 1 |
| Bin | 1 | 0 | 8155 | 1 |
TXT_FSM_CE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31086 | 1 |
| Bin | 1 | 0 | 32687 | 1 |
GO_TO_FAILED| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5218 | 1 |
| Bin | 1 | 0 | 5230 | 1 |
TRANSIENT_STATE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6554 | 1 |
| Bin | 1 | 0 | 8155 | 1 |
TXTB_HW_CMD_I| Element | From | To | Count | Threshold | |
|---|---|---|---|---|---|
| Bin | LOCK | 0 | 1 | 8356 | 1 |
| Bin | LOCK | 1 | 0 | 9957 | 1 |
| Bin | VALID | 0 | 1 | 4363 | 1 |
| Bin | VALID | 1 | 0 | 5964 | 1 |
| Bin | ERR | 0 | 1 | 1885 | 1 |
| Bin | ERR | 1 | 0 | 3486 | 1 |
| Bin | ARBL | 0 | 1 | 207 | 1 |
| Bin | ARBL | 1 | 0 | 1808 | 1 |
| Bin | FAILED | 0 | 1 | 1896 | 1 |
| Bin | FAILED | 1 | 0 | 3497 | 1 |
ARBL_OR_ERR| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2092 | 1 |
| Bin | 1 | 0 | 3693 | 1 |
(curr_state = s_txt_ab_prog) or (curr_state = s_txt_tx_prog) or (curr_state = s_txt_ready)
<---------------------------LHS----------------------------> <---------RHS----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 10565 | 1 |
| Bin | False | True | 8605 | 1 |
| Bin | True | False | 8420 | 1 |
(curr_state = s_txt_ab_prog) or (curr_state = s_txt_tx_prog)
<----------LHS-----------> <----------RHS-----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 19170 | 1 |
| Bin | False | True | 8351 | 1 |
| Bin | True | False | 69 | 1 |
curr_state = s_txt_ab_prog | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 27521 | 1 |
| Bin | True | 69 | 1 |
curr_state = s_txt_tx_prog | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 19239 | 1 |
| Bin | True | 8351 | 1 |
curr_state = s_txt_ready | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 18985 | 1 |
| Bin | True | 8605 | 1 |
(is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or mr_mode_bmm = BMM_ENABLED or mr_mode_rom = ROM_ENABLED
<------------------------------------------------LHS------------------------------------------------> <----------RHS----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 16284 | 1 |
| Bin | False | True | 62 | 1 |
| Bin | True | False | 5268 | 1 |
(is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or mr_mode_bmm = BMM_ENABLED
<--------------------------------LHS---------------------------------> <----------RHS----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 16346 | 1 |
| Bin | False | True | 40 | 1 |
| Bin | True | False | 5253 | 1 |
is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED
<-----LHS------> <----------------------RHS----------------------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 2877 | 1 |
| Bin | True | False | 6349 | 1 |
| Bin | True | True | 5263 | 1 |
is_bus_off = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 10037 | 1 |
| Bin | True | 11612 | 1 |
mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 13509 | 1 |
| Bin | True | 8140 | 1 |
mr_mode_bmm = BMM_ENABLED | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 21599 | 1 |
| Bin | True | 50 | 1 |
mr_mode_rom = ROM_ENABLED | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 21552 | 1 |
| Bin | True | 97 | 1 |
txtb_hw_cmd_cs = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 78969 | 1 |
| Bin | True | 39013 | 1 |
txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1'
<---------LHS---------> <---------RHS----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 5294 | 1 |
| Bin | False | True | 207 | 1 |
| Bin | True | False | 1885 | 1 |
txtb_hw_cmd_i.err = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 5501 | 1 |
| Bin | True | 1885 | 1 |
txtb_hw_cmd_i.arbl = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 7179 | 1 |
| Bin | True | 207 | 1 |
tx_command_txcr_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 17735 | 1 |
| Bin | True | 4018 | 1 |
go_to_failed = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 28699 | 1 |
| Bin | True | 37 | 1 |
txtb_parity_error_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 28493 | 1 |
| Bin | True | 206 | 1 |
txtb_hw_cmd_i.lock = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 20132 | 1 |
| Bin | True | 8361 | 1 |
abort_applied = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 8356 | 1 |
| Bin | True | 5 | 1 |
abort_or_skipped = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 19930 | 1 |
| Bin | True | 202 | 1 |
go_to_failed = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 27535 | 1 |
| Bin | True | 10 | 1 |
txtb_parity_error_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 27420 | 1 |
| Bin | True | 115 | 1 |
txtb_hw_cmd_i.failed = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 25566 | 1 |
| Bin | True | 1854 | 1 |
txtb_hw_cmd_i.valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 21218 | 1 |
| Bin | True | 4348 | 1 |
arbl_or_err = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 19162 | 1 |
| Bin | True | 2056 | 1 |
abort_applied = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 2051 | 1 |
| Bin | True | 5 | 1 |
abort_applied = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 19024 | 1 |
| Bin | True | 138 | 1 |
go_to_failed = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 304 | 1 |
| Bin | True | 5 | 1 |
txtb_parity_error_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 299 | 1 |
| Bin | True | 5 | 1 |
txtb_hw_cmd_i.failed = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 280 | 1 |
| Bin | True | 19 | 1 |
txtb_hw_cmd_i.valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 265 | 1 |
| Bin | True | 15 | 1 |
arbl_or_err = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 234 | 1 |
| Bin | True | 31 | 1 |
tx_command_txcr_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 5426 | 1 |
| Bin | True | 3341 | 1 |
tx_command_txce_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 5401 | 1 |
| Bin | True | 25 | 1 |
tx_command_txcr_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 653 | 1 |
| Bin | True | 210 | 1 |
tx_command_txce_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 648 | 1 |
| Bin | True | 5 | 1 |
tx_command_txcr_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 10392 | 1 |
| Bin | True | 3758 | 1 |
tx_command_txce_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 10339 | 1 |
| Bin | True | 53 | 1 |
tx_command_txcr_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 205 | 1 |
| Bin | True | 46 | 1 |
tx_command_txce_valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 193 | 1 |
| Bin | True | 12 | 1 |
next_state /= curr_state | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 32687 | 1 |
| Bin | True | 31091 | 1 |
rst_n = '0' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 1094358647 | 1 |
| Bin | True | 2422674 | 1 |
txt_fsm_ce = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 547150670 | 1 |
| Bin | True | 23664 | 1 |
(curr_state = s_txt_ready) or (curr_state = s_txt_tx_prog) or (curr_state = s_txt_ab_prog)
<--------------------------LHS---------------------------> <----------RHS-----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 10565 | 1 |
| Bin | False | True | 69 | 1 |
| Bin | True | False | 16956 | 1 |
(curr_state = s_txt_ready) or (curr_state = s_txt_tx_prog)
<---------LHS----------> <----------RHS-----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 10634 | 1 |
| Bin | False | True | 8351 | 1 |
| Bin | True | False | 8605 | 1 |
curr_state = s_txt_ready | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 18985 | 1 |
| Bin | True | 8605 | 1 |
curr_state = s_txt_tx_prog | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 19239 | 1 |
| Bin | True | 8351 | 1 |
curr_state = s_txt_ab_prog | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 27521 | 1 |
| Bin | True | 69 | 1 |
(txtb_hw_cmd_i.failed = '1') or (txtb_hw_cmd_i.valid = '1') or ((txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.err = '1') and (curr_state = s_txt_ab_prog))
<---------------------------LHS---------------------------> <----------------------------------------RHS-----------------------------------------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 86585 | 1 |
| Bin | False | True | 62 | 1 |
| Bin | True | False | 24967 | 1 |
(txtb_hw_cmd_i.failed = '1') or (txtb_hw_cmd_i.valid = '1')
<----------LHS-----------> <----------RHS----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 86647 | 1 |
| Bin | False | True | 17452 | 1 |
| Bin | True | False | 7515 | 1 |
txtb_hw_cmd_i.failed = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 104099 | 1 |
| Bin | True | 7515 | 1 |
txtb_hw_cmd_i.valid = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 94162 | 1 |
| Bin | True | 17452 | 1 |
(txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.err = '1') and (curr_state = s_txt_ab_prog)
<-----------------------LHS-----------------------> <----------RHS-----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 143 | 1 |
| Bin | True | False | 6255 | 1 |
| Bin | True | True | 62 | 1 |
txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.err = '1'
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | False | 105297 | 1 |
| Bin | False | True | 5691 | 1 |
| Bin | True | False | 626 | 1 |
txtb_hw_cmd_i.arbl = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 110988 | 1 |
| Bin | True | 626 | 1 |
txtb_hw_cmd_i.err = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 105923 | 1 |
| Bin | True | 5691 | 1 |
curr_state = s_txt_ab_prog | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 111409 | 1 |
| Bin | True | 205 | 1 |
is_bus_off = '1' and next_state = s_txt_failed and transient_state = '1'
<--------------------LHS---------------------> <--------RHS--------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 32722 | 1 |
| Bin | True | False | 64 | 1 |
| Bin | True | True | 44 | 1 |
is_bus_off = '1' and next_state = s_txt_failed
<-----LHS------> <----------RHS----------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 3586 | 1 |
| Bin | True | False | 8275 | 1 |
| Bin | True | True | 108 | 1 |
is_bus_off = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 78202 | 1 |
| Bin | True | 8383 | 1 |
next_state = s_txt_failed | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 82891 | 1 |
| Bin | True | 3694 | 1 |
transient_state = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 53819 | 1 |
| Bin | True | 32766 | 1 |
(curr_state = s_txt_ready) and (abort_applied = '0')
<---------LHS----------> <-------RHS-------> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 18990 | 1 |
| Bin | True | False | 155 | 1 |
| Bin | True | True | 8610 | 1 |
curr_state = s_txt_ready | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 20884 | 1 |
| Bin | True | 8765 | 1 |
abort_applied = '0' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 2049 | 1 |
| Bin | True | 27600 | 1 |
transient_state = '1' | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 9756 | 1 |
| Bin | True | 6554 | 1 |
157: signal next_state : t_txt_buf_state; | State | Count | Threshold | |
|---|---|---|---|
| Bin | S_TXT_EMPTY | 5624 | 1 |
| Bin | S_TXT_READY | 13600 | 1 |
| Bin | S_TXT_TX_PROG | 8447 | 1 |
| Bin | S_TXT_AB_PROG | 75 | 1 |
| Bin | S_TXT_OK | 5972 | 1 |
| Bin | S_TXT_FAILED | 3493 | 1 |
| Bin | S_TXT_ABORTED | 244 | 1 |
| Bin | S_TXT_PARITY_ERR | 334 | 1 |
158: signal curr_state : t_txt_buf_state; | State | Count | Threshold | |
|---|---|---|---|
| Bin | S_TXT_EMPTY | 4016 | 1 |
| Bin | S_TXT_READY | 8605 | 1 |
| Bin | S_TXT_TX_PROG | 8351 | 1 |
| Bin | S_TXT_AB_PROG | 69 | 1 |
| Bin | S_TXT_OK | 4363 | 1 |
| Bin | S_TXT_FAILED | 1905 | 1 |
| Bin | S_TXT_ABORTED | 223 | 1 |
| Bin | S_TXT_PARITY_ERR | 58 | 1 |