NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_TRIGGER_MUX

File:  /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_top.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
I_CRC_TRIG_TX_WBS_REG 100.0 % (3/3) 100.0 % (4/4) 100.0 % (8/8) 100.0 % (2/2) N.A. N.A. 100.0 % (17/17)
I_CRC_DATA_RX_WBS_REG 100.0 % (4/4) 100.0 % (6/6) 100.0 % (10/10) 100.0 % (4/4) N.A. N.A. 100.0 % (24/24)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_TRIGGER_MUX 100.0 % (22/22) 100.0 % (16/16) 100.0 % (38/38) 100.0 % (46/46) N.A. N.A. 100.0 % (122/122)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 188 to 190:

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0') 
189:                         else 
190:                     '0'; 

Count: 24762439
Threshold: 1

Signal assignment statement on line 188:

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0') 
Count: 11432038
Threshold: 1

Signal assignment statement on line 190:

190:                     '0'
Count: 13330401
Threshold: 1

If statement on lines 192 to 194:

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
193:                         else 
194:                     '0'; 

Count: 22871784
Threshold: 1

Signal assignment statement on line 192:

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
Count: 10401065
Threshold: 1

Signal assignment statement on line 194:

194:                     '0'
Count: 12470719
Threshold: 1

Signal assignment statement on line 203:

203:    bst_trigger <= tx_trigger
Count: 22867275
Threshold: 1

Signal assignment statement on line 204:

204:    bds_trigger <= rx_triggers(1)
Count: 45723324
Threshold: 1

If statement on lines 214 to 216:

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
215:                           else 
216:                       '0'; 

Count: 22871784
Threshold: 1

Signal assignment statement on line 214:

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
Count: 10401065
Threshold: 1

Signal assignment statement on line 216:

216:                       '0'
Count: 12470719
Threshold: 1

If statement on lines 218 to 220:

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0') 
219:                           else 
220:                       '0'; 

Count: 24762439
Threshold: 1

Signal assignment statement on line 218:

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0') 
Count: 11432038
Threshold: 1

Signal assignment statement on line 220:

220:                       '0'
Count: 13330401
Threshold: 1

If statement on lines 243 to 245:

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
244:                       '1' when (tx_trigger_q = '1') else 
245:                       '0'; 

Count: 24783498
Threshold: 1

Signal assignment statement on line 243:

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
Count: 215343
Threshold: 1

Signal assignment statement on line 244:

244:                       '1' when (tx_trigger_q = '1') else 
Count: 12561025
Threshold: 1

Signal assignment statement on line 245:

245:                       '0'
Count: 12007130
Threshold: 1

If statement on lines 267 to 269:

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
268:                       '1' when (rx_triggers(0) = '1') else 
269:                       '0'; 

Count: 22899439
Threshold: 1

Signal assignment statement on line 267:

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
Count: 153592
Threshold: 1

Signal assignment statement on line 268:

268:                       '1' when (rx_triggers(0) = '1') else 
Count: 11346413
Threshold: 1

Signal assignment statement on line 269:

269:                       '0'
Count: 11399434
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 188:

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0'
Evaluated toCountThreshold
BinTrue114320381
BinFalse133304011

"if" / "when" / "else" condition on line 192:

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0'
Evaluated toCountThreshold
BinTrue104010651
BinFalse124707191

"if" / "when" / "else" condition on line 214:

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0'
Evaluated toCountThreshold
BinTrue104010651
BinFalse124707191

"if" / "when" / "else" condition on line 218:

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0'
Evaluated toCountThreshold
BinTrue114320381
BinFalse133304011

"if" / "when" / "else" condition on line 243:

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
Evaluated toCountThreshold
BinTrue2153431
BinFalse245681551

"if" / "when" / "else" condition on line 244:

244:                       '1' when (tx_trigger_q = '1') else 
Evaluated toCountThreshold
BinTrue125610251
BinFalse120071301

"if" / "when" / "else" condition on line 267:

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
Evaluated toCountThreshold
BinTrue1535921
BinFalse227458471

"if" / "when" / "else" condition on line 268:

268:                       '1' when (rx_triggers(0) = '1') else 
Evaluated toCountThreshold
BinTrue113464131
BinFalse113994341

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RST_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_TRIGGERS
ElementFromToCountThresholdExcluded due to
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 TX_TRIGGER
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 DATA_HALT
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 DESTUFFED
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 FIXED_STUFF
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 BDS_DATA_IN
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Port:

 PC_TX_TRIGGER
FromToCountThreshold
Bin01114320381
Bin10114336361

Port:

 PC_RX_TRIGGER
FromToCountThreshold
Bin01104010651
Bin10104026661

Port:

 BST_TRIGGER
FromToCountThreshold
Bin01114320381
Bin10114336361

Port:

 BDS_TRIGGER
FromToCountThreshold
Bin01228600611
Bin10228616621

Port:

 CRC_TRIG_RX_NBS
FromToCountThreshold
Bin01104010651
Bin10104026661

Port:

 CRC_TRIG_TX_NBS
FromToCountThreshold
Bin01114320381
Bin10114336361

Port:

 CRC_TRIG_RX_WBS
FromToCountThreshold
Bin01113464131
Bin10113480141

Port:

 CRC_TRIG_TX_WBS
FromToCountThreshold
Bin01114649731
Bin10114665741

Port:

 CRC_DATA_RX_WBS
FromToCountThreshold
Bin0114043571
Bin1014059471

Signal:

 TX_TRIGGER_Q
FromToCountThreshold
Bin01114279381
Bin10114295391

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 188:

 tx_trigger = '1' and data_halt = '0' 
 <-----LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue117508871
BinTrueFalse6303311
BinTrueTrue114320381

"=" expression on line 188:

 tx_trigger = '1' 
Evaluated toCountThreshold
BinFalse127000701
BinTrue120623691

"=" expression on line 188:

 data_halt = '0' 
Evaluated toCountThreshold
BinFalse15795141
BinTrue231829251

"and" expression on line 192:

 rx_triggers(0) = '1' and destuffed = '0' 
 <-------LHS-------->     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue104232291
BinTrueFalse10221441
BinTrueTrue104010651

"=" expression on line 192:

 rx_triggers(0) = '1' 
Evaluated toCountThreshold
BinFalse114485751
BinTrue114232091

"=" expression on line 192:

 destuffed = '0' 
Evaluated toCountThreshold
BinFalse20474901
BinTrue208242941

"and" expression on line 214:

 rx_triggers(0) = '1' and destuffed = '0' 
 <-------LHS-------->     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue104232291
BinTrueFalse10221441
BinTrueTrue104010651

"=" expression on line 214:

 rx_triggers(0) = '1' 
Evaluated toCountThreshold
BinFalse114485751
BinTrue114232091

"=" expression on line 214:

 destuffed = '0' 
Evaluated toCountThreshold
BinFalse20474901
BinTrue208242941

"and" expression on line 218:

 tx_trigger = '1' and data_halt = '0' 
 <-----LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue117508871
BinTrueFalse6303311
BinTrueTrue114320381

"=" expression on line 218:

 tx_trigger = '1' 
Evaluated toCountThreshold
BinFalse127000701
BinTrue120623691

"=" expression on line 218:

 data_halt = '0' 
Evaluated toCountThreshold
BinFalse15795141
BinTrue231829251

"and" expression on line 243:

 fixed_stuff = '1' and data_halt = '1' 
 <------LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue13684241
BinTrueFalse7404531
BinTrueTrue2153431

"=" expression on line 243:

 fixed_stuff = '1' 
Evaluated toCountThreshold
BinFalse238277021
BinTrue9557961

"=" expression on line 243:

 data_halt = '1' 
Evaluated toCountThreshold
BinFalse231997311
BinTrue15837671

"=" expression on line 244:

 tx_trigger_q = '1' 
Evaluated toCountThreshold
BinFalse120071301
BinTrue125610251

"and" expression on line 267:

 fixed_stuff = '1' and destuffed = '1' 
 <------LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue18911511
BinTrueFalse5501231
BinTrueTrue1535921

"=" expression on line 267:

 fixed_stuff = '1' 
Evaluated toCountThreshold
BinFalse221957241
BinTrue7037151

"=" expression on line 267:

 destuffed = '1' 
Evaluated toCountThreshold
BinFalse208546961
BinTrue20447431

"=" expression on line 268:

 rx_triggers(0) = '1' 
Evaluated toCountThreshold
BinFalse113994341
BinTrue113464131

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: