NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_CONTROL_COUNTER	100.0 % (45/45)	100.0 % (40/40)	100.0 % (158/158)	100.0 % (33/33)	N.A.	N.A.	100.0 % (276/276)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_CONTROL_COUNTER

100.0 % (45/45)

100.0 % (40/40)

100.0 % (158/158)

100.0 % (33/33)

N.A.

100.0 % (276/276)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 178 to 180:

178:    ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else 
179:                              (ctrl_ctr_q - 1) when (rx_trigger = '1') else 
180:                                   ctrl_ctr_q;

Count: 30101238
Threshold: 1

Signal assignment statement on line 178:

178: ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else
Count: 1863409
Threshold: 1

Signal assignment statement on line 179:

179: (ctrl_ctr_q - 1) when (rx_trigger = '1') else
Count: 17518287
Threshold: 1

Signal assignment statement on line 180:

180: ctrl_ctr_q;
Count: 10719542
Threshold: 1

If statement on lines 183 to 185:

183:    ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else 
184:                   '1' when (ctrl_ctr_pload = '1') else 
185:                   '0';

Count: 22459739
Threshold: 1

Signal assignment statement on line 183:

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else
Count: 7665354
Threshold: 1

Signal assignment statement on line 184:

184: '1' when (ctrl_ctr_pload = '1') else
Count: 829201
Threshold: 1

Signal assignment statement on line 185:

185: '0';
Count: 13965184
Threshold: 1

If statement on lines 187 to 189:

187:    ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0) 
188:                         else 
189:                     '0';

Count: 7411238
Threshold: 1

Signal assignment statement on line 187:

187: ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0)
Count: 356910
Threshold: 1

Signal assignment statement on line 189:

189: '0';
Count: 7054328
Threshold: 1

If statement on lines 191 to 193:

191:    ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1) 
192:                        else 
193:                    '0';

Count: 7411238
Threshold: 1

Signal assignment statement on line 191:

191: ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1)
Count: 352815
Threshold: 1

Signal assignment statement on line 193:

193: '0';
Count: 7058423
Threshold: 1

If statement on lines 200 to 206:

200:        if (rst_n = '0') then 
201:            ctrl_ctr_q <= (others => '0'); 
...
205:            end if; 
206:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 201:

201: ctrl_ctr_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 203 to 205:

203:            if (ctrl_ctr_ce = '1') then 
204:                ctrl_ctr_q <= ctrl_ctr_d; 
205:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 204:

204: ctrl_ctr_q <= ctrl_ctr_d;
Count: 7865556
Threshold: 1

If statement on lines 218 to 219:

218:    compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else 
219:                   compl_ctr_q + 1;

Count: 6177552
Threshold: 1

Signal assignment statement on line 218:

218: compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else
Count: 879261
Threshold: 1

Signal assignment statement on line 219:

219: compl_ctr_q + 1;
Count: 5298291
Threshold: 1

If statement on lines 221 to 223:

221:    compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else 
222:                    '1' when (compl_ctr_ena = '1') else 
223:                    '0';

Count: 10636686
Threshold: 1

Signal assignment statement on line 221:

221: compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else
Count: 889666
Threshold: 1

Signal assignment statement on line 222:

222: '1' when (compl_ctr_ena = '1') else
Count: 4469052
Threshold: 1

Signal assignment statement on line 223:

223: '0';
Count: 5277968
Threshold: 1

If statement on lines 227 to 233:

227:        if (rst_n = '0') then 
228:            compl_ctr_q <= (others => '0'); 
...
232:            end if; 
233:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 228:

228: compl_ctr_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 230 to 232:

230:            if (compl_ctr_ce = '1') then 
231:                compl_ctr_q <= compl_ctr_d; 
232:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 231:

231: compl_ctr_q <= compl_ctr_d;
Count: 5346369
Threshold: 1

If statement on lines 240 to 242:

240:    ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111") 
241:                             else 
242:                         '0';

Count: 4488738
Threshold: 1

Signal assignment statement on line 240:

240: ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111")
Count: 551752
Threshold: 1

Signal assignment statement on line 242:

242: '0';
Count: 3936986
Threshold: 1

Signal assignment statement on line 245:

245: ctrl_counted_byte_index <= std_logic_vector(compl_ctr_q(4 downto 3));
Count: 557738
Threshold: 1

Signal assignment statement on line 248:

248: compl_ctr_div_32 <= compl_ctr_q(G_CTRL_CTR_WIDTH - 1 downto 5);
Count: 144911
Threshold: 1

Signal assignment statement on line 251:

251: compl_ctr_div_32_plus_5 <= to_integer(compl_ctr_div_32) + 5;
Count: 144911
Threshold: 1

If statement on lines 254 to 256:

254:    compl_ctr_div_32_plus_5_sat <= 
255:        compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else 
256:        19;

Count: 144911
Threshold: 1

Signal assignment statement on line 255:

255: compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else
Count: 141497
Threshold: 1

Signal assignment statement on line 256:

256: 19;
Count: 3414
Threshold: 1

Signal assignment statement on line 267:

267: std_logic_vector(to_unsigned(compl_ctr_div_32_plus_5_sat, 5));
Count: 143588
Threshold: 1

If statement on lines 275 to 283:

275:        if (rst_n = '0') then 
276:            alc_alc_bit <= (others => '0'); 
...
282:            end if; 
283:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 276:

276: alc_alc_bit <= (others => '0');
Count: 2422674
Threshold: 1

Signal assignment statement on line 277:

277: alc_alc_id_field <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 279 to 282:

279:            if (arbitration_lost = '1') then 
280:                alc_alc_bit <= std_logic_vector(ctrl_ctr_q(4 downto 0)); 
281:                alc_alc_id_field <= arbitration_part; 
282:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 280:

280: alc_alc_bit <= std_logic_vector(ctrl_ctr_q(4 downto 0));
Count: 713
Threshold: 1

Signal assignment statement on line 281:

281: alc_alc_id_field <= arbitration_part;
Count: 713
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 178:

178: ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	1863409	1
Bin	False	28237829	1

"if" / "when" / "else" condition on line 179:

179: (ctrl_ctr_q - 1) when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	17518287	1
Bin	False	10719542	1

"if" / "when" / "else" condition on line 183:

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	7665354	1
Bin	False	14794385	1

"if" / "when" / "else" condition on line 184:

184: '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	829201	1
Bin	False	13965184	1

"if" / "when" / "else" condition on line 187:

187: ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0)

	Evaluated to	Count	Threshold
Bin	True	356910	1
Bin	False	7054328	1

"if" / "when" / "else" condition on line 191:

191: ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1)

	Evaluated to	Count	Threshold
Bin	True	352815	1
Bin	False	7058423	1

"if" / "when" / "else" condition on line 200:

200: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 202:

202: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 203:

203: if (ctrl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	7865556	1
Bin	False	539308778	1

"if" / "when" / "else" condition on line 218:

218: compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	879261	1
Bin	False	5298291	1

"if" / "when" / "else" condition on line 221:

221: compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	889666	1
Bin	False	9747020	1

"if" / "when" / "else" condition on line 222:

222: '1' when (compl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	4469052	1
Bin	False	5277968	1

"if" / "when" / "else" condition on line 227:

227: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 229:

229: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 230:

230: if (compl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	5346369	1
Bin	False	541827965	1

"if" / "when" / "else" condition on line 240:

240: ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111")

	Evaluated to	Count	Threshold
Bin	True	551752	1
Bin	False	3936986	1

"if" / "when" / "else" condition on line 255:

255: compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else

	Evaluated to	Count	Threshold
Bin	True	141497	1
Bin	False	3414	1

"if" / "when" / "else" condition on line 275:

275: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 278:

278: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 279:

279: if (arbitration_lost = '1') then

	Evaluated to	Count	Threshold
Bin	True	713	1
Bin	False	547173621	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRL_CTR_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRL_CTR_PLOAD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRL_CTR_PLOAD_VAL

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

COMPL_CTR_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ARBITRATION_LOST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ARBITRATION_PART

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

CTRL_CTR_ZERO

	From	To	Count	Threshold
Bin	0	1	356910	1
Bin	1	0	356918	1

Port:

CTRL_CTR_ONE

	From	To	Count	Threshold
Bin	0	1	352815	1
Bin	1	0	354416	1

Port:

CTRL_COUNTED_BYTE

	From	To	Count	Threshold
Bin	0	1	551752	1
Bin	1	0	553353	1

Port:

CTRL_COUNTED_BYTE_INDEX

	Element	From	To	Count	Threshold
Bin	(1)	0	1	136713	1
Bin	(1)	1	0	138314	1
Bin	(0)	0	1	274438	1
Bin	(0)	1	0	276039	1

Port:

CTRL_CTR_MEM_INDEX

	Element	From	To	Count	Threshold
Bin	(4)	0	1	4730	1
Bin	(4)	1	0	6331	1
Bin	(3)	0	1	12725	1
Bin	(3)	1	0	14326	1
Bin	(2)	0	1	19056	1
Bin	(2)	1	0	19056	1
Bin	(1)	0	1	40877	1
Bin	(1)	1	0	42478	1
Bin	(0)	0	1	68095	1
Bin	(0)	1	0	68095	1

Port:

ALC_ALC_BIT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	69	1
Bin	(4)	1	0	1668	1
Bin	(3)	0	1	90	1
Bin	(3)	1	0	1689	1
Bin	(2)	0	1	103	1
Bin	(2)	1	0	1702	1
Bin	(1)	0	1	173	1
Bin	(1)	1	0	1772	1
Bin	(0)	0	1	299	1
Bin	(0)	1	0	1898	1

Port:

ALC_ALC_ID_FIELD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33	1
Bin	(2)	1	0	1634	1
Bin	(1)	0	1	42	1
Bin	(1)	1	0	1641	1
Bin	(0)	0	1	95	1
Bin	(0)	1	0	1696	1

Signal:

CTRL_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	864275	1
Bin	(8)	1	0	865876	1
Bin	(7)	0	1	889238	1
Bin	(7)	1	0	890839	1
Bin	(6)	0	1	935581	1
Bin	(6)	1	0	937182	1
Bin	(5)	0	1	1051579	1
Bin	(5)	1	0	1053180	1
Bin	(4)	0	1	1313653	1
Bin	(4)	1	0	1315254	1
Bin	(3)	0	1	2083544	1
Bin	(3)	1	0	2085144	1
Bin	(2)	0	1	3449310	1
Bin	(2)	1	0	3450905	1
Bin	(1)	0	1	6025695	1
Bin	(1)	1	0	6027290	1
Bin	(0)	0	1	14156227	1
Bin	(0)	1	0	14157820	1

Signal:

CTRL_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	126986	1
Bin	(8)	1	0	128587	1
Bin	(7)	0	1	135210	1
Bin	(7)	1	0	136811	1
Bin	(6)	0	1	150538	1
Bin	(6)	1	0	152139	1
Bin	(5)	0	1	189222	1
Bin	(5)	1	0	190823	1
Bin	(4)	0	1	270969	1
Bin	(4)	1	0	272570	1
Bin	(3)	0	1	520141	1
Bin	(3)	1	0	521742	1
Bin	(2)	0	1	963277	1
Bin	(2)	1	0	964872	1
Bin	(1)	0	1	1869924	1
Bin	(1)	1	0	1871519	1
Bin	(0)	0	1	3594259	1
Bin	(0)	1	0	3595853	1

Signal:

CTRL_CTR_CE

	From	To	Count	Threshold
Bin	0	1	7812700	1
Bin	1	0	7814300	1

Signal:

COMPL_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	8048	1
Bin	(8)	1	0	9649	1
Bin	(7)	0	1	17481	1
Bin	(7)	1	0	19082	1
Bin	(6)	0	1	37317	1
Bin	(6)	1	0	38918	1
Bin	(5)	0	1	75444	1
Bin	(5)	1	0	77045	1
Bin	(4)	0	1	144782	1
Bin	(4)	1	0	146383	1
Bin	(3)	0	1	292339	1
Bin	(3)	1	0	293940	1
Bin	(2)	0	1	562119	1
Bin	(2)	1	0	563720	1
Bin	(1)	0	1	1124546	1
Bin	(1)	1	0	1126147	1
Bin	(0)	0	1	3038380	1
Bin	(0)	1	0	3036780	1

Signal:

COMPL_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	213184	1
Bin	(8)	1	0	350660	1
Bin	(7)	0	1	458765	1
Bin	(7)	1	0	601313	1
Bin	(6)	0	1	924233	1
Bin	(6)	1	0	1070319	1
Bin	(5)	0	1	2005371	1
Bin	(5)	1	0	2284724	1
Bin	(4)	0	1	1080670	1
Bin	(4)	1	0	1181836	1
Bin	(3)	0	1	2169076	1
Bin	(3)	1	0	2272795	1
Bin	(2)	0	1	560177	1
Bin	(2)	1	0	563616	1
Bin	(1)	0	1	1120662	1
Bin	(1)	1	0	1124101	1
Bin	(0)	0	1	2238417	1
Bin	(0)	1	0	2241856	1

Signal:

COMPL_CTR_DIV_32

	Element	From	To	Count	Threshold
Bin	(3)	0	1	7034	1
Bin	(3)	1	0	8635	1
Bin	(2)	0	1	15114	1
Bin	(2)	1	0	16715	1
Bin	(1)	0	1	30429	1
Bin	(1)	1	0	32030	1
Bin	(0)	0	1	67817	1
Bin	(0)	1	0	69418	1

Signal:

COMPL_CTR_CE

	From	To	Count	Threshold
Bin	0	1	5273166	1
Bin	1	0	5274766	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 178:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	28237829	1
Bin	True	1863409	1

"=" expression on line 179:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	10719542	1
Bin	True	17518287	1

"and" expression on line 183:

 rx_trigger = '1' and ctrl_ctr_ena = '1' 
 <-----LHS------>     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	7900251	1
Bin	True	False	3512693	1
Bin	True	True	7665354	1

"=" expression on line 183:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11281692	1
Bin	True	11178047	1

"=" expression on line 183:

ctrl_ctr_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	6894134	1
Bin	True	15565605	1

"=" expression on line 184:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	13965184	1
Bin	True	829201	1

"=" expression on line 200:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 203:

ctrl_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	539308778	1
Bin	True	7865556	1

"=" expression on line 218:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	5298291	1
Bin	True	879261	1

"=" expression on line 221:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	9747020	1
Bin	True	889666	1

"=" expression on line 222:

compl_ctr_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	5277968	1
Bin	True	4469052	1

"=" expression on line 227:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 230:

compl_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	541827965	1
Bin	True	5346369	1

"<" expression on line 255:

compl_ctr_div_32_plus_5 < 19

	Evaluated to	Count	Threshold
Bin	False	3414	1
Bin	True	141497	1

"=" expression on line 275:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 279:

arbitration_lost = '1'

	Evaluated to	Count	Threshold
Bin	False	547173621	1
Bin	True	713	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_CONTROL_COUNTER

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

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If statement on lines 183 to 185:

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If statement on lines 187 to 189:

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If statement on lines 254 to 256:

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Uncovered branches:

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"if" / "when" / "else" condition on line 178:

"if" / "when" / "else" condition on line 179:

"if" / "when" / "else" condition on line 183:

"if" / "when" / "else" condition on line 184:

"if" / "when" / "else" condition on line 187:

"if" / "when" / "else" condition on line 191:

"if" / "when" / "else" condition on line 200:

"if" / "when" / "else" condition on line 202:

"if" / "when" / "else" condition on line 203:

"if" / "when" / "else" condition on line 218:

"if" / "when" / "else" condition on line 221:

"if" / "when" / "else" condition on line 222:

"if" / "when" / "else" condition on line 227:

"if" / "when" / "else" condition on line 229:

"if" / "when" / "else" condition on line 230:

"if" / "when" / "else" condition on line 240:

"if" / "when" / "else" condition on line 255:

"if" / "when" / "else" condition on line 275:

"if" / "when" / "else" condition on line 278:

"if" / "when" / "else" condition on line 279:

Uncovered toggles:

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Port:

Port: