NVC code coverage report

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_SEGMENT_METER_DBT	100.0 % (66/66)	100.0 % (48/48)	100.0 % (90/90)	100.0 % (161/161)	N.A.	N.A.	100.0 % (365/365)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 273 to 277:

273:        if (a > b) then 
274:            return a; 
275:        else 
276:            return b; 
277:        end if;

Count: 8005
Threshold: 1

Sequential statement on line 274:

274: return a;
Count: 6404
Threshold: 1

Sequential statement on line 276:

276: return b;
Count: 1601
Threshold: 1

If statement on lines 351 to 354:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else 
354:                 '0';

Count: 68705637
Threshold: 1

Signal assignment statement on line 351:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

Count: 34416055
Threshold: 1

Signal assignment statement on line 354:

354: '0';
Count: 34289582
Threshold: 1

If statement on lines 356 to 358:

356:    basic_segm_length <= 
357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 
358:        resize(unsigned(tseg_2), C_BS_WIDTH);

Count: 68591397
Threshold: 1

Signal assignment statement on line 357:

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else
Count: 34287672
Threshold: 1

Signal assignment statement on line 358:

358: resize(unsigned(tseg_2), C_BS_WIDTH);
Count: 34303725
Threshold: 1

If statement on lines 360 to 364:

360:    segm_extension <= 
361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else 
363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 
364:        resize(unsigned(segm_counter), C_EXT_WIDTH);

Count: 104089745
Threshold: 1

Signal assignment statement on line 361:

361: to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or
Count: 68416
Threshold: 1

Signal assignment statement on line 363:

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else
Count: 59604862
Threshold: 1

Signal assignment statement on line 364:

364: resize(unsigned(segm_counter), C_EXT_WIDTH);
Count: 44416467
Threshold: 1

Signal assignment statement on lines 366 to 367:

366:    segm_ext_add <= resize(basic_segm_length, C_EXP_WIDTH) + 
367:                    resize(segm_extension, C_EXP_WIDTH);

Count: 115706407
Threshold: 1

Signal assignment statement on lines 369 to 370:

369:    segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) - 
370:                    resize(segm_extension, C_EXP_WIDTH);

Count: 115706407
Threshold: 1

If statement on lines 372 to 375:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1') 
374:                                     else 
375:                        segm_ext_add;

Count: 138673518
Threshold: 1

Signal assignment statement on line 372:

372: sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or
Count: 64037835
Threshold: 1

Signal assignment statement on line 375:

375: segm_ext_add;
Count: 74635683
Threshold: 1

If statement on lines 384 to 388:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0') 
387:                                 else 
388:                             '0';

Count: 45852936
Threshold: 1

Signal assignment statement on line 384:

384: use_basic_segm_length <= '1' when (start_edge = '1') or
Count: 22861592
Threshold: 1

Signal assignment statement on line 388:

388: '0';
Count: 22991344
Threshold: 1

If statement on lines 395 to 398:

395:    exp_seg_length_d <= 
396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 
397:                                               else 
398:        resize(sync_segm_length, C_EXP_WIDTH);

Count: 238568394
Threshold: 1

Signal assignment statement on line 396:

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')
Count: 131138548
Threshold: 1

Signal assignment statement on line 398:

398: resize(sync_segm_length, C_EXP_WIDTH);
Count: 107429846
Threshold: 1

If statement on lines 400 to 403:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1') 
402:                             else 
403:                         '0';

Count: 47446867
Threshold: 1

Signal assignment statement on line 400:

400: exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or
Count: 24237640
Threshold: 1

Signal assignment statement on line 403:

403: '0';
Count: 23209227
Threshold: 1

If statement on lines 407 to 413:

407:        if (rst_n = '0') then 
408:            exp_seg_length_q <= (others => '1'); 
...
412:            end if; 
413:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 408:

408: exp_seg_length_q <= (others => '1');
Count: 2422674
Threshold: 1

If statement on lines 410 to 412:

410:            if (exp_seg_length_ce = '1') then 
411:                exp_seg_length_q <= exp_seg_length_d; 
412:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 411:

411: exp_seg_length_q <= exp_seg_length_d;
Count: 23602497
Threshold: 1

Signal assignment statement on lines 425 to 426:

425:    neg_phase_err  <= resize(unsigned(tseg_2), C_E_WIDTH) - 
426:                      resize(unsigned(segm_counter), C_E_WIDTH);

Count: 93306400
Threshold: 1

If statement on lines 428 to 429:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 
429:                 resize(unsigned(segm_counter), C_E_WIDTH);

Count: 199408985
Threshold: 1

Signal assignment statement on line 428:

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else
Count: 68574854
Threshold: 1

Signal assignment statement on line 429:

429: resize(unsigned(segm_counter), C_E_WIDTH);
Count: 130834131
Threshold: 1

If statement on lines 431 to 434:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
433:                            else 
434:                        '0';

Count: 111069806
Threshold: 1

Signal assignment statement on line 431:

431: phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) >
Count: 59522652
Threshold: 1

Signal assignment statement on line 434:

434: '0';
Count: 51547154
Threshold: 1

If statement on lines 436 to 439:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
438:                            else 
439:                        '0';

Count: 111069806
Threshold: 1

Signal assignment statement on line 436:

436: phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
Count: 13525175
Threshold: 1

Signal assignment statement on line 439:

439: '0';
Count: 97544631
Threshold: 1

If statement on lines 441 to 445:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH))) 
444:                                else 
445:                            '0';

Count: 111069806
Threshold: 1

Signal assignment statement on line 441:

441: phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
Count: 6298433
Threshold: 1

Signal assignment statement on line 445:

445: '0';
Count: 104771373
Threshold: 1

If statement on lines 447 to 448:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 
448:                   '0';

Count: 5738
Threshold: 1

Signal assignment statement on line 447:

447: sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else
Count: 3899
Threshold: 1

Signal assignment statement on line 448:

448: '0';
Count: 1839
Threshold: 1

If statement on lines 458 to 461:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1') 
460:                              else 
461:                          '0';

Count: 41245323
Threshold: 1

Signal assignment statement on line 458:

458: exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and
Count: 7602
Threshold: 1

Signal assignment statement on line 461:

461: '0';
Count: 41237721
Threshold: 1

If statement on lines 468 to 470:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
469:                                     else 
470:                                 '0';

Count: 12615254
Threshold: 1

Signal assignment statement on line 468:

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')
Count: 7379
Threshold: 1

Signal assignment statement on line 470:

470: '0';
Count: 12607875
Threshold: 1

If statement on lines 475 to 478:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH)) 
477:                             else 
478:                         '0';

Count: 116185587
Threshold: 1

Signal assignment statement on line 475:

475: exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >=
Count: 17344466
Threshold: 1

Signal assignment statement on line 478:

478: '0';
Count: 98841121
Threshold: 1

If statement on lines 486 to 491:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1') 
488:                                    else 
489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
490:                                    else 
491:                                '0';

Count: 39514149
Threshold: 1

Signal assignment statement on line 486:

486: exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and
Count: 629208
Threshold: 1

Signal assignment statement on line 489:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

Count: 5079814
Threshold: 1

Signal assignment statement on line 491:

491: '0';
Count: 33805127
Threshold: 1

If statement on lines 496 to 498:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
497:                                   else 
498:                               '0';

Count: 37909019
Threshold: 1

Signal assignment statement on line 496:

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')
Count: 9992528
Threshold: 1

Signal assignment statement on line 498:

498: '0';
Count: 27916491
Threshold: 1

If statement on lines 507 to 510:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
509:                         else 
510:                     '0';

Count: 25115580
Threshold: 1

Signal assignment statement on line 507:

507: exit_segm_req <= '1' when (exit_ph2_immediate = '1') or
Count: 15079914
Threshold: 1

Signal assignment statement on line 510:

510: '0';
Count: 10035666
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 273:

273: if (a > b) then

	Evaluated to	Count	Threshold
Bin	True	6404	1
Bin	False	1601	1

"if" / "when" / "else" condition on lines 351 to 353:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	True	34416055	1
Bin	False	34289582	1

"if" / "when" / "else" condition on line 357:

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	True	34287672	1
Bin	False	34303725	1

"if" / "when" / "else" condition on lines 361 to 362:

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	True	68416	1
Bin	False	104021329	1

"if" / "when" / "else" condition on line 363:

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else

	Evaluated to	Count	Threshold
Bin	True	59604862	1
Bin	False	44416467	1

"if" / "when" / "else" condition on lines 372 to 373:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1')

	Evaluated to	Count	Threshold
Bin	True	64037835	1
Bin	False	74635683	1

"if" / "when" / "else" condition on lines 384 to 386:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0')

	Evaluated to	Count	Threshold
Bin	True	22861592	1
Bin	False	22991344	1

"if" / "when" / "else" condition on line 396:

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')

	Evaluated to	Count	Threshold
Bin	True	131138548	1
Bin	False	107429846	1

"if" / "when" / "else" condition on lines 400 to 401:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1')

	Evaluated to	Count	Threshold
Bin	True	24237640	1
Bin	False	23209227	1

"if" / "when" / "else" condition on line 407:

407: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 409:

409: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 410:

410: if (exp_seg_length_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	23602497	1
Bin	False	523571837	1

"if" / "when" / "else" condition on line 428:

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	True	68574854	1
Bin	False	130834131	1

"if" / "when" / "else" condition on lines 431 to 432:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	59522652	1
Bin	False	51547154	1

"if" / "when" / "else" condition on lines 436 to 437:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	13525175	1
Bin	False	97544631	1

"if" / "when" / "else" condition on lines 441 to 443:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH)))

	Evaluated to	Count	Threshold
Bin	True	6298433	1
Bin	False	104771373	1

"if" / "when" / "else" condition on line 447:

447: sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else

	Evaluated to	Count	Threshold
Bin	True	3899	1
Bin	False	1839	1

"if" / "when" / "else" condition on lines 458 to 459:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	7602	1
Bin	False	41237721	1

"if" / "when" / "else" condition on line 468:

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')

	Evaluated to	Count	Threshold
Bin	True	7379	1
Bin	False	12607875	1

"if" / "when" / "else" condition on lines 475 to 476:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	17344466	1
Bin	False	98841121	1

"if" / "when" / "else" condition on lines 486 to 487:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1')

	Evaluated to	Count	Threshold
Bin	True	629208	1
Bin	False	38884941	1

"if" / "when" / "else" condition on line 489:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	True	5079814	1
Bin	False	33805127	1

"if" / "when" / "else" condition on line 496:

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	True	9992528	1
Bin	False	27916491	1

"if" / "when" / "else" condition on lines 507 to 508:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	Evaluated to	Count	Threshold
Bin	True	15079914	1
Bin	False	10035666	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RESYNC_EDGE_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TSEG1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TSEG2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TSEG_1

	Element	From	To	Threshold	Excluded due to
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TSEG_2

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SJW

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

START_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SEGM_COUNTER

	Element	From	To	Threshold	Excluded due to
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SEGM_END

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

H_SYNC_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

EXIT_SEGM_REQ

	From	To	Count	Threshold
Bin	0	1	10032464	1
Bin	1	0	10034065	1

Signal:

SEL_TSEG1

	From	To	Count	Threshold
Bin	0	1	34284010	1
Bin	1	0	34285600	1

Signal:

EXP_SEG_LENGTH_CE

	From	To	Count	Threshold
Bin	0	1	23204426	1
Bin	1	0	23206025	1

Signal:

PHASE_ERR_MT_SJW

	From	To	Count	Threshold
Bin	0	1	5332058	1
Bin	1	0	5333657	1

Signal:

PHASE_ERR_EQ_SJW

	From	To	Count	Threshold
Bin	0	1	13525175	1
Bin	1	0	13526769	1

Signal:

EXIT_PH2_IMMEDIATE

	From	To	Count	Threshold
Bin	0	1	7596	1
Bin	1	0	9197	1

Signal:

EXIT_SEGM_REGULAR

	From	To	Count	Threshold
Bin	0	1	10022147	1
Bin	1	0	10023748	1

Signal:

EXIT_SEGM_REGULAR_TSEG1

	From	To	Count	Threshold
Bin	0	1	5079782	1
Bin	1	0	5081383	1

Signal:

EXIT_SEGM_REGULAR_TSEG2

	From	To	Count	Threshold
Bin	0	1	9992528	1
Bin	1	0	9994129	1

Signal:

SJW_MT_ZERO

	From	To	Count	Threshold
Bin	0	1	1830	1
Bin	1	0	1839	1

Signal:

USE_BASIC_SEGM_LENGTH

	From	To	Count	Threshold
Bin	0	1	22861592	1
Bin	1	0	22863191	1

Signal:

PHASE_ERR_SJW_BY_ONE

	From	To	Count	Threshold
Bin	0	1	6298433	1
Bin	1	0	6300034	1

Signal:

SHORTEN_TSEG1_AFTER_TSEG2

	From	To	Count	Threshold
Bin	0	1	7379	1
Bin	1	0	8980	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

">" expression on line 273:

a > b

	Evaluated to	Count	Threshold
Bin	False	1601	1
Bin	True	6404	1

"or" expression on lines 351 to 353:

 (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or (segm_end = '1' and is_tseg2 = '1') or (segm_end = '0' and is_tseg1 = '1') 
 <------------------------------------------------------LHS------------------------------------------------------->     <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	34289582	1
Bin	False	True	11478163	1
Bin	True	False	22887075	1

"or" expression on lines 351 to 352:

 (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or (segm_end = '1' and is_tseg2 = '1') 
  <----------------------------------LHS---------------------------------->      <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	45767745	1
Bin	False	True	22831865	1
Bin	True	False	91713	1

"or" expression on line 351:

 h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1' 
 <----------------LHS----------------->    <-------------RHS------------->

	LHS	RHS	Count	Threshold
Bin	False	False	68599610	1
Bin	False	True	20475	1
Bin	True	False	85552	1

"or" expression on line 351:

 h_sync_valid = '1' or start_edge = '1' 
 <------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	68620085	1
Bin	False	True	6482	1
Bin	True	False	79070	1

"=" expression on line 351:

h_sync_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	68626567	1
Bin	True	79070	1

"=" expression on line 351:

start_edge = '1'

	Evaluated to	Count	Threshold
Bin	False	68699155	1
Bin	True	6482	1

"=" expression on line 351:

shorten_tseg1_after_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	68685162	1
Bin	True	20475	1

"and" expression on line 352:

 segm_end = '1' and is_tseg2 = '1' 
 <----LHS----->     <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	11437701	1
Bin	True	False	22881503	1
Bin	True	True	22846179	1

"=" expression on line 352:

segm_end = '1'

	Evaluated to	Count	Threshold
Bin	False	22977955	1
Bin	True	45727682	1

"=" expression on line 352:

is_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	34421757	1
Bin	True	34283880	1

"and" expression on line 353:

 segm_end = '0' and is_tseg1 = '1' 
 <----LHS----->     <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	22882391	1
Bin	True	False	11445773	1
Bin	True	True	11528980	1

"=" expression on line 353:

segm_end = '0'

	Evaluated to	Count	Threshold
Bin	False	45730884	1
Bin	True	22974753	1

"=" expression on line 353:

is_tseg1 = '1'

	Evaluated to	Count	Threshold
Bin	False	34294266	1
Bin	True	34411371	1

"=" expression on line 357:

sel_tseg1 = '1'

	Evaluated to	Count	Threshold
Bin	False	34303725	1
Bin	True	34287672	1

"or" expression on lines 361 to 362:

 h_sync_valid = '1' or shorten_tseg1_after_tseg2 = '1' 
 <------LHS------->    <-------------RHS------------->

	LHS	RHS	Count	Threshold
Bin	False	False	104021329	1
Bin	False	True	13504	1
Bin	True	False	54912	1

"=" expression on line 361:

h_sync_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	104034833	1
Bin	True	54912	1

"=" expression on line 362:

shorten_tseg1_after_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	104076241	1
Bin	True	13504	1

"=" expression on line 363:

phase_err_mt_sjw = '1'

	Evaluated to	Count	Threshold
Bin	False	44416467	1
Bin	True	59604862	1

"or" expression on lines 372 to 373:

 is_tseg2 = '1' or h_sync_valid = '1' or exit_ph2_immediate = '1' 
 <---------------LHS---------------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	74635683	1
Bin	False	True	6830	1
Bin	True	False	64008936	1

"or" expression on line 372:

 is_tseg2 = '1' or h_sync_valid = '1' 
 <----LHS----->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	74642513	1
Bin	False	True	107052	1
Bin	True	False	63901372	1

"=" expression on line 372:

is_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	74749565	1
Bin	True	63923953	1

"=" expression on line 372:

h_sync_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	138543885	1
Bin	True	129633	1

"=" expression on line 373:

exit_ph2_immediate = '1'

	Evaluated to	Count	Threshold
Bin	False	138644619	1
Bin	True	28899	1

"or" expression on lines 384 to 386:

 (start_edge = '1') or (segm_end = '1' and h_sync_valid = '0' and shorten_tseg1_after_tseg2 = '0') 
  <-----LHS------>      <----------------------------------RHS---------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	22991344	1
Bin	False	True	22855110	1
Bin	True	False	6482	1

"=" expression on line 384:

start_edge = '1'

	Evaluated to	Count	Threshold
Bin	False	45846454	1
Bin	True	6482	1

"and" expression on lines 385 to 386:

 segm_end = '1' and h_sync_valid = '0' and shorten_tseg1_after_tseg2 = '0' 
 <----------------LHS---------------->     <-------------RHS------------->

	LHS	RHS	Count	Threshold
Bin	False	True	22982420	1
Bin	True	False	6709	1
Bin	True	True	22855110	1

"and" expression on line 385:

 segm_end = '1' and h_sync_valid = '0' 
 <----LHS----->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	22916328	1
Bin	True	False	20521	1
Bin	True	True	22861819	1

"=" expression on line 385:

segm_end = '1'

	Evaluated to	Count	Threshold
Bin	False	22970596	1
Bin	True	22882340	1

"=" expression on line 385:

h_sync_valid = '0'

	Evaluated to	Count	Threshold
Bin	False	74789	1
Bin	True	45778147	1

"=" expression on line 386:

shorten_tseg1_after_tseg2 = '0'

	Evaluated to	Count	Threshold
Bin	False	15406	1
Bin	True	45837530	1

"=" expression on line 396:

use_basic_segm_length = '1'

	Evaluated to	Count	Threshold
Bin	False	107429846	1
Bin	True	131138548	1

"or" expression on lines 400 to 401:

 segm_end = '1' or resync_edge_valid = '1' or h_sync_valid = '1' or start_edge = '1' 
 <-----------------------------LHS----------------------------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	23209227	1
Bin	False	True	6482	1
Bin	True	False	24231158	1

"or" expression on lines 400 to 401:

 segm_end = '1' or resync_edge_valid = '1' or h_sync_valid = '1' 
 <------------------LHS------------------>    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	23215709	1
Bin	False	True	51066	1
Bin	True	False	24159571	1

"or" expression on line 400:

 segm_end = '1' or resync_edge_valid = '1' 
 <----LHS----->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	23266775	1
Bin	False	True	733321	1
Bin	True	False	22946513	1

"=" expression on line 400:

segm_end = '1'

	Evaluated to	Count	Threshold
Bin	False	24000096	1
Bin	True	23446771	1

"=" expression on line 400:

resync_edge_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	46213288	1
Bin	True	1233579	1

"=" expression on line 401:

h_sync_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	47375280	1
Bin	True	71587	1

"=" expression on line 401:

start_edge = '1'

	Evaluated to	Count	Threshold
Bin	False	47440385	1
Bin	True	6482	1

"=" expression on line 407:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 410:

exp_seg_length_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	523571837	1
Bin	True	23602497	1

"=" expression on line 428:

is_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	130834131	1
Bin	True	68574854	1

"and" expression on lines 458 to 459:

 (phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and is_tseg2 = '1' and resync_edge_valid = '1' 
 <----------------------------------LHS---------------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	796644	1
Bin	True	False	13055746	1
Bin	True	True	7602	1

"and" expression on lines 458 to 459:

 (phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and is_tseg2 = '1' 
  <-----------------------LHS------------------------>      <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	5332680	1
Bin	True	False	17456501	1
Bin	True	True	13063348	1

"or" expression on line 458:

 phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1' 
 <--------LHS--------->    <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	10725474	1
Bin	False	True	7766737	1
Bin	True	False	22753112	1

"=" expression on line 458:

phase_err_mt_sjw = '0'

	Evaluated to	Count	Threshold
Bin	False	18492211	1
Bin	True	22753112	1

"=" expression on line 458:

phase_err_sjw_by_one = '1'

	Evaluated to	Count	Threshold
Bin	False	33478586	1
Bin	True	7766737	1

"=" expression on line 459:

is_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	22849295	1
Bin	True	18396028	1

"=" expression on line 459:

resync_edge_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	40441077	1
Bin	True	804246	1

"and" expression on line 468:

 exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0' 
 <---------LHS---------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	6307407	1
Bin	True	False	217	1
Bin	True	True	7379	1

"=" expression on line 468:

exit_ph2_immediate = '1'

	Evaluated to	Count	Threshold
Bin	False	12607658	1
Bin	True	7596	1

"=" expression on line 468:

phase_err_sjw_by_one = '0'

	Evaluated to	Count	Threshold
Bin	False	6300468	1
Bin	True	6314786	1

"and" expression on lines 486 to 487:

 is_tseg1 = '1' and resync_edge_valid = '1' and sjw_mt_zero = '1' 
 <------------------LHS------------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	30154613	1
Bin	True	False	154960	1
Bin	True	True	629208	1

"and" expression on line 486:

 is_tseg1 = '1' and resync_edge_valid = '1' 
 <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	20035	1
Bin	True	False	17300925	1
Bin	True	True	784168	1

"=" expression on line 486:

is_tseg1 = '1'

	Evaluated to	Count	Threshold
Bin	False	21429056	1
Bin	True	18085093	1

"=" expression on line 486:

resync_edge_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	38709946	1
Bin	True	804203	1

"=" expression on line 487:

sjw_mt_zero = '1'

	Evaluated to	Count	Threshold
Bin	False	8730328	1
Bin	True	30783821	1

"and" expression on line 489:

 is_tseg1 = '1' and exit_segm_regular = '1' 
 <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	9992745	1
Bin	True	False	12376071	1
Bin	True	True	5079814	1

"=" expression on line 489:

is_tseg1 = '1'

	Evaluated to	Count	Threshold
Bin	False	21429056	1
Bin	True	17455885	1

"=" expression on line 489:

exit_segm_regular = '1'

	Evaluated to	Count	Threshold
Bin	False	23812382	1
Bin	True	15072559	1

"and" expression on line 496:

 is_tseg2 = '1' and exit_segm_regular = '1' 
 <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	5076981	1
Bin	True	False	11402117	1
Bin	True	True	9992528	1

"=" expression on line 496:

is_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	16514374	1
Bin	True	21394645	1

"=" expression on line 496:

exit_segm_regular = '1'

	Evaluated to	Count	Threshold
Bin	False	22839510	1
Bin	True	15069509	1

"or" expression on lines 507 to 508:

 (exit_ph2_immediate = '1') or (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
  <---------LHS---------->      <----------------------------RHS----------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	10035666	1
Bin	False	True	15072318	1
Bin	True	False	7538	1

"=" expression on line 507:

exit_ph2_immediate = '1'

	Evaluated to	Count	Threshold
Bin	False	25107984	1
Bin	True	7596	1

"or" expression on line 508:

 exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1' 
 <------------LHS------------>    <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	False	10043204	1
Bin	False	True	9992594	1
Bin	True	False	5079782	1

"=" expression on line 508:

exit_segm_regular_tseg1 = '1'

	Evaluated to	Count	Threshold
Bin	False	20035798	1
Bin	True	5079782	1

"=" expression on line 508:

exit_segm_regular_tseg2 = '1'

	Evaluated to	Count	Threshold
Bin	False	15122986	1
Bin	True	9992594	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP.I_BTL_SEGMENT_METER_DBT

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bit_timing_logic/btl_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 273 to 277:

Sequential statement on line 274:

Sequential statement on line 276:

If statement on lines 351 to 354:

Signal assignment statement on line 351:

Signal assignment statement on line 354:

If statement on lines 356 to 358:

Signal assignment statement on line 357:

Signal assignment statement on line 358:

If statement on lines 360 to 364:

Signal assignment statement on line 361:

Signal assignment statement on line 363:

Signal assignment statement on line 364:

Signal assignment statement on lines 366 to 367:

Signal assignment statement on lines 369 to 370:

If statement on lines 372 to 375:

Signal assignment statement on line 372:

Signal assignment statement on line 375:

If statement on lines 384 to 388:

Signal assignment statement on line 384:

Signal assignment statement on line 388:

If statement on lines 395 to 398:

Signal assignment statement on line 396:

Signal assignment statement on line 398:

If statement on lines 400 to 403:

Signal assignment statement on line 400:

Signal assignment statement on line 403:

If statement on lines 407 to 413:

Signal assignment statement on line 408:

If statement on lines 410 to 412:

Signal assignment statement on line 411:

Signal assignment statement on lines 425 to 426:

If statement on lines 428 to 429:

Signal assignment statement on line 428:

Signal assignment statement on line 429:

If statement on lines 431 to 434:

Signal assignment statement on line 431:

Signal assignment statement on line 434:

If statement on lines 436 to 439:

Signal assignment statement on line 436:

Signal assignment statement on line 439:

If statement on lines 441 to 445:

Signal assignment statement on line 441:

Signal assignment statement on line 445:

If statement on lines 447 to 448:

Signal assignment statement on line 447:

Signal assignment statement on line 448:

If statement on lines 458 to 461:

Signal assignment statement on line 458:

Signal assignment statement on line 461:

If statement on lines 468 to 470:

Signal assignment statement on line 468:

Signal assignment statement on line 470:

If statement on lines 475 to 478:

Signal assignment statement on line 475:

Signal assignment statement on line 478:

If statement on lines 486 to 491:

Signal assignment statement on line 486:

Signal assignment statement on line 489:

Signal assignment statement on line 491:

If statement on lines 496 to 498:

Signal assignment statement on line 496:

Signal assignment statement on line 498:

If statement on lines 507 to 510:

Signal assignment statement on line 507:

Signal assignment statement on line 510:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 273:

"if" / "when" / "else" condition on lines 351 to 353:

"if" / "when" / "else" condition on line 357: