NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_BTL_CFG_CAPTURE	100.0 % (25/25)	100.0 % (14/14)	100.0 % (270/270)	100.0 % (20/20)	N.A.	N.A.	100.0 % (329/329)
I_BTL_SYNCHRONISATION_CHECKER	100.0 % (27/27)	100.0 % (24/24)	100.0 % (34/34)	100.0 % (68/68)	N.A.	N.A.	100.0 % (153/153)
I_BTL_SEGMENT_METER_NBT	100.0 % (66/66)	100.0 % (48/48)	100.0 % (96/96)	100.0 % (161/161)	N.A.	N.A.	100.0 % (371/371)
I_BTL_COUNTERS_NBT	100.0 % (23/23)	100.0 % (20/20)	100.0 % (114/114)	100.0 % (29/29)	N.A.	N.A.	100.0 % (186/186)
I_BTL_SEGMENT_METER_DBT	100.0 % (66/66)	100.0 % (48/48)	100.0 % (90/90)	100.0 % (161/161)	N.A.	N.A.	100.0 % (365/365)
I_BTL_COUNTERS_DBT	100.0 % (23/23)	100.0 % (20/20)	100.0 % (108/108)	100.0 % (29/29)	N.A.	N.A.	100.0 % (180/180)
I_BTL_SEGMENT_END_DETECTOR	100.0 % (63/63)	100.0 % (44/44)	100.0 % (72/72)	99.1 % (119/120)	N.A.	N.A.	99.6 % (298/299)
I_BTL_FSM	100.0 % (29/29)	100.0 % (26/26)	100.0 % (18/18)	100.0 % (18/18)	100.0 % (6/6)	N.A.	100.0 % (97/97)
I_BTL_TRIGGER_GENERATOR	100.0 % (16/16)	100.0 % (14/14)	100.0 % (22/22)	100.0 % (18/18)	N.A.	N.A.	100.0 % (70/70)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_BTL_CFG_CAPTURE

100.0 % (25/25)

100.0 % (14/14)

100.0 % (270/270)

100.0 % (20/20)

N.A.

100.0 % (329/329)

I_BTL_SYNCHRONISATION_CHECKER

100.0 % (27/27)

100.0 % (24/24)

100.0 % (34/34)

100.0 % (68/68)

N.A.

100.0 % (153/153)

I_BTL_SEGMENT_METER_NBT

100.0 % (66/66)

100.0 % (48/48)

100.0 % (96/96)

100.0 % (161/161)

N.A.

100.0 % (371/371)

I_BTL_COUNTERS_NBT

100.0 % (23/23)

100.0 % (20/20)

100.0 % (114/114)

100.0 % (29/29)

N.A.

100.0 % (186/186)

I_BTL_SEGMENT_METER_DBT

100.0 % (66/66)

100.0 % (48/48)

100.0 % (90/90)

100.0 % (161/161)

N.A.

100.0 % (365/365)

I_BTL_COUNTERS_DBT

100.0 % (23/23)

100.0 % (20/20)

100.0 % (108/108)

100.0 % (29/29)

N.A.

100.0 % (180/180)

I_BTL_SEGMENT_END_DETECTOR

100.0 % (63/63)

100.0 % (44/44)

100.0 % (72/72)

99.1 % (119/120)

N.A.

99.6 % (298/299)

I_BTL_FSM

100.0 % (29/29)

100.0 % (26/26)

100.0 % (18/18)

100.0 % (6/6)

N.A.

100.0 % (97/97)

I_BTL_TRIGGER_GENERATOR

100.0 % (16/16)

100.0 % (14/14)

100.0 % (22/22)

100.0 % (18/18)

N.A.

100.0 % (70/70)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (314/314)	N.A.	N.A.	N.A.	100.0 % (319/319)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP

100.0 % (3/3)

100.0 % (2/2)

100.0 % (314/314)

N.A.

100.0 % (319/319)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 474 to 475:

474:    tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else 
475:               tq_edge_dbt;

Count: 239868553
Threshold: 1

Signal assignment statement on line 474:

474: tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else
Count: 155473203
Threshold: 1

Signal assignment statement on line 475:

475: tq_edge_dbt;
Count: 84395350
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 474:

474: tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	155473203	1
Bin	False	84395350	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_BTR_PROP

	Element	From	To	Threshold	Excluded due to
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_PH1

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_PH2

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_BRP

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_SJW

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PROP_FD

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PH1_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PH2_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_BRP_FD

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_SJW_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SYNC_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SYNC_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

NO_POS_RESYNC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

NBT_CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DBT_CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

RX_TRIGGERS

	Element	From	To	Count	Threshold
Bin	(1)	0	1	34283270	1
Bin	(1)	1	0	34286472	1
Bin	(0)	0	1	22846418	1
Bin	(0)	1	0	45721723	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11432038	1
Bin	1	0	11433636	1

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	111638238	1
Bin	1	0	111639834	1

Signal:

TSEG1_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	459	1
Bin	(7)	1	0	2058	1
Bin	(6)	0	1	1687	1
Bin	(6)	1	0	3288	1
Bin	(5)	0	1	808	1
Bin	(5)	1	0	2407	1
Bin	(4)	0	1	934	1
Bin	(4)	1	0	2533	1
Bin	(3)	0	1	5979	1
Bin	(3)	1	0	4379	1
Bin	(2)	0	1	4192	1
Bin	(2)	1	0	5783	1
Bin	(1)	0	1	1066	1
Bin	(1)	1	0	2664	1
Bin	(0)	0	1	3761	1
Bin	(0)	1	0	2160	1

Signal:

TSEG2_NBT

	Element	From	To	Count	Threshold
Bin	(5)	0	1	206	1
Bin	(5)	1	0	1805	1
Bin	(4)	0	1	346	1
Bin	(4)	1	0	1944	1
Bin	(3)	0	1	315	1
Bin	(3)	1	0	1914	1
Bin	(2)	0	1	3874	1
Bin	(2)	1	0	2275	1
Bin	(1)	0	1	3412	1
Bin	(1)	1	0	5003	1
Bin	(0)	0	1	2158	1
Bin	(0)	1	0	557	1

Signal:

BRP_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	14	1
Bin	(7)	1	0	1615	1
Bin	(6)	0	1	12	1
Bin	(6)	1	0	1613	1
Bin	(5)	0	1	12	1
Bin	(5)	1	0	1613	1
Bin	(4)	0	1	16	1
Bin	(4)	1	0	1617	1
Bin	(3)	0	1	4831	1
Bin	(3)	1	0	3242	1
Bin	(2)	0	1	929	1
Bin	(2)	1	0	2523	1
Bin	(1)	0	1	4762	1
Bin	(1)	1	0	3170	1
Bin	(0)	0	1	2316	1
Bin	(0)	1	0	3914	1

Signal:

SJW_NBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	209	1
Bin	(4)	1	0	1807	1
Bin	(3)	0	1	266	1
Bin	(3)	1	0	1864	1
Bin	(2)	0	1	965	1
Bin	(2)	1	0	2563	1
Bin	(1)	0	1	2623	1
Bin	(1)	1	0	1031	1
Bin	(0)	0	1	3116	1
Bin	(0)	1	0	4714	1

Signal:

TSEG1_DBT

	Element	From	To	Count	Threshold
Bin	(6)	0	1	2335	1
Bin	(6)	1	0	3934	1
Bin	(5)	0	1	265	1
Bin	(5)	1	0	1866	1
Bin	(4)	0	1	2407	1
Bin	(4)	1	0	4006	1
Bin	(3)	0	1	3648	1
Bin	(3)	1	0	5238	1
Bin	(2)	0	1	4399	1
Bin	(2)	1	0	2798	1
Bin	(1)	0	1	3272	1
Bin	(1)	1	0	1680	1
Bin	(0)	0	1	2080	1
Bin	(0)	1	0	479	1

Signal:

TSEG2_DBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	281	1
Bin	(4)	1	0	1880	1
Bin	(3)	0	1	317	1
Bin	(3)	1	0	1916	1
Bin	(2)	0	1	1209	1
Bin	(2)	1	0	2799	1
Bin	(1)	0	1	1725	1
Bin	(1)	1	0	125	1
Bin	(0)	0	1	3868	1
Bin	(0)	1	0	2267	1

Signal:

BRP_DBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	18	1
Bin	(7)	1	0	1619	1
Bin	(6)	0	1	30	1
Bin	(6)	1	0	1631	1
Bin	(5)	0	1	17	1
Bin	(5)	1	0	1618	1
Bin	(4)	0	1	27	1
Bin	(4)	1	0	1628	1
Bin	(3)	0	1	28	1
Bin	(3)	1	0	1629	1
Bin	(2)	0	1	4843	1
Bin	(2)	1	0	3254	1
Bin	(1)	0	1	764	1
Bin	(1)	1	0	2363	1
Bin	(0)	0	1	2598	1
Bin	(0)	1	0	4189	1

Signal:

SJW_DBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	238	1
Bin	(4)	1	0	1836	1
Bin	(3)	0	1	282	1
Bin	(3)	1	0	1880	1
Bin	(2)	0	1	924	1
Bin	(2)	1	0	2522	1
Bin	(1)	0	1	2557	1
Bin	(1)	1	0	965	1
Bin	(0)	0	1	959	1
Bin	(0)	1	0	2557	1

Signal:

SEGMENT_END

	From	To	Count	Threshold
Bin	0	1	22860474	1
Bin	1	0	22862073	1

Signal:

H_SYNC_VALID

	From	To	Count	Threshold
Bin	0	1	54910	1
Bin	1	0	56511	1

Signal:

IS_TSEG1

	From	To	Count	Threshold
Bin	0	1	11429515	1
Bin	1	0	11429506	1

Signal:

IS_TSEG2

	From	To	Count	Threshold
Bin	0	1	11423197	1
Bin	1	0	11424796	1

Signal:

RESYNC_EDGE_VALID

	From	To	Count	Threshold
Bin	0	1	804203	1
Bin	1	0	805804	1

Signal:

H_SYNC_EDGE_VALID

	From	To	Count	Threshold
Bin	0	1	54911	1
Bin	1	0	56512	1

Signal:

SEGM_COUNTER_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	575352	1
Bin	(7)	1	0	576953	1
Bin	(6)	0	1	926888	1
Bin	(6)	1	0	928488	1
Bin	(5)	0	1	3240738	1
Bin	(5)	1	0	3242339	1
Bin	(4)	0	1	6980013	1
Bin	(4)	1	0	6981613	1
Bin	(3)	0	1	15522880	1
Bin	(3)	1	0	15524478	1
Bin	(2)	0	1	37911554	1
Bin	(2)	1	0	37913154	1
Bin	(1)	0	1	79493821	1
Bin	(1)	1	0	79495416	1
Bin	(0)	0	1	152248390	1
Bin	(0)	1	0	152249988	1

Signal:

SEGM_COUNTER_DBT

	Element	From	To	Count	Threshold
Bin	(6)	0	1	142320	1
Bin	(6)	1	0	143921	1
Bin	(5)	0	1	248387	1
Bin	(5)	1	0	249988	1
Bin	(4)	0	1	798552	1
Bin	(4)	1	0	800153	1
Bin	(3)	0	1	4518748	1
Bin	(3)	1	0	4520349	1
Bin	(2)	0	1	12010808	1
Bin	(2)	1	0	12012409	1
Bin	(1)	0	1	22910154	1
Bin	(1)	1	0	22911755	1
Bin	(0)	0	1	42613854	1
Bin	(0)	1	0	42615454	1

Signal:

EXIT_SEGM_REQ_NBT

	From	To	Count	Threshold
Bin	0	1	16517513	1
Bin	1	0	16519112	1

Signal:

EXIT_SEGM_REQ_DBT

	From	To	Count	Threshold
Bin	0	1	10032464	1
Bin	1	0	10034065	1

Signal:

TQ_EDGE_NBT

	From	To	Count	Threshold
Bin	0	1	99263834	1
Bin	1	0	99265430	1

Signal:

TQ_EDGE_DBT

	From	To	Count	Threshold
Bin	0	1	35305112	1
Bin	1	0	35306702	1

Signal:

RX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22860061	1
Bin	1	0	22861662	1

Signal:

TX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22854376	1
Bin	1	0	22855974	1

Signal:

START_EDGE

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8083	1

Signal:

BT_CTR_CLEAR

	From	To	Count	Threshold
Bin	0	1	22893999	1
Bin	1	0	22895598	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BTL_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 474 to 475:

Signal assignment statement on line 474:

Signal assignment statement on line 475:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 474:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: