NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_TXARB_PRIORITY_DECODER	100.0 % (82/82)	100.0 % (36/36)	100.0 % (194/194)	100.0 % (19/19)	N.A.	N.A.	100.0 % (331/331)
I_TXARB_FSM	100.0 % (126/126)	100.0 % (136/136)	100.0 % (54/54)	100.0 % (141/141)	100.0 % (16/16)	N.A.	100.0 % (473/473)
G_TXTB_PRIORITY(0)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
G_TXTB_PRIORITY(1)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)
G_TXTB_PRIORITY(2)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
G_TXTB_PRIORITY(3)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)
G_TXTB_PRIORITY(4)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
G_TXTB_PRIORITY(5)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)
G_TXTB_PRIORITY(6)	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
G_TXTB_PRIORITY(7)	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_TXARB_TOP	100.0 % (132/132)	100.0 % (102/102)	100.0 % (1420/1420)	98.3 % (119/121)	N.A.	N.A.	99.8 % (1773/1775)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 354 to 360:

354:        if (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or 
355:            ((a(63 downto 32) = b(63 downto 32)) and 
...
359:           return '0'; 
360:        end if;

Count: 811937
Threshold: 1

Sequential statement on line 357:

357: return '1';
Count: 347031
Threshold: 1

Sequential statement on line 359:

359: return '0';
Count: 464906
Threshold: 1

If statement on lines 444 to 446:

444:    timestamp_valid <= less_than(txtb_timestamp, timestamp) when (mr_mode_tttm = TTTM_ENABLED) 
445:                                                            else 
446:                                                        '1';

Count: 548545736
Threshold: 1

Signal assignment statement on line 444:

444: timestamp_valid <= less_than(txtb_timestamp, timestamp) when (mr_mode_tttm = TTTM_ENABLED)
Count: 811937
Threshold: 1

Signal assignment statement on line 446:

446:                                                        '1';

Count: 547733799
Threshold: 1

If statement on lines 454 to 457:

454:    validated_buffer <= '1' when (txtb_available(curr_txtb_index_i) = '1') and 
455:                                 (tran_frame_valid_com = '1') 
456:                            else 
457:                        '0';

Count: 111448
Threshold: 1

Signal assignment statement on line 454:

454: validated_buffer <= '1' when (txtb_available(curr_txtb_index_i) = '1') and
Count: 26158
Threshold: 1

Signal assignment statement on line 457:

457: '0';
Count: 85290
Threshold: 1

If statement on lines 459 to 461:

459:    tran_frame_valid <= '1' when (validated_buffer = '1') or (tx_arb_locked = '1') 
460:                            else 
461:                        '0';

Count: 105650
Threshold: 1

Signal assignment statement on line 459:

459: tran_frame_valid <= '1' when (validated_buffer = '1') or (tx_arb_locked = '1')
Count: 76702
Threshold: 1

Signal assignment statement on line 461:

461: '0';
Count: 28948
Threshold: 1

If statement on lines 467 to 469:

467:    txtb_parity_mismatch_vld <= '1' when (txtb_parity_mismatch(select_buf_index) = '1') 
468:                                    else 
469:                                '0';

Count: 56892
Threshold: 1

Signal assignment statement on line 467:

467: txtb_parity_mismatch_vld <= '1' when (txtb_parity_mismatch(select_buf_index) = '1')
Count: 4075
Threshold: 1

Signal assignment statement on line 469:

469: '0';
Count: 52817
Threshold: 1

If statement on lines 477 to 479:

477:    txtb_parity_mismatch_tx <= '1' when (txtb_parity_mismatch(curr_txtb_index_i) = '1') 
478:                                   else 
479:                               '0';

Count: 23130
Threshold: 1

Signal assignment statement on line 477:

477: txtb_parity_mismatch_tx <= '1' when (txtb_parity_mismatch(curr_txtb_index_i) = '1')
Count: 2828
Threshold: 1

Signal assignment statement on line 479:

479: '0';
Count: 20302
Threshold: 1

If statement on lines 481 to 483:

481:    tran_frame_parity_error <= '1' when (txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1') 
482:                                   else 
483:                               '0';

Count: 171249
Threshold: 1

Signal assignment statement on line 481:

481: tran_frame_parity_error <= '1' when (txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1')
Count: 699
Threshold: 1

Signal assignment statement on line 483:

483: '0';
Count: 170550
Threshold: 1

If statement on lines 489 to 491:

489:    txtb_index_muxed_i <= curr_txtb_index_i when (tx_arb_locked = '1') 
490:                                            else 
491:                          select_buf_index;

Count: 111222
Threshold: 1

Signal assignment statement on line 489:

489: txtb_index_muxed_i <= curr_txtb_index_i when (tx_arb_locked = '1')
Count: 50397
Threshold: 1

Signal assignment statement on line 491:

491: select_buf_index;
Count: 60825
Threshold: 1

If statement on lines 497 to 499:

497:    txtb_parity_check_valid <= txtb_clk_en_q when (tx_arb_locked = '1') 
498:                                             else 
499:                               tx_arb_parity_check_valid;

Count: 427227
Threshold: 1

Signal assignment statement on line 497:

497: txtb_parity_check_valid <= txtb_clk_en_q when (tx_arb_locked = '1')
Count: 180277
Threshold: 1

Signal assignment statement on line 499:

499: tx_arb_parity_check_valid;
Count: 246950
Threshold: 1

Signal assignment statement on line 502:

502: txtb_selected_input <= txtb_port_b_data_out(txtb_index_muxed_i);
Count: 197135
Threshold: 1

Signal assignment statement on line 505:

505: tran_word <= txtb_selected_input;
Count: 161387
Threshold: 1

Signal assignment statement on line 506:

506: txtb_index_muxed <= txtb_index_muxed_i;
Count: 40838
Threshold: 1

Signal assignment statement on line 512:

512: txtb_timestamp <= txtb_selected_input & ts_low_internal;
Count: 163388
Threshold: 1

Signal assignment statement on line 517:

517: tran_dlc <= tran_dlc_com;
Count: 14472
Threshold: 1

Signal assignment statement on line 518:

518: tran_is_rtr <= tran_is_rtr_com;
Count: 5546
Threshold: 1

Signal assignment statement on line 519:

519: tran_ident_type <= tran_ident_type_com;
Count: 8326
Threshold: 1

Signal assignment statement on line 520:

520: tran_frame_type <= tran_frame_type_com;
Count: 8628
Threshold: 1

Signal assignment statement on line 521:

521: tran_brs <= tran_brs_com;
Count: 7224
Threshold: 1

Signal assignment statement on line 522:

522: tran_identifier <= tran_identifier_com;
Count: 17798
Threshold: 1

If statement on lines 529 to 531:

529:    txtb_port_b_address <= std_logic_vector(to_unsigned(txtb_ptr, 5)) when (tx_arb_locked = '1') 
530:                                                                      else 
531:                           std_logic_vector(to_unsigned(txtb_pointer_meta_q, 5));

Count: 268000
Threshold: 1

Signal assignment statement on line 529:

529: txtb_port_b_address <= std_logic_vector(to_unsigned(txtb_ptr, 5)) when (tx_arb_locked = '1')
Count: 106383
Threshold: 1

Signal assignment statement on line 531:

531: std_logic_vector(to_unsigned(txtb_pointer_meta_q, 5));
Count: 161617
Threshold: 1

If statement on lines 533 to 535:

533:    txtb_port_b_clk_en <= txtb_clk_en when (tx_arb_locked = '1') 
534:                                      else 
535:                          txtb_meta_clk_en;

Count: 263721
Threshold: 1

Signal assignment statement on line 533:

533: txtb_port_b_clk_en <= txtb_clk_en when (tx_arb_locked = '1')
Count: 180277
Threshold: 1

Signal assignment statement on line 535:

535: txtb_meta_clk_en;
Count: 83444
Threshold: 1

Signal assignment statement on line 539:

539: txtb_hw_cmd_cs <= (others => '0');
Count: 13947
Threshold: 1

Signal assignment statement on line 540:

540: txtb_hw_cmd_cs(curr_txtb_index_i) <= '1';
Count: 13947
Threshold: 1

If statement on lines 548 to 552:

548:        if (rst_n = '0') then 
549:            txtb_clk_en_q <= '0'; 
550:        elsif (rising_edge(clk_sys)) then 
551:            txtb_clk_en_q <= txtb_clk_en; 
552:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 549:

549: txtb_clk_en_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 551:

551: txtb_clk_en_q <= txtb_clk_en;
Count: 547174334
Threshold: 1

If statement on lines 561 to 567:

561:        if (rst_n = '0') then 
562:            ts_low_internal <= (others => '0'); 
...
566:            end if; 
567:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 562:

562: ts_low_internal <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 564 to 566:

564:            if (store_ts_l_w = '1') then 
565:                ts_low_internal <= txtb_selected_input; 
566:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 565:

565: ts_low_internal <= txtb_selected_input;
Count: 26474
Threshold: 1

If statement on lines 575 to 589:

575:        if (rst_n = '0') then 
576:            tran_dlc_dbl_buf           <= (others => '0'); 
...
588:            end if; 
589:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 576:

576: tran_dlc_dbl_buf <= (others => '0');
Count: 2422674
Threshold: 1

Signal assignment statement on line 577:

577: tran_is_rtr_dbl_buf <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 578:

578: tran_ident_type_dbl_buf <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 579:

579: tran_frame_type_dbl_buf <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 580:

580: tran_brs_dbl_buf <= '0';
Count: 2422674
Threshold: 1

If statement on lines 582 to 588:

582:            if (buffer_md_w = '1') then 
583:                tran_dlc_dbl_buf           <= txtb_selected_input(DLC_H downto DLC_L); 
...
587:                tran_brs_dbl_buf           <= txtb_selected_input(BRS_IND); 
588:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 583:

583:                tran_dlc_dbl_buf           <= txtb_selected_input(DLC_H downto DLC_L);

Count: 25999
Threshold: 1

Signal assignment statement on line 584:

584: tran_is_rtr_dbl_buf <= txtb_selected_input(RTR_IND);
Count: 25999
Threshold: 1

Signal assignment statement on line 585:

585: tran_ident_type_dbl_buf <= txtb_selected_input(IDE_IND);
Count: 25999
Threshold: 1

Signal assignment statement on line 586:

586: tran_frame_type_dbl_buf <= txtb_selected_input(FDF_IND);
Count: 25999
Threshold: 1

Signal assignment statement on line 587:

587: tran_brs_dbl_buf <= txtb_selected_input(BRS_IND);
Count: 25999
Threshold: 1

If statement on lines 597 to 609:

597:        if (rst_n = '0') then 
598:            tran_frame_test_dbl_buf.fstc <= '0'; 
...
608:            end if; 
609:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 598:

598: tran_frame_test_dbl_buf.fstc <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 599:

599: tran_frame_test_dbl_buf.fcrc <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 600:

600: tran_frame_test_dbl_buf.sdlc <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 601:

601: tran_frame_test_dbl_buf.tprm <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 603 to 608:

603:            if (buffer_frame_test_w = '1') then 
604:                tran_frame_test_dbl_buf.fstc <= txtb_selected_input(FSTC_IND); 
605:                tran_frame_test_dbl_buf.fcrc <= txtb_selected_input(FCRC_IND); 
606:                tran_frame_test_dbl_buf.sdlc <= txtb_selected_input(SDLC_IND); 
607:                tran_frame_test_dbl_buf.tprm <= txtb_selected_input(TPRM_H downto TPRM_L); 
608:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 604:

604: tran_frame_test_dbl_buf.fstc <= txtb_selected_input(FSTC_IND);
Count: 26116
Threshold: 1

Signal assignment statement on line 605:

605: tran_frame_test_dbl_buf.fcrc <= txtb_selected_input(FCRC_IND);
Count: 26116
Threshold: 1

Signal assignment statement on line 606:

606: tran_frame_test_dbl_buf.sdlc <= txtb_selected_input(SDLC_IND);
Count: 26116
Threshold: 1

Signal assignment statement on line 607:

607: tran_frame_test_dbl_buf.tprm <= txtb_selected_input(TPRM_H downto TPRM_L);
Count: 26116
Threshold: 1

If statement on lines 619 to 633:

619:        if (rst_n = '0') then 
620:            tran_dlc_com         <= (others => '0'); 
...
632:            end if; 
633:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 620:

620: tran_dlc_com <= (others => '0');
Count: 2422674
Threshold: 1

Signal assignment statement on line 621:

621: tran_is_rtr_com <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 622:

622: tran_ident_type_com <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 623:

623: tran_frame_type_com <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 624:

624: tran_brs_com <= '0';
Count: 2422674
Threshold: 1

If statement on lines 626 to 632:

626:            if (commit_dbl_bufs = '1') then 
627:                tran_frame_type_com  <= tran_frame_type_dbl_buf; 
...
631:                tran_brs_com         <= tran_brs_dbl_buf; 
632:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 627:

627: tran_frame_type_com <= tran_frame_type_dbl_buf;
Count: 25783
Threshold: 1

Signal assignment statement on line 628:

628: tran_ident_type_com <= tran_ident_type_dbl_buf;
Count: 25783
Threshold: 1

Signal assignment statement on line 629:

629: tran_dlc_com <= tran_dlc_dbl_buf;
Count: 25783
Threshold: 1

Signal assignment statement on line 630:

630: tran_is_rtr_com <= tran_is_rtr_dbl_buf;
Count: 25783
Threshold: 1

Signal assignment statement on line 631:

631: tran_brs_com <= tran_brs_dbl_buf;
Count: 25783
Threshold: 1

If statement on lines 641 to 647:

641:        if (rst_n = '0') then 
642:            tran_identifier_com <= (others => '0'); 
...
646:            end if; 
647:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 642:

642: tran_identifier_com <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 644 to 646:

644:            if (commit_dbl_bufs = '1') then 
645:                tran_identifier_com <= txtb_selected_input(28 downto 0); 
646:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 645:

645: tran_identifier_com <= txtb_selected_input(28 downto 0);
Count: 25783
Threshold: 1

If statement on lines 655 to 664:

655:        if (rst_n = '0') then 
656:            tran_frame_test.fstc <= '0'; 
...
663:            end if; 
664:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 656:

656: tran_frame_test.fstc <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 657:

657: tran_frame_test.fcrc <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 658:

658: tran_frame_test.sdlc <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 659:

659: tran_frame_test.tprm <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 661 to 663:

661:            if (commit_dbl_bufs = '1') then 
662:                tran_frame_test <= tran_frame_test_dbl_buf; 
663:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 662:

662: tran_frame_test <= tran_frame_test_dbl_buf;
Count: 25783
Threshold: 1

If statement on lines 672 to 680:

672:        if (rst_n = '0') then 
673:            tran_frame_valid_com        <= '0'; 
...
679:            end if; 
680:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 673:

673: tran_frame_valid_com <= '0';
Count: 2422674
Threshold: 1

If statement on lines 675 to 679:

675:            if (frame_valid_com_set = '1') then 
676:                tran_frame_valid_com    <= '1'; 
677:            elsif (frame_valid_com_clear = '1') then 
678:                tran_frame_valid_com    <= '0'; 
679:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 676:

676: tran_frame_valid_com <= '1';
Count: 25783
Threshold: 1

Signal assignment statement on line 678:

678: tran_frame_valid_com <= '0';
Count: 26237
Threshold: 1

If statement on lines 691 to 706:

691:        if (rst_n = '0') then 
692:            last_txtb_index             <= 0; 
...
705: 
706:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 692:

692: last_txtb_index <= 0;
Count: 2422674
Threshold: 1

Signal assignment statement on line 693:

693: curr_txtb_index_i <= 0;
Count: 2422674
Threshold: 1

If statement on lines 697 to 699:

697:            if (store_last_txtb_index = '1') then 
698:                last_txtb_index         <= curr_txtb_index_i; 
699:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 698:

698: last_txtb_index <= curr_txtb_index_i;
Count: 25501
Threshold: 1

If statement on lines 702 to 704:

702:            if (commit_dbl_bufs = '1') then 
703:                curr_txtb_index_i       <= select_buf_index; 
704:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 703:

703: curr_txtb_index_i <= select_buf_index;
Count: 25783
Threshold: 1

If statement on lines 709 to 711:

709:    txtb_changed  <= '1' when (last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1') 
710:                         else 
711:                     '0';

Count: 76542
Threshold: 1

Signal assignment statement on line 709:

709:    txtb_changed  <= '1' when (last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1')

Count: 9992
Threshold: 1

Signal assignment statement on line 711:

711: '0';
Count: 66550
Threshold: 1

Signal assignment statement on line 713:

713: curr_txtb_index <= std_logic_vector(to_unsigned(curr_txtb_index_i, 3));
Count: 13947
Threshold: 1

If statement on lines 721 to 725:

721:        if (rst_n = '0') then 
722:            select_buf_index_reg  <= 0; 
723:        elsif (rising_edge(clk_sys)) then 
724:            select_buf_index_reg <= select_buf_index; 
725:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 722:

722: select_buf_index_reg <= 0;
Count: 2422674
Threshold: 1

Signal assignment statement on line 724:

724: select_buf_index_reg <= select_buf_index;
Count: 547174334
Threshold: 1

If statement on lines 728 to 730:

728:    select_index_changed <= '0' when (select_buf_index = select_buf_index_reg) 
729:                                else 
730:                            '1';

Count: 100909
Threshold: 1

Signal assignment statement on line 728:

728: select_index_changed <= '0' when (select_buf_index = select_buf_index_reg)
Count: 46626
Threshold: 1

Signal assignment statement on line 730:

730: '1';
Count: 54283
Threshold: 1

If statement on lines 736 to 742:

736:    txtb_pointer_meta_d <= 
737:        to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))) when (load_ts_lw_addr = '1') else 
...
741:        to_integer(unsigned(FRAME_TEST_W_ADR(11 downto 2))) when (load_frame_test_w_addr = '1') else 
742:        txtb_pointer_meta_q;

Count: 404108
Threshold: 1

Signal assignment statement on line 737:

737: to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))) when (load_ts_lw_addr = '1') else
Count: 50823
Threshold: 1

Signal assignment statement on line 738:

738: to_integer(unsigned(TIMESTAMP_U_W_ADR(11 downto 2))) when (load_ts_uw_addr = '1') else
Count: 53037
Threshold: 1

Signal assignment statement on line 739:

739: to_integer(unsigned(FRAME_FORMAT_W_ADR(11 downto 2))) when (load_ffmt_w_addr = '1') else
Count: 52288
Threshold: 1

Signal assignment statement on line 740:

740: to_integer(unsigned(IDENTIFIER_W_ADR(11 downto 2))) when (load_ident_w_addr = '1') else
Count: 52058
Threshold: 1

Signal assignment statement on line 741:

741:        to_integer(unsigned(FRAME_TEST_W_ADR(11 downto 2))) when (load_frame_test_w_addr = '1') else

Count: 52644
Threshold: 1

Signal assignment statement on line 742:

742: txtb_pointer_meta_q;
Count: 143258
Threshold: 1

If statement on lines 746 to 750:

746:        if (rst_n = '0') then 
747:            txtb_pointer_meta_q <= to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))); 
748:        elsif (rising_edge(clk_sys)) then 
749:            txtb_pointer_meta_q <= txtb_pointer_meta_d; 
750:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 747:

747: txtb_pointer_meta_q <= to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2)));
Count: 2422674
Threshold: 1

Signal assignment statement on line 749:

749: txtb_pointer_meta_q <= txtb_pointer_meta_d;
Count: 547174334
Threshold: 1

If statement on lines 756 to 759:

756:    txtb_hw_cmd_unlock <= '1' when (txtb_hw_cmd.valid  = '1' or txtb_hw_cmd.err    = '1' or 
757:                                    txtb_hw_cmd.arbl   = '1' or txtb_hw_cmd.failed = '1') 
758:                              else 
759:                          '0';

Count: 54182
Threshold: 1

Signal assignment statement on line 756:

756: txtb_hw_cmd_unlock <= '1' when (txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' or
Count: 25490
Threshold: 1

Signal assignment statement on line 759:

759: '0';
Count: 28692
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 354 to 356:

354:        if (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or 
355:            ((a(63 downto 32) = b(63 downto 32)) and 
356:            (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))))then

	Evaluated to	Count	Threshold
Bin	True	347031	1
Bin	False	464906	1

"if" / "when" / "else" condition on line 444:

444: timestamp_valid <= less_than(txtb_timestamp, timestamp) when (mr_mode_tttm = TTTM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	811937	1
Bin	False	547733799	1

"if" / "when" / "else" condition on lines 454 to 455:

454:    validated_buffer <= '1' when (txtb_available(curr_txtb_index_i) = '1') and 
455:                                 (tran_frame_valid_com = '1')

	Evaluated to	Count	Threshold
Bin	True	26158	1
Bin	False	85290	1

"if" / "when" / "else" condition on line 459:

459: tran_frame_valid <= '1' when (validated_buffer = '1') or (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	76702	1
Bin	False	28948	1

"if" / "when" / "else" condition on line 467:

467: txtb_parity_mismatch_vld <= '1' when (txtb_parity_mismatch(select_buf_index) = '1')

	Evaluated to	Count	Threshold
Bin	True	4075	1
Bin	False	52817	1

"if" / "when" / "else" condition on line 477:

477: txtb_parity_mismatch_tx <= '1' when (txtb_parity_mismatch(curr_txtb_index_i) = '1')

	Evaluated to	Count	Threshold
Bin	True	2828	1
Bin	False	20302	1

"if" / "when" / "else" condition on line 481:

481: tran_frame_parity_error <= '1' when (txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1')

	Evaluated to	Count	Threshold
Bin	True	699	1
Bin	False	170550	1

"if" / "when" / "else" condition on line 489:

489: txtb_index_muxed_i <= curr_txtb_index_i when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	50397	1
Bin	False	60825	1

"if" / "when" / "else" condition on line 497:

497: txtb_parity_check_valid <= txtb_clk_en_q when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	180277	1
Bin	False	246950	1

"if" / "when" / "else" condition on line 529:

529: txtb_port_b_address <= std_logic_vector(to_unsigned(txtb_ptr, 5)) when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	106383	1
Bin	False	161617	1

"if" / "when" / "else" condition on line 533:

533: txtb_port_b_clk_en <= txtb_clk_en when (tx_arb_locked = '1')

	Evaluated to	Count	Threshold
Bin	True	180277	1
Bin	False	83444	1

"if" / "when" / "else" condition on line 548:

548: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 550:

550: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 561:

561: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 563:

563: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 564:

564: if (store_ts_l_w = '1') then

	Evaluated to	Count	Threshold
Bin	True	26474	1
Bin	False	547147860	1

"if" / "when" / "else" condition on line 575:

575: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 581:

581: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 582:

582: if (buffer_md_w = '1') then

	Evaluated to	Count	Threshold
Bin	True	25999	1
Bin	False	547148335	1

"if" / "when" / "else" condition on line 597:

597: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 602:

602: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 603:

603: if (buffer_frame_test_w = '1') then

	Evaluated to	Count	Threshold
Bin	True	26116	1
Bin	False	547148218	1

"if" / "when" / "else" condition on line 619:

619: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 625:

625: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 626:

626: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25783	1
Bin	False	547148551	1

"if" / "when" / "else" condition on line 641:

641: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 643:

643: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 644:

644: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25783	1
Bin	False	547148551	1

"if" / "when" / "else" condition on line 655:

655: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 660:

660: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 661:

661: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25783	1
Bin	False	547148551	1

"if" / "when" / "else" condition on line 672:

672: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 674:

674: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 675:

675: if (frame_valid_com_set = '1') then

	Evaluated to	Count	Threshold
Bin	True	25783	1
Bin	False	547148551	1

"if" / "when" / "else" condition on line 677:

677: elsif (frame_valid_com_clear = '1') then

	Evaluated to	Count	Threshold
Bin	True	26237	1
Bin	False	547122314	1

"if" / "when" / "else" condition on line 691:

691: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 695:

695: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 697:

697: if (store_last_txtb_index = '1') then

	Evaluated to	Count	Threshold
Bin	True	25501	1
Bin	False	547148833	1

"if" / "when" / "else" condition on line 702:

702: if (commit_dbl_bufs = '1') then

	Evaluated to	Count	Threshold
Bin	True	25783	1
Bin	False	547148551	1

"if" / "when" / "else" condition on line 709:

709:    txtb_changed  <= '1' when (last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1')

	Evaluated to	Count	Threshold
Bin	True	9992	1
Bin	False	66550	1

"if" / "when" / "else" condition on line 721:

721: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 723:

723: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 728:

728: select_index_changed <= '0' when (select_buf_index = select_buf_index_reg)

	Evaluated to	Count	Threshold
Bin	True	46626	1
Bin	False	54283	1

"if" / "when" / "else" condition on line 737:

737: to_integer(unsigned(TIMESTAMP_L_W_ADR(11 downto 2))) when (load_ts_lw_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	50823	1
Bin	False	353285	1

"if" / "when" / "else" condition on line 738:

738: to_integer(unsigned(TIMESTAMP_U_W_ADR(11 downto 2))) when (load_ts_uw_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	53037	1
Bin	False	300248	1

"if" / "when" / "else" condition on line 739:

739: to_integer(unsigned(FRAME_FORMAT_W_ADR(11 downto 2))) when (load_ffmt_w_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	52288	1
Bin	False	247960	1

"if" / "when" / "else" condition on line 740:

740: to_integer(unsigned(IDENTIFIER_W_ADR(11 downto 2))) when (load_ident_w_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	52058	1
Bin	False	195902	1

"if" / "when" / "else" condition on line 741:

741:        to_integer(unsigned(FRAME_TEST_W_ADR(11 downto 2))) when (load_frame_test_w_addr = '1') else

	Evaluated to	Count	Threshold
Bin	True	52644	1
Bin	False	143258	1

"if" / "when" / "else" condition on line 746:

746: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 748:

748: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on lines 756 to 757:

756:    txtb_hw_cmd_unlock <= '1' when (txtb_hw_cmd.valid  = '1' or txtb_hw_cmd.err    = '1' or 
757:                                    txtb_hw_cmd.arbl   = '1' or txtb_hw_cmd.failed = '1')

	Evaluated to	Count	Threshold
Bin	True	25490	1
Bin	False	28692	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Threshold	Excluded due to
Bin	(7)(31)	0	1	1	Exclude file
Bin	(7)(31)	1	0	1	Exclude file
Bin	(7)(30)	0	1	1	Exclude file
Bin	(7)(30)	1	0	1	Exclude file
Bin	(7)(29)	0	1	1	Exclude file
Bin	(7)(29)	1	0	1	Exclude file
Bin	(7)(28)	0	1	1	Exclude file
Bin	(7)(28)	1	0	1	Exclude file
Bin	(7)(27)	0	1	1	Exclude file
Bin	(7)(27)	1	0	1	Exclude file
Bin	(7)(26)	0	1	1	Exclude file
Bin	(7)(26)	1	0	1	Exclude file
Bin	(7)(25)	0	1	1	Exclude file
Bin	(7)(25)	1	0	1	Exclude file
Bin	(7)(24)	0	1	1	Exclude file
Bin	(7)(24)	1	0	1	Exclude file
Bin	(7)(23)	0	1	1	Exclude file
Bin	(7)(23)	1	0	1	Exclude file
Bin	(7)(22)	0	1	1	Exclude file
Bin	(7)(22)	1	0	1	Exclude file
Bin	(7)(21)	0	1	1	Exclude file
Bin	(7)(21)	1	0	1	Exclude file
Bin	(7)(20)	0	1	1	Exclude file
Bin	(7)(20)	1	0	1	Exclude file
Bin	(7)(19)	0	1	1	Exclude file
Bin	(7)(19)	1	0	1	Exclude file
Bin	(7)(18)	0	1	1	Exclude file
Bin	(7)(18)	1	0	1	Exclude file
Bin	(7)(17)	0	1	1	Exclude file
Bin	(7)(17)	1	0	1	Exclude file
Bin	(7)(16)	0	1	1	Exclude file
Bin	(7)(16)	1	0	1	Exclude file
Bin	(7)(15)	0	1	1	Exclude file
Bin	(7)(15)	1	0	1	Exclude file
Bin	(7)(14)	0	1	1	Exclude file
Bin	(7)(14)	1	0	1	Exclude file
Bin	(7)(13)	0	1	1	Exclude file
Bin	(7)(13)	1	0	1	Exclude file
Bin	(7)(12)	0	1	1	Exclude file
Bin	(7)(12)	1	0	1	Exclude file
Bin	(7)(11)	0	1	1	Exclude file
Bin	(7)(11)	1	0	1	Exclude file
Bin	(7)(10)	0	1	1	Exclude file
Bin	(7)(10)	1	0	1	Exclude file
Bin	(7)(9)	0	1	1	Exclude file
Bin	(7)(9)	1	0	1	Exclude file
Bin	(7)(8)	0	1	1	Exclude file
Bin	(7)(8)	1	0	1	Exclude file
Bin	(7)(7)	0	1	1	Exclude file
Bin	(7)(7)	1	0	1	Exclude file
Bin	(7)(6)	0	1	1	Exclude file
Bin	(7)(6)	1	0	1	Exclude file
Bin	(7)(5)	0	1	1	Exclude file
Bin	(7)(5)	1	0	1	Exclude file
Bin	(7)(4)	0	1	1	Exclude file
Bin	(7)(4)	1	0	1	Exclude file
Bin	(7)(3)	0	1	1	Exclude file
Bin	(7)(3)	1	0	1	Exclude file
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(31)	0	1	1	Exclude file
Bin	(6)(31)	1	0	1	Exclude file
Bin	(6)(30)	0	1	1	Exclude file
Bin	(6)(30)	1	0	1	Exclude file
Bin	(6)(29)	0	1	1	Exclude file
Bin	(6)(29)	1	0	1	Exclude file
Bin	(6)(28)	0	1	1	Exclude file
Bin	(6)(28)	1	0	1	Exclude file
Bin	(6)(27)	0	1	1	Exclude file
Bin	(6)(27)	1	0	1	Exclude file
Bin	(6)(26)	0	1	1	Exclude file
Bin	(6)(26)	1	0	1	Exclude file
Bin	(6)(25)	0	1	1	Exclude file
Bin	(6)(25)	1	0	1	Exclude file
Bin	(6)(24)	0	1	1	Exclude file
Bin	(6)(24)	1	0	1	Exclude file
Bin	(6)(23)	0	1	1	Exclude file
Bin	(6)(23)	1	0	1	Exclude file
Bin	(6)(22)	0	1	1	Exclude file
Bin	(6)(22)	1	0	1	Exclude file
Bin	(6)(21)	0	1	1	Exclude file
Bin	(6)(21)	1	0	1	Exclude file
Bin	(6)(20)	0	1	1	Exclude file
Bin	(6)(20)	1	0	1	Exclude file
Bin	(6)(19)	0	1	1	Exclude file
Bin	(6)(19)	1	0	1	Exclude file
Bin	(6)(18)	0	1	1	Exclude file
Bin	(6)(18)	1	0	1	Exclude file
Bin	(6)(17)	0	1	1	Exclude file
Bin	(6)(17)	1	0	1	Exclude file
Bin	(6)(16)	0	1	1	Exclude file
Bin	(6)(16)	1	0	1	Exclude file
Bin	(6)(15)	0	1	1	Exclude file
Bin	(6)(15)	1	0	1	Exclude file
Bin	(6)(14)	0	1	1	Exclude file
Bin	(6)(14)	1	0	1	Exclude file
Bin	(6)(13)	0	1	1	Exclude file
Bin	(6)(13)	1	0	1	Exclude file
Bin	(6)(12)	0	1	1	Exclude file
Bin	(6)(12)	1	0	1	Exclude file
Bin	(6)(11)	0	1	1	Exclude file
Bin	(6)(11)	1	0	1	Exclude file
Bin	(6)(10)	0	1	1	Exclude file
Bin	(6)(10)	1	0	1	Exclude file
Bin	(6)(9)	0	1	1	Exclude file
Bin	(6)(9)	1	0	1	Exclude file
Bin	(6)(8)	0	1	1	Exclude file
Bin	(6)(8)	1	0	1	Exclude file
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Bin	(6)(6)	1	0	1	Exclude file
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Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
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Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
Bin	(5)(31)	0	1	1	Exclude file
Bin	(5)(31)	1	0	1	Exclude file
Bin	(5)(30)	0	1	1	Exclude file
Bin	(5)(30)	1	0	1	Exclude file
Bin	(5)(29)	0	1	1	Exclude file
Bin	(5)(29)	1	0	1	Exclude file
Bin	(5)(28)	0	1	1	Exclude file
Bin	(5)(28)	1	0	1	Exclude file
Bin	(5)(27)	0	1	1	Exclude file
Bin	(5)(27)	1	0	1	Exclude file
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Bin	(5)(26)	1	0	1	Exclude file
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Bin	(5)(21)	0	1	1	Exclude file
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Bin	(5)(9)	1	0	1	Exclude file
Bin	(5)(8)	0	1	1	Exclude file
Bin	(5)(8)	1	0	1	Exclude file
Bin	(5)(7)	0	1	1	Exclude file
Bin	(5)(7)	1	0	1	Exclude file
Bin	(5)(6)	0	1	1	Exclude file
Bin	(5)(6)	1	0	1	Exclude file
Bin	(5)(5)	0	1	1	Exclude file
Bin	(5)(5)	1	0	1	Exclude file
Bin	(5)(4)	0	1	1	Exclude file
Bin	(5)(4)	1	0	1	Exclude file
Bin	(5)(3)	0	1	1	Exclude file
Bin	(5)(3)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(31)	0	1	1	Exclude file
Bin	(4)(31)	1	0	1	Exclude file
Bin	(4)(30)	0	1	1	Exclude file
Bin	(4)(30)	1	0	1	Exclude file
Bin	(4)(29)	0	1	1	Exclude file
Bin	(4)(29)	1	0	1	Exclude file
Bin	(4)(28)	0	1	1	Exclude file
Bin	(4)(28)	1	0	1	Exclude file
Bin	(4)(27)	0	1	1	Exclude file
Bin	(4)(27)	1	0	1	Exclude file
Bin	(4)(26)	0	1	1	Exclude file
Bin	(4)(26)	1	0	1	Exclude file
Bin	(4)(25)	0	1	1	Exclude file
Bin	(4)(25)	1	0	1	Exclude file
Bin	(4)(24)	0	1	1	Exclude file
Bin	(4)(24)	1	0	1	Exclude file
Bin	(4)(23)	0	1	1	Exclude file
Bin	(4)(23)	1	0	1	Exclude file
Bin	(4)(22)	0	1	1	Exclude file
Bin	(4)(22)	1	0	1	Exclude file
Bin	(4)(21)	0	1	1	Exclude file
Bin	(4)(21)	1	0	1	Exclude file
Bin	(4)(20)	0	1	1	Exclude file
Bin	(4)(20)	1	0	1	Exclude file
Bin	(4)(19)	0	1	1	Exclude file
Bin	(4)(19)	1	0	1	Exclude file
Bin	(4)(18)	0	1	1	Exclude file
Bin	(4)(18)	1	0	1	Exclude file
Bin	(4)(17)	0	1	1	Exclude file
Bin	(4)(17)	1	0	1	Exclude file
Bin	(4)(16)	0	1	1	Exclude file
Bin	(4)(16)	1	0	1	Exclude file
Bin	(4)(15)	0	1	1	Exclude file
Bin	(4)(15)	1	0	1	Exclude file
Bin	(4)(14)	0	1	1	Exclude file
Bin	(4)(14)	1	0	1	Exclude file
Bin	(4)(13)	0	1	1	Exclude file
Bin	(4)(13)	1	0	1	Exclude file
Bin	(4)(12)	0	1	1	Exclude file
Bin	(4)(12)	1	0	1	Exclude file
Bin	(4)(11)	0	1	1	Exclude file
Bin	(4)(11)	1	0	1	Exclude file
Bin	(4)(10)	0	1	1	Exclude file
Bin	(4)(10)	1	0	1	Exclude file
Bin	(4)(9)	0	1	1	Exclude file
Bin	(4)(9)	1	0	1	Exclude file
Bin	(4)(8)	0	1	1	Exclude file
Bin	(4)(8)	1	0	1	Exclude file
Bin	(4)(7)	0	1	1	Exclude file
Bin	(4)(7)	1	0	1	Exclude file
Bin	(4)(6)	0	1	1	Exclude file
Bin	(4)(6)	1	0	1	Exclude file
Bin	(4)(5)	0	1	1	Exclude file
Bin	(4)(5)	1	0	1	Exclude file
Bin	(4)(4)	0	1	1	Exclude file
Bin	(4)(4)	1	0	1	Exclude file
Bin	(4)(3)	0	1	1	Exclude file
Bin	(4)(3)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(31)	0	1	1	Exclude file
Bin	(3)(31)	1	0	1	Exclude file
Bin	(3)(30)	0	1	1	Exclude file
Bin	(3)(30)	1	0	1	Exclude file
Bin	(3)(29)	0	1	1	Exclude file
Bin	(3)(29)	1	0	1	Exclude file
Bin	(3)(28)	0	1	1	Exclude file
Bin	(3)(28)	1	0	1	Exclude file
Bin	(3)(27)	0	1	1	Exclude file
Bin	(3)(27)	1	0	1	Exclude file
Bin	(3)(26)	0	1	1	Exclude file
Bin	(3)(26)	1	0	1	Exclude file
Bin	(3)(25)	0	1	1	Exclude file
Bin	(3)(25)	1	0	1	Exclude file
Bin	(3)(24)	0	1	1	Exclude file
Bin	(3)(24)	1	0	1	Exclude file
Bin	(3)(23)	0	1	1	Exclude file
Bin	(3)(23)	1	0	1	Exclude file
Bin	(3)(22)	0	1	1	Exclude file
Bin	(3)(22)	1	0	1	Exclude file
Bin	(3)(21)	0	1	1	Exclude file
Bin	(3)(21)	1	0	1	Exclude file
Bin	(3)(20)	0	1	1	Exclude file
Bin	(3)(20)	1	0	1	Exclude file
Bin	(3)(19)	0	1	1	Exclude file
Bin	(3)(19)	1	0	1	Exclude file
Bin	(3)(18)	0	1	1	Exclude file
Bin	(3)(18)	1	0	1	Exclude file
Bin	(3)(17)	0	1	1	Exclude file
Bin	(3)(17)	1	0	1	Exclude file
Bin	(3)(16)	0	1	1	Exclude file
Bin	(3)(16)	1	0	1	Exclude file
Bin	(3)(15)	0	1	1	Exclude file
Bin	(3)(15)	1	0	1	Exclude file
Bin	(3)(14)	0	1	1	Exclude file
Bin	(3)(14)	1	0	1	Exclude file
Bin	(3)(13)	0	1	1	Exclude file
Bin	(3)(13)	1	0	1	Exclude file
Bin	(3)(12)	0	1	1	Exclude file
Bin	(3)(12)	1	0	1	Exclude file
Bin	(3)(11)	0	1	1	Exclude file
Bin	(3)(11)	1	0	1	Exclude file
Bin	(3)(10)	0	1	1	Exclude file
Bin	(3)(10)	1	0	1	Exclude file
Bin	(3)(9)	0	1	1	Exclude file
Bin	(3)(9)	1	0	1	Exclude file
Bin	(3)(8)	0	1	1	Exclude file
Bin	(3)(8)	1	0	1	Exclude file
Bin	(3)(7)	0	1	1	Exclude file
Bin	(3)(7)	1	0	1	Exclude file
Bin	(3)(6)	0	1	1	Exclude file
Bin	(3)(6)	1	0	1	Exclude file
Bin	(3)(5)	0	1	1	Exclude file
Bin	(3)(5)	1	0	1	Exclude file
Bin	(3)(4)	0	1	1	Exclude file
Bin	(3)(4)	1	0	1	Exclude file
Bin	(3)(3)	0	1	1	Exclude file
Bin	(3)(3)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(31)	0	1	1	Exclude file
Bin	(2)(31)	1	0	1	Exclude file
Bin	(2)(30)	0	1	1	Exclude file
Bin	(2)(30)	1	0	1	Exclude file
Bin	(2)(29)	0	1	1	Exclude file
Bin	(2)(29)	1	0	1	Exclude file
Bin	(2)(28)	0	1	1	Exclude file
Bin	(2)(28)	1	0	1	Exclude file
Bin	(2)(27)	0	1	1	Exclude file
Bin	(2)(27)	1	0	1	Exclude file
Bin	(2)(26)	0	1	1	Exclude file
Bin	(2)(26)	1	0	1	Exclude file
Bin	(2)(25)	0	1	1	Exclude file
Bin	(2)(25)	1	0	1	Exclude file
Bin	(2)(24)	0	1	1	Exclude file
Bin	(2)(24)	1	0	1	Exclude file
Bin	(2)(23)	0	1	1	Exclude file
Bin	(2)(23)	1	0	1	Exclude file
Bin	(2)(22)	0	1	1	Exclude file
Bin	(2)(22)	1	0	1	Exclude file
Bin	(2)(21)	0	1	1	Exclude file
Bin	(2)(21)	1	0	1	Exclude file
Bin	(2)(20)	0	1	1	Exclude file
Bin	(2)(20)	1	0	1	Exclude file
Bin	(2)(19)	0	1	1	Exclude file
Bin	(2)(19)	1	0	1	Exclude file
Bin	(2)(18)	0	1	1	Exclude file
Bin	(2)(18)	1	0	1	Exclude file
Bin	(2)(17)	0	1	1	Exclude file
Bin	(2)(17)	1	0	1	Exclude file
Bin	(2)(16)	0	1	1	Exclude file
Bin	(2)(16)	1	0	1	Exclude file
Bin	(2)(15)	0	1	1	Exclude file
Bin	(2)(15)	1	0	1	Exclude file
Bin	(2)(14)	0	1	1	Exclude file
Bin	(2)(14)	1	0	1	Exclude file
Bin	(2)(13)	0	1	1	Exclude file
Bin	(2)(13)	1	0	1	Exclude file
Bin	(2)(12)	0	1	1	Exclude file
Bin	(2)(12)	1	0	1	Exclude file
Bin	(2)(11)	0	1	1	Exclude file
Bin	(2)(11)	1	0	1	Exclude file
Bin	(2)(10)	0	1	1	Exclude file
Bin	(2)(10)	1	0	1	Exclude file
Bin	(2)(9)	0	1	1	Exclude file
Bin	(2)(9)	1	0	1	Exclude file
Bin	(2)(8)	0	1	1	Exclude file
Bin	(2)(8)	1	0	1	Exclude file
Bin	(2)(7)	0	1	1	Exclude file
Bin	(2)(7)	1	0	1	Exclude file
Bin	(2)(6)	0	1	1	Exclude file
Bin	(2)(6)	1	0	1	Exclude file
Bin	(2)(5)	0	1	1	Exclude file
Bin	(2)(5)	1	0	1	Exclude file
Bin	(2)(4)	0	1	1	Exclude file
Bin	(2)(4)	1	0	1	Exclude file
Bin	(2)(3)	0	1	1	Exclude file
Bin	(2)(3)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(31)	0	1	1	Exclude file
Bin	(1)(31)	1	0	1	Exclude file
Bin	(1)(30)	0	1	1	Exclude file
Bin	(1)(30)	1	0	1	Exclude file
Bin	(1)(29)	0	1	1	Exclude file
Bin	(1)(29)	1	0	1	Exclude file
Bin	(1)(28)	0	1	1	Exclude file
Bin	(1)(28)	1	0	1	Exclude file
Bin	(1)(27)	0	1	1	Exclude file
Bin	(1)(27)	1	0	1	Exclude file
Bin	(1)(26)	0	1	1	Exclude file
Bin	(1)(26)	1	0	1	Exclude file
Bin	(1)(25)	0	1	1	Exclude file
Bin	(1)(25)	1	0	1	Exclude file
Bin	(1)(24)	0	1	1	Exclude file
Bin	(1)(24)	1	0	1	Exclude file
Bin	(1)(23)	0	1	1	Exclude file
Bin	(1)(23)	1	0	1	Exclude file
Bin	(1)(22)	0	1	1	Exclude file
Bin	(1)(22)	1	0	1	Exclude file
Bin	(1)(21)	0	1	1	Exclude file
Bin	(1)(21)	1	0	1	Exclude file
Bin	(1)(20)	0	1	1	Exclude file
Bin	(1)(20)	1	0	1	Exclude file
Bin	(1)(19)	0	1	1	Exclude file
Bin	(1)(19)	1	0	1	Exclude file
Bin	(1)(18)	0	1	1	Exclude file
Bin	(1)(18)	1	0	1	Exclude file
Bin	(1)(17)	0	1	1	Exclude file
Bin	(1)(17)	1	0	1	Exclude file
Bin	(1)(16)	0	1	1	Exclude file
Bin	(1)(16)	1	0	1	Exclude file
Bin	(1)(15)	0	1	1	Exclude file
Bin	(1)(15)	1	0	1	Exclude file
Bin	(1)(14)	0	1	1	Exclude file
Bin	(1)(14)	1	0	1	Exclude file
Bin	(1)(13)	0	1	1	Exclude file
Bin	(1)(13)	1	0	1	Exclude file
Bin	(1)(12)	0	1	1	Exclude file
Bin	(1)(12)	1	0	1	Exclude file
Bin	(1)(11)	0	1	1	Exclude file
Bin	(1)(11)	1	0	1	Exclude file
Bin	(1)(10)	0	1	1	Exclude file
Bin	(1)(10)	1	0	1	Exclude file
Bin	(1)(9)	0	1	1	Exclude file
Bin	(1)(9)	1	0	1	Exclude file
Bin	(1)(8)	0	1	1	Exclude file
Bin	(1)(8)	1	0	1	Exclude file
Bin	(1)(7)	0	1	1	Exclude file
Bin	(1)(7)	1	0	1	Exclude file
Bin	(1)(6)	0	1	1	Exclude file
Bin	(1)(6)	1	0	1	Exclude file
Bin	(1)(5)	0	1	1	Exclude file
Bin	(1)(5)	1	0	1	Exclude file
Bin	(1)(4)	0	1	1	Exclude file
Bin	(1)(4)	1	0	1	Exclude file
Bin	(1)(3)	0	1	1	Exclude file
Bin	(1)(3)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(31)	0	1	1	Exclude file
Bin	(0)(31)	1	0	1	Exclude file
Bin	(0)(30)	0	1	1	Exclude file
Bin	(0)(30)	1	0	1	Exclude file
Bin	(0)(29)	0	1	1	Exclude file
Bin	(0)(29)	1	0	1	Exclude file
Bin	(0)(28)	0	1	1	Exclude file
Bin	(0)(28)	1	0	1	Exclude file
Bin	(0)(27)	0	1	1	Exclude file
Bin	(0)(27)	1	0	1	Exclude file
Bin	(0)(26)	0	1	1	Exclude file
Bin	(0)(26)	1	0	1	Exclude file
Bin	(0)(25)	0	1	1	Exclude file
Bin	(0)(25)	1	0	1	Exclude file
Bin	(0)(24)	0	1	1	Exclude file
Bin	(0)(24)	1	0	1	Exclude file
Bin	(0)(23)	0	1	1	Exclude file
Bin	(0)(23)	1	0	1	Exclude file
Bin	(0)(22)	0	1	1	Exclude file
Bin	(0)(22)	1	0	1	Exclude file
Bin	(0)(21)	0	1	1	Exclude file
Bin	(0)(21)	1	0	1	Exclude file
Bin	(0)(20)	0	1	1	Exclude file
Bin	(0)(20)	1	0	1	Exclude file
Bin	(0)(19)	0	1	1	Exclude file
Bin	(0)(19)	1	0	1	Exclude file
Bin	(0)(18)	0	1	1	Exclude file
Bin	(0)(18)	1	0	1	Exclude file
Bin	(0)(17)	0	1	1	Exclude file
Bin	(0)(17)	1	0	1	Exclude file
Bin	(0)(16)	0	1	1	Exclude file
Bin	(0)(16)	1	0	1	Exclude file
Bin	(0)(15)	0	1	1	Exclude file
Bin	(0)(15)	1	0	1	Exclude file
Bin	(0)(14)	0	1	1	Exclude file
Bin	(0)(14)	1	0	1	Exclude file
Bin	(0)(13)	0	1	1	Exclude file
Bin	(0)(13)	1	0	1	Exclude file
Bin	(0)(12)	0	1	1	Exclude file
Bin	(0)(12)	1	0	1	Exclude file
Bin	(0)(11)	0	1	1	Exclude file
Bin	(0)(11)	1	0	1	Exclude file
Bin	(0)(10)	0	1	1	Exclude file
Bin	(0)(10)	1	0	1	Exclude file
Bin	(0)(9)	0	1	1	Exclude file
Bin	(0)(9)	1	0	1	Exclude file
Bin	(0)(8)	0	1	1	Exclude file
Bin	(0)(8)	1	0	1	Exclude file
Bin	(0)(7)	0	1	1	Exclude file
Bin	(0)(7)	1	0	1	Exclude file
Bin	(0)(6)	0	1	1	Exclude file
Bin	(0)(6)	1	0	1	Exclude file
Bin	(0)(5)	0	1	1	Exclude file
Bin	(0)(5)	1	0	1	Exclude file
Bin	(0)(4)	0	1	1	Exclude file
Bin	(0)(4)	1	0	1	Exclude file
Bin	(0)(3)	0	1	1	Exclude file
Bin	(0)(3)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

TXTB_AVAILABLE

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_ALLOW_BB

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PARITY_MISMATCH

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TTTM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_PRIORITY

	Element	From	To	Threshold	Excluded due to
Bin	(7)(2)	0	1	1	Exclude file
Bin	(7)(2)	1	0	1	Exclude file
Bin	(7)(1)	0	1	1	Exclude file
Bin	(7)(1)	1	0	1	Exclude file
Bin	(7)(0)	0	1	1	Exclude file
Bin	(7)(0)	1	0	1	Exclude file
Bin	(6)(2)	0	1	1	Exclude file
Bin	(6)(2)	1	0	1	Exclude file
Bin	(6)(1)	0	1	1	Exclude file
Bin	(6)(1)	1	0	1	Exclude file
Bin	(6)(0)	0	1	1	Exclude file
Bin	(6)(0)	1	0	1	Exclude file
Bin	(5)(2)	0	1	1	Exclude file
Bin	(5)(2)	1	0	1	Exclude file
Bin	(5)(1)	0	1	1	Exclude file
Bin	(5)(1)	1	0	1	Exclude file
Bin	(5)(0)	0	1	1	Exclude file
Bin	(5)(0)	1	0	1	Exclude file
Bin	(4)(2)	0	1	1	Exclude file
Bin	(4)(2)	1	0	1	Exclude file
Bin	(4)(1)	0	1	1	Exclude file
Bin	(4)(1)	1	0	1	Exclude file
Bin	(4)(0)	0	1	1	Exclude file
Bin	(4)(0)	1	0	1	Exclude file
Bin	(3)(2)	0	1	1	Exclude file
Bin	(3)(2)	1	0	1	Exclude file
Bin	(3)(1)	0	1	1	Exclude file
Bin	(3)(1)	1	0	1	Exclude file
Bin	(3)(0)	0	1	1	Exclude file
Bin	(3)(0)	1	0	1	Exclude file
Bin	(2)(2)	0	1	1	Exclude file
Bin	(2)(2)	1	0	1	Exclude file
Bin	(2)(1)	0	1	1	Exclude file
Bin	(2)(1)	1	0	1	Exclude file
Bin	(2)(0)	0	1	1	Exclude file
Bin	(2)(0)	1	0	1	Exclude file
Bin	(1)(2)	0	1	1	Exclude file
Bin	(1)(2)	1	0	1	Exclude file
Bin	(1)(1)	0	1	1	Exclude file
Bin	(1)(1)	1	0	1	Exclude file
Bin	(1)(0)	0	1	1	Exclude file
Bin	(1)(0)	1	0	1	Exclude file
Bin	(0)(2)	0	1	1	Exclude file
Bin	(0)(2)	1	0	1	Exclude file
Bin	(0)(1)	0	1	1	Exclude file
Bin	(0)(1)	1	0	1	Exclude file
Bin	(0)(0)	0	1	1	Exclude file
Bin	(0)(0)	1	0	1	Exclude file

Port:

TIMESTAMP

	Element	From	To	Threshold	Excluded due to
Bin	(63)	0	1	1	Exclude file
Bin	(63)	1	0	1	Exclude file
Bin	(62)	0	1	1	Exclude file
Bin	(62)	1	0	1	Exclude file
Bin	(61)	0	1	1	Exclude file
Bin	(61)	1	0	1	Exclude file
Bin	(60)	0	1	1	Exclude file
Bin	(60)	1	0	1	Exclude file
Bin	(59)	0	1	1	Exclude file
Bin	(59)	1	0	1	Exclude file
Bin	(58)	0	1	1	Exclude file
Bin	(58)	1	0	1	Exclude file
Bin	(57)	0	1	1	Exclude file
Bin	(57)	1	0	1	Exclude file
Bin	(56)	0	1	1	Exclude file
Bin	(56)	1	0	1	Exclude file
Bin	(55)	0	1	1	Exclude file
Bin	(55)	1	0	1	Exclude file
Bin	(54)	0	1	1	Exclude file
Bin	(54)	1	0	1	Exclude file
Bin	(53)	0	1	1	Exclude file
Bin	(53)	1	0	1	Exclude file
Bin	(52)	0	1	1	Exclude file
Bin	(52)	1	0	1	Exclude file
Bin	(51)	0	1	1	Exclude file
Bin	(51)	1	0	1	Exclude file
Bin	(50)	0	1	1	Exclude file
Bin	(50)	1	0	1	Exclude file
Bin	(49)	0	1	1	Exclude file
Bin	(49)	1	0	1	Exclude file
Bin	(48)	0	1	1	Exclude file
Bin	(48)	1	0	1	Exclude file
Bin	(47)	0	1	1	Exclude file
Bin	(47)	1	0	1	Exclude file
Bin	(46)	0	1	1	Exclude file
Bin	(46)	1	0	1	Exclude file
Bin	(45)	0	1	1	Exclude file
Bin	(45)	1	0	1	Exclude file
Bin	(44)	0	1	1	Exclude file
Bin	(44)	1	0	1	Exclude file
Bin	(43)	0	1	1	Exclude file
Bin	(43)	1	0	1	Exclude file
Bin	(42)	0	1	1	Exclude file
Bin	(42)	1	0	1	Exclude file
Bin	(41)	0	1	1	Exclude file
Bin	(41)	1	0	1	Exclude file
Bin	(40)	0	1	1	Exclude file
Bin	(40)	1	0	1	Exclude file
Bin	(39)	0	1	1	Exclude file
Bin	(39)	1	0	1	Exclude file
Bin	(38)	0	1	1	Exclude file
Bin	(38)	1	0	1	Exclude file
Bin	(37)	0	1	1	Exclude file
Bin	(37)	1	0	1	Exclude file
Bin	(36)	0	1	1	Exclude file
Bin	(36)	1	0	1	Exclude file
Bin	(35)	0	1	1	Exclude file
Bin	(35)	1	0	1	Exclude file
Bin	(34)	0	1	1	Exclude file
Bin	(34)	1	0	1	Exclude file
Bin	(33)	0	1	1	Exclude file
Bin	(33)	1	0	1	Exclude file
Bin	(32)	0	1	1	Exclude file
Bin	(32)	1	0	1	Exclude file
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold
Bin	(4)	0	1	27463	1
Bin	(4)	1	0	29064	1
Bin	(3)	0	1	4010	1
Bin	(3)	1	0	5611	1
Bin	(2)	0	1	47158	1
Bin	(2)	1	0	48759	1
Bin	(1)	0	1	38295	1
Bin	(1)	1	0	38298	1
Bin	(0)	0	1	103594	1
Bin	(0)	1	0	105192	1

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold
Bin	0	1	107454	1
Bin	1	0	109055	1

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold
Bin	0	1	185711	1
Bin	1	0	187312	1

Port:

TXTB_IS_BB

	Element	From	To	Count	Threshold
Bin	(3)	0	1	7	1
Bin	(3)	1	0	236	1
Bin	(2)	0	1	11	1
Bin	(2)	1	0	232	1
Bin	(1)	0	1	36	1
Bin	(1)	1	0	886	1
Bin	(0)	0	1	89	1
Bin	(0)	1	0	1798	1

Port:

TRAN_WORD

	Element	From	To	Count	Threshold
Bin	(31)	0	1	10387	1
Bin	(31)	1	0	27360	1
Bin	(30)	0	1	10685	1
Bin	(30)	1	0	26144	1
Bin	(29)	0	1	10089	1
Bin	(29)	1	0	25792	1
Bin	(28)	0	1	26430	1
Bin	(28)	1	0	68315	1
Bin	(27)	0	1	21991	1
Bin	(27)	1	0	56789	1
Bin	(26)	0	1	26938	1
Bin	(26)	1	0	68845	1
Bin	(25)	0	1	23263	1
Bin	(25)	1	0	60615	1
Bin	(24)	0	1	27764	1
Bin	(24)	1	0	69735	1
Bin	(23)	0	1	24621	1
Bin	(23)	1	0	58550	1
Bin	(22)	0	1	26701	1
Bin	(22)	1	0	67341	1
Bin	(21)	0	1	24872	1
Bin	(21)	1	0	60971	1
Bin	(20)	0	1	26469	1
Bin	(20)	1	0	66414	1
Bin	(19)	0	1	24512	1
Bin	(19)	1	0	59826	1
Bin	(18)	0	1	27778	1
Bin	(18)	1	0	66619	1
Bin	(17)	0	1	16891	1
Bin	(17)	1	0	39819	1
Bin	(16)	0	1	17493	1
Bin	(16)	1	0	39188	1
Bin	(15)	0	1	17281	1
Bin	(15)	1	0	60097	1
Bin	(14)	0	1	17336	1
Bin	(14)	1	0	59761	1
Bin	(13)	0	1	16872	1
Bin	(13)	1	0	59268	1
Bin	(12)	0	1	16888	1
Bin	(12)	1	0	58693	1
Bin	(11)	0	1	17668	1
Bin	(11)	1	0	58921	1
Bin	(10)	0	1	19444	1
Bin	(10)	1	0	63616	1
Bin	(9)	0	1	28357	1
Bin	(9)	1	0	75504	1
Bin	(8)	0	1	18089	1
Bin	(8)	1	0	62077	1
Bin	(7)	0	1	36386	1
Bin	(7)	1	0	46720	1
Bin	(6)	0	1	28539	1
Bin	(6)	1	0	35209	1
Bin	(5)	0	1	21141	1
Bin	(5)	1	0	29254	1
Bin	(4)	0	1	18334	1
Bin	(4)	1	0	23579	1
Bin	(3)	0	1	27223	1
Bin	(3)	1	0	34686	1
Bin	(2)	0	1	29043	1
Bin	(2)	1	0	36792	1
Bin	(1)	0	1	29198	1
Bin	(1)	1	0	36820	1
Bin	(0)	0	1	36332	1
Bin	(0)	1	0	45841	1

Port:

TRAN_DLC

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1496	1
Bin	(3)	1	0	3096	1
Bin	(2)	0	1	1955	1
Bin	(2)	1	0	3555	1
Bin	(1)	0	1	1908	1
Bin	(1)	1	0	3509	1
Bin	(0)	0	1	3563	1
Bin	(0)	1	0	5164	1

Port:

TRAN_IS_RTR

	From	To	Count	Threshold
Bin	0	1	1173	1
Bin	1	0	2772	1

Port:

TRAN_IDENT_TYPE

	From	To	Count	Threshold
Bin	0	1	2562	1
Bin	1	0	4163	1

Port:

TRAN_FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	2713	1
Bin	1	0	4314	1

Port:

TRAN_BRS

	From	To	Count	Threshold
Bin	0	1	2011	1
Bin	1	0	3612	1

Port:

TRAN_IDENTIFIER

	Element	From	To	Count	Threshold
Bin	(28)	0	1	3924	1
Bin	(28)	1	0	5475	1
Bin	(27)	0	1	3883	1
Bin	(27)	1	0	5516	1
Bin	(26)	0	1	3870	1
Bin	(26)	1	0	5418	1
Bin	(25)	0	1	4127	1
Bin	(25)	1	0	5750	1
Bin	(24)	0	1	3960	1
Bin	(24)	1	0	5498	1
Bin	(23)	0	1	4124	1
Bin	(23)	1	0	5749	1
Bin	(22)	0	1	3814	1
Bin	(22)	1	0	5444	1
Bin	(21)	0	1	4199	1
Bin	(21)	1	0	5759	1
Bin	(20)	0	1	3869	1
Bin	(20)	1	0	5501	1
Bin	(19)	0	1	4219	1
Bin	(19)	1	0	5772	1
Bin	(18)	0	1	3822	1
Bin	(18)	1	0	5451	1
Bin	(17)	0	1	1754	1
Bin	(17)	1	0	9592	1
Bin	(16)	0	1	1740	1
Bin	(16)	1	0	9640	1
Bin	(15)	0	1	1754	1
Bin	(15)	1	0	9659	1
Bin	(14)	0	1	1697	1
Bin	(14)	1	0	9664	1
Bin	(13)	0	1	1711	1
Bin	(13)	1	0	9576	1
Bin	(12)	0	1	1663	1
Bin	(12)	1	0	9481	1
Bin	(11)	0	1	1734	1
Bin	(11)	1	0	9563	1
Bin	(10)	0	1	1663	1
Bin	(10)	1	0	9394	1
Bin	(9)	0	1	1725	1
Bin	(9)	1	0	9518	1
Bin	(8)	0	1	1705	1
Bin	(8)	1	0	9495	1
Bin	(7)	0	1	1775	1
Bin	(7)	1	0	9568	1
Bin	(6)	0	1	1740	1
Bin	(6)	1	0	9640	1
Bin	(5)	0	1	1751	1
Bin	(5)	1	0	9583	1
Bin	(4)	0	1	1736	1
Bin	(4)	1	0	9633	1
Bin	(3)	0	1	1753	1
Bin	(3)	1	0	9554	1
Bin	(2)	0	1	1733	1
Bin	(2)	1	0	9512	1
Bin	(1)	0	1	1754	1
Bin	(1)	1	0	9637	1
Bin	(0)	0	1	1726	1
Bin	(0)	1	0	9541	1

Port:

TRAN_FRAME_TEST

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	58	1
Bin	TPRM(4)	1	0	3273	1
Bin	TPRM(3)	0	1	189	1
Bin	TPRM(3)	1	0	1838	1
Bin	TPRM(2)	0	1	209	1
Bin	TPRM(2)	1	0	1858	1
Bin	TPRM(1)	0	1	431	1
Bin	TPRM(1)	1	0	2080	1
Bin	TPRM(0)	0	1	653	1
Bin	TPRM(0)	1	0	2302	1

Port:

TRAN_FRAME_VALID

	From	To	Count	Threshold
Bin	0	1	25746	1
Bin	1	0	27347	1

Port:

TRAN_FRAME_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	699	1
Bin	1	0	2300	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	25501	1
Bin	LOCK	1	0	27102	1
Bin	VALID	0	1	11115	1
Bin	VALID	1	0	12716	1
Bin	ERR	0	1	4269	1
Bin	ERR	1	0	5870	1
Bin	ARBL	0	1	455	1
Bin	ARBL	1	0	2056	1
Bin	FAILED	0	1	9651	1
Bin	FAILED	1	0	11252	1

Port:

TXTB_CHANGED

	From	To	Count	Threshold
Bin	0	1	9992	1
Bin	1	0	11593	1

Port:

TXTB_HW_CMD_CS

	Element	From	To	Count	Threshold
Bin	(7)	0	1	74	1
Bin	(7)	1	0	856	1
Bin	(6)	0	1	72	1
Bin	(6)	1	0	858	1
Bin	(5)	0	1	70	1
Bin	(5)	1	0	860	1
Bin	(4)	0	1	77	1
Bin	(4)	1	0	853	1
Bin	(3)	0	1	369	1
Bin	(3)	1	0	2707	1
Bin	(2)	0	1	293	1
Bin	(2)	1	0	2783	1
Bin	(1)	0	1	5599	1
Bin	(1)	1	0	8348	1
Bin	(0)	0	1	7393	1
Bin	(0)	1	0	6554	1

Port:

CURR_TXTB_INDEX

	Element	From	To	Count	Threshold
Bin	(2)	0	1	117	1
Bin	(2)	1	0	1718	1
Bin	(1)	0	1	520	1
Bin	(1)	1	0	2121	1
Bin	(0)	0	1	6016	1
Bin	(0)	1	0	7617	1

Signal:

SELECT_BUF_AVAIL

	From	To	Count	Threshold
Bin	0	1	27203	1
Bin	1	0	28804	1

Signal:

TXTB_SELECTED_INPUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8701	1
Bin	(31)	1	0	10302	1
Bin	(30)	0	1	8651	1
Bin	(30)	1	0	10252	1
Bin	(29)	0	1	8418	1
Bin	(29)	1	0	10019	1
Bin	(28)	0	1	26185	1
Bin	(28)	1	0	27786	1
Bin	(27)	0	1	20423	1
Bin	(27)	1	0	22024	1
Bin	(26)	0	1	26634	1
Bin	(26)	1	0	28235	1
Bin	(25)	0	1	21726	1
Bin	(25)	1	0	23327	1
Bin	(24)	0	1	27533	1
Bin	(24)	1	0	29134	1
Bin	(23)	0	1	23084	1
Bin	(23)	1	0	24685	1
Bin	(22)	0	1	26541	1
Bin	(22)	1	0	28142	1
Bin	(21)	0	1	23341	1
Bin	(21)	1	0	24942	1
Bin	(20)	0	1	26369	1
Bin	(20)	1	0	27970	1
Bin	(19)	0	1	22949	1
Bin	(19)	1	0	24550	1
Bin	(18)	0	1	27560	1
Bin	(18)	1	0	29161	1
Bin	(17)	0	1	15363	1
Bin	(17)	1	0	16964	1
Bin	(16)	0	1	15654	1
Bin	(16)	1	0	17255	1
Bin	(15)	0	1	15609	1
Bin	(15)	1	0	17210	1
Bin	(14)	0	1	15444	1
Bin	(14)	1	0	17045	1
Bin	(13)	0	1	15185	1
Bin	(13)	1	0	16786	1
Bin	(12)	0	1	15097	1
Bin	(12)	1	0	16698	1
Bin	(11)	0	1	16120	1
Bin	(11)	1	0	17721	1
Bin	(10)	0	1	17647	1
Bin	(10)	1	0	19248	1
Bin	(9)	0	1	26763	1
Bin	(9)	1	0	28364	1
Bin	(8)	0	1	16193	1
Bin	(8)	1	0	17794	1
Bin	(7)	0	1	36273	1
Bin	(7)	1	0	37874	1
Bin	(6)	0	1	28429	1
Bin	(6)	1	0	30030	1
Bin	(5)	0	1	21116	1
Bin	(5)	1	0	22717	1
Bin	(4)	0	1	18302	1
Bin	(4)	1	0	19903	1
Bin	(3)	0	1	27203	1
Bin	(3)	1	0	28804	1
Bin	(2)	0	1	28957	1
Bin	(2)	1	0	30558	1
Bin	(1)	0	1	29125	1
Bin	(1)	1	0	30726	1
Bin	(0)	0	1	36252	1
Bin	(0)	1	0	37853	1

Signal:

TXTB_TIMESTAMP

	Element	From	To	Count	Threshold
Bin	(63)	0	1	8701	1
Bin	(63)	1	0	10302	1
Bin	(62)	0	1	8651	1
Bin	(62)	1	0	10252	1
Bin	(61)	0	1	8418	1
Bin	(61)	1	0	10019	1
Bin	(60)	0	1	26185	1
Bin	(60)	1	0	27786	1
Bin	(59)	0	1	20423	1
Bin	(59)	1	0	22024	1
Bin	(58)	0	1	26634	1
Bin	(58)	1	0	28235	1
Bin	(57)	0	1	21726	1
Bin	(57)	1	0	23327	1
Bin	(56)	0	1	27533	1
Bin	(56)	1	0	29134	1
Bin	(55)	0	1	23084	1
Bin	(55)	1	0	24685	1
Bin	(54)	0	1	26541	1
Bin	(54)	1	0	28142	1
Bin	(53)	0	1	23341	1
Bin	(53)	1	0	24942	1
Bin	(52)	0	1	26369	1
Bin	(52)	1	0	27970	1
Bin	(51)	0	1	22949	1
Bin	(51)	1	0	24550	1
Bin	(50)	0	1	27560	1
Bin	(50)	1	0	29161	1
Bin	(49)	0	1	15363	1
Bin	(49)	1	0	16964	1
Bin	(48)	0	1	15654	1
Bin	(48)	1	0	17255	1
Bin	(47)	0	1	15609	1
Bin	(47)	1	0	17210	1
Bin	(46)	0	1	15444	1
Bin	(46)	1	0	17045	1
Bin	(45)	0	1	15185	1
Bin	(45)	1	0	16786	1
Bin	(44)	0	1	15097	1
Bin	(44)	1	0	16698	1
Bin	(43)	0	1	16120	1
Bin	(43)	1	0	17721	1
Bin	(42)	0	1	17647	1
Bin	(42)	1	0	19248	1
Bin	(41)	0	1	26763	1
Bin	(41)	1	0	28364	1
Bin	(40)	0	1	16193	1
Bin	(40)	1	0	17794	1
Bin	(39)	0	1	36273	1
Bin	(39)	1	0	37874	1
Bin	(38)	0	1	28429	1
Bin	(38)	1	0	30030	1
Bin	(37)	0	1	21116	1
Bin	(37)	1	0	22717	1
Bin	(36)	0	1	18302	1
Bin	(36)	1	0	19903	1
Bin	(35)	0	1	27203	1
Bin	(35)	1	0	28804	1
Bin	(34)	0	1	28957	1
Bin	(34)	1	0	30558	1
Bin	(33)	0	1	29125	1
Bin	(33)	1	0	30726	1
Bin	(32)	0	1	36252	1
Bin	(32)	1	0	37853	1
Bin	(31)	0	1	14	1
Bin	(31)	1	0	1615	1
Bin	(30)	0	1	13	1
Bin	(30)	1	0	1614	1
Bin	(29)	0	1	13	1
Bin	(29)	1	0	1614	1
Bin	(28)	0	1	18	1
Bin	(28)	1	0	1619	1
Bin	(27)	0	1	22	1
Bin	(27)	1	0	1623	1
Bin	(26)	0	1	17	1
Bin	(26)	1	0	1618	1
Bin	(25)	0	1	20	1
Bin	(25)	1	0	1621	1
Bin	(24)	0	1	13	1
Bin	(24)	1	0	1614	1
Bin	(23)	0	1	18	1
Bin	(23)	1	0	1619	1
Bin	(22)	0	1	14	1
Bin	(22)	1	0	1615	1
Bin	(21)	0	1	14	1
Bin	(21)	1	0	1615	1
Bin	(20)	0	1	15	1
Bin	(20)	1	0	1616	1
Bin	(19)	0	1	19	1
Bin	(19)	1	0	1620	1
Bin	(18)	0	1	14	1
Bin	(18)	1	0	1615	1
Bin	(17)	0	1	23	1
Bin	(17)	1	0	1624	1
Bin	(16)	0	1	17	1
Bin	(16)	1	0	1618	1
Bin	(15)	0	1	18	1
Bin	(15)	1	0	1619	1
Bin	(14)	0	1	30	1
Bin	(14)	1	0	1631	1
Bin	(13)	0	1	53	1
Bin	(13)	1	0	1654	1
Bin	(12)	0	1	70	1
Bin	(12)	1	0	1671	1
Bin	(11)	0	1	59	1
Bin	(11)	1	0	1660	1
Bin	(10)	0	1	72	1
Bin	(10)	1	0	1673	1
Bin	(9)	0	1	65	1
Bin	(9)	1	0	1666	1
Bin	(8)	0	1	51	1
Bin	(8)	1	0	1652	1
Bin	(7)	0	1	56	1
Bin	(7)	1	0	1657	1
Bin	(6)	0	1	78	1
Bin	(6)	1	0	1679	1
Bin	(5)	0	1	56	1
Bin	(5)	1	0	1657	1
Bin	(4)	0	1	63	1
Bin	(4)	1	0	1664	1
Bin	(3)	0	1	78	1
Bin	(3)	1	0	1679	1
Bin	(2)	0	1	56	1
Bin	(2)	1	0	1657	1
Bin	(1)	0	1	52	1
Bin	(1)	1	0	1653	1
Bin	(0)	0	1	54	1
Bin	(0)	1	0	1655	1

Signal:

TIMESTAMP_VALID

	From	To	Count	Threshold
Bin	0	1	1813	1
Bin	1	0	212	1

Signal:

SELECT_INDEX_CHANGED

	From	To	Count	Threshold
Bin	0	1	46615	1
Bin	1	0	46626	1

Signal:

VALIDATED_BUFFER

	From	To	Count	Threshold
Bin	0	1	25723	1
Bin	1	0	27324	1

Signal:

TXTB_CLK_EN_Q

	From	To	Count	Threshold
Bin	0	1	80871	1
Bin	1	0	82472	1

Signal:

TX_ARB_PARITY_CHECK_VALID

	From	To	Count	Threshold
Bin	0	1	104840	1
Bin	1	0	106441	1

Signal:

TS_LOW_INTERNAL

	Element	From	To	Count	Threshold
Bin	(31)	0	1	14	1
Bin	(31)	1	0	1615	1
Bin	(30)	0	1	13	1
Bin	(30)	1	0	1614	1
Bin	(29)	0	1	13	1
Bin	(29)	1	0	1614	1
Bin	(28)	0	1	18	1
Bin	(28)	1	0	1619	1
Bin	(27)	0	1	22	1
Bin	(27)	1	0	1623	1
Bin	(26)	0	1	17	1
Bin	(26)	1	0	1618	1
Bin	(25)	0	1	20	1
Bin	(25)	1	0	1621	1
Bin	(24)	0	1	13	1
Bin	(24)	1	0	1614	1
Bin	(23)	0	1	18	1
Bin	(23)	1	0	1619	1
Bin	(22)	0	1	14	1
Bin	(22)	1	0	1615	1
Bin	(21)	0	1	14	1
Bin	(21)	1	0	1615	1
Bin	(20)	0	1	15	1
Bin	(20)	1	0	1616	1
Bin	(19)	0	1	19	1
Bin	(19)	1	0	1620	1
Bin	(18)	0	1	14	1
Bin	(18)	1	0	1615	1
Bin	(17)	0	1	23	1
Bin	(17)	1	0	1624	1
Bin	(16)	0	1	17	1
Bin	(16)	1	0	1618	1
Bin	(15)	0	1	18	1
Bin	(15)	1	0	1619	1
Bin	(14)	0	1	30	1
Bin	(14)	1	0	1631	1
Bin	(13)	0	1	53	1
Bin	(13)	1	0	1654	1
Bin	(12)	0	1	70	1
Bin	(12)	1	0	1671	1
Bin	(11)	0	1	59	1
Bin	(11)	1	0	1660	1
Bin	(10)	0	1	72	1
Bin	(10)	1	0	1673	1
Bin	(9)	0	1	65	1
Bin	(9)	1	0	1666	1
Bin	(8)	0	1	51	1
Bin	(8)	1	0	1652	1
Bin	(7)	0	1	56	1
Bin	(7)	1	0	1657	1
Bin	(6)	0	1	78	1
Bin	(6)	1	0	1679	1
Bin	(5)	0	1	56	1
Bin	(5)	1	0	1657	1
Bin	(4)	0	1	63	1
Bin	(4)	1	0	1664	1
Bin	(3)	0	1	78	1
Bin	(3)	1	0	1679	1
Bin	(2)	0	1	56	1
Bin	(2)	1	0	1657	1
Bin	(1)	0	1	52	1
Bin	(1)	1	0	1653	1
Bin	(0)	0	1	54	1
Bin	(0)	1	0	1655	1

Signal:

TRAN_DLC_DBL_BUF

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1512	1
Bin	(3)	1	0	3112	1
Bin	(2)	0	1	1978	1
Bin	(2)	1	0	3578	1
Bin	(1)	0	1	1928	1
Bin	(1)	1	0	3529	1
Bin	(0)	0	1	3584	1
Bin	(0)	1	0	5185	1

Signal:

TRAN_IS_RTR_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	1195	1
Bin	1	0	2794	1

Signal:

TRAN_IDENT_TYPE_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	2586	1
Bin	1	0	4187	1

Signal:

TRAN_FRAME_TYPE_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	2741	1
Bin	1	0	4342	1

Signal:

TRAN_BRS_DBL_BUF

	From	To	Count	Threshold
Bin	0	1	2034	1
Bin	1	0	3635	1

Signal:

TRAN_FRAME_TEST_DBL_BUF

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	50	1
Bin	TPRM(4)	1	0	1651	1
Bin	TPRM(3)	0	1	189	1
Bin	TPRM(3)	1	0	1790	1
Bin	TPRM(2)	0	1	209	1
Bin	TPRM(2)	1	0	1810	1
Bin	TPRM(1)	0	1	431	1
Bin	TPRM(1)	1	0	2032	1
Bin	TPRM(0)	0	1	653	1
Bin	TPRM(0)	1	0	2254	1

Signal:

TRAN_DLC_COM

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1496	1
Bin	(3)	1	0	3096	1
Bin	(2)	0	1	1955	1
Bin	(2)	1	0	3555	1
Bin	(1)	0	1	1908	1
Bin	(1)	1	0	3509	1
Bin	(0)	0	1	3563	1
Bin	(0)	1	0	5164	1

Signal:

TRAN_IS_RTR_COM

	From	To	Count	Threshold
Bin	0	1	1173	1
Bin	1	0	2772	1

Signal:

TRAN_IDENT_TYPE_COM

	From	To	Count	Threshold
Bin	0	1	2562	1
Bin	1	0	4163	1

Signal:

TRAN_FRAME_TYPE_COM

	From	To	Count	Threshold
Bin	0	1	2713	1
Bin	1	0	4314	1

Signal:

TRAN_BRS_COM

	From	To	Count	Threshold
Bin	0	1	2011	1
Bin	1	0	3612	1

Signal:

TRAN_FRAME_VALID_COM

	From	To	Count	Threshold
Bin	0	1	25718	1
Bin	1	0	27319	1

Signal:

TRAN_IDENTIFIER_COM

	Element	From	To	Count	Threshold
Bin	(28)	0	1	3839	1
Bin	(28)	1	0	5438	1
Bin	(27)	0	1	3881	1
Bin	(27)	1	0	5482	1
Bin	(26)	0	1	3779	1
Bin	(26)	1	0	5379	1
Bin	(25)	0	1	4116	1
Bin	(25)	1	0	5715	1
Bin	(24)	0	1	3866	1
Bin	(24)	1	0	5466	1
Bin	(23)	0	1	4114	1
Bin	(23)	1	0	5714	1
Bin	(22)	0	1	3807	1
Bin	(22)	1	0	5406	1
Bin	(21)	0	1	4112	1
Bin	(21)	1	0	5710	1
Bin	(20)	0	1	3866	1
Bin	(20)	1	0	5466	1
Bin	(19)	0	1	4130	1
Bin	(19)	1	0	5729	1
Bin	(18)	0	1	3817	1
Bin	(18)	1	0	5415	1
Bin	(17)	0	1	1749	1
Bin	(17)	1	0	3350	1
Bin	(16)	0	1	1735	1
Bin	(16)	1	0	3336	1
Bin	(15)	0	1	1750	1
Bin	(15)	1	0	3351	1
Bin	(14)	0	1	1697	1
Bin	(14)	1	0	3298	1
Bin	(13)	0	1	1711	1
Bin	(13)	1	0	3312	1
Bin	(12)	0	1	1662	1
Bin	(12)	1	0	3263	1
Bin	(11)	0	1	1733	1
Bin	(11)	1	0	3334	1
Bin	(10)	0	1	1658	1
Bin	(10)	1	0	3259	1
Bin	(9)	0	1	1721	1
Bin	(9)	1	0	3322	1
Bin	(8)	0	1	1700	1
Bin	(8)	1	0	3301	1
Bin	(7)	0	1	1770	1
Bin	(7)	1	0	3371	1
Bin	(6)	0	1	1740	1
Bin	(6)	1	0	3341	1
Bin	(5)	0	1	1750	1
Bin	(5)	1	0	3351	1
Bin	(4)	0	1	1735	1
Bin	(4)	1	0	3336	1
Bin	(3)	0	1	1753	1
Bin	(3)	1	0	3354	1
Bin	(2)	0	1	1727	1
Bin	(2)	1	0	3328	1
Bin	(1)	0	1	1749	1
Bin	(1)	1	0	3350	1
Bin	(0)	0	1	1722	1
Bin	(0)	1	0	3323	1

Signal:

LOAD_TS_LW_ADDR

	From	To	Count	Threshold
Bin	0	1	28975	1
Bin	1	0	30576	1

Signal:

LOAD_TS_UW_ADDR

	From	To	Count	Threshold
Bin	0	1	26563	1
Bin	1	0	28164	1

Signal:

LOAD_FFMT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	26172	1
Bin	1	0	27773	1

Signal:

LOAD_IDENT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	26059	1
Bin	1	0	27660	1

Signal:

LOAD_FRAME_TEST_W_ADDR

	From	To	Count	Threshold
Bin	0	1	26380	1
Bin	1	0	27981	1

Signal:

STORE_TS_L_W

	From	To	Count	Threshold
Bin	0	1	26563	1
Bin	1	0	28164	1

Signal:

COMMIT_DBL_BUFS

	From	To	Count	Threshold
Bin	0	1	26141	1
Bin	1	0	27742	1

Signal:

BUFFER_MD_W

	From	To	Count	Threshold
Bin	0	1	26059	1
Bin	1	0	27660	1

Signal:

BUFFER_FRAME_TEST_W

	From	To	Count	Threshold
Bin	0	1	26172	1
Bin	1	0	27773	1

Signal:

STORE_LAST_TXTB_INDEX

	From	To	Count	Threshold
Bin	0	1	25501	1
Bin	1	0	27102	1

Signal:

FRAME_VALID_COM_SET

	From	To	Count	Threshold
Bin	0	1	26141	1
Bin	1	0	27742	1

Signal:

FRAME_VALID_COM_CLEAR

	From	To	Count	Threshold
Bin	0	1	26237	1
Bin	1	0	27838	1

Signal:

TX_ARB_LOCKED

	From	To	Count	Threshold
Bin	0	1	25501	1
Bin	1	0	27102	1

Signal:

TXTB_META_CLK_EN

	From	To	Count	Threshold
Bin	0	1	26583	1
Bin	1	0	28184	1

Signal:

MR_TX_PRIORITY_TXBBM

	Element	From	To	Count	Threshold
Bin	(7)(2)	0	1	61	1
Bin	(7)(2)	1	0	319	1
Bin	(7)(1)	0	1	54	1
Bin	(7)(1)	1	0	305	1
Bin	(7)(0)	0	1	88	1
Bin	(7)(0)	1	0	340	1
Bin	(6)(2)	0	1	72	1
Bin	(6)(2)	1	0	317	1
Bin	(6)(1)	0	1	58	1
Bin	(6)(1)	1	0	291	1
Bin	(6)(0)	0	1	104	1
Bin	(6)(0)	1	0	350	1
Bin	(5)(2)	0	1	81	1
Bin	(5)(2)	1	0	316	1
Bin	(5)(1)	0	1	67	1
Bin	(5)(1)	1	0	314	1
Bin	(5)(0)	0	1	89	1
Bin	(5)(0)	1	0	324	1
Bin	(4)(2)	0	1	111	1
Bin	(4)(2)	1	0	308	1
Bin	(4)(1)	0	1	106	1
Bin	(4)(1)	1	0	319	1
Bin	(4)(0)	0	1	90	1
Bin	(4)(0)	1	0	283	1
Bin	(3)(2)	0	1	184	1
Bin	(3)(2)	1	0	1002	1
Bin	(3)(1)	0	1	193	1
Bin	(3)(1)	1	0	1068	1
Bin	(3)(0)	0	1	243	1
Bin	(3)(0)	1	0	1033	1
Bin	(2)(2)	0	1	221	1
Bin	(2)(2)	1	0	1000	1
Bin	(2)(1)	0	1	223	1
Bin	(2)(1)	1	0	1043	1
Bin	(2)(0)	0	1	285	1
Bin	(2)(0)	1	0	1036	1
Bin	(1)(2)	0	1	283	1
Bin	(1)(2)	1	0	1839	1
Bin	(1)(1)	0	1	264	1
Bin	(1)(1)	1	0	1920	1
Bin	(1)(0)	0	1	339	1
Bin	(1)(0)	1	0	1912	1
Bin	(0)(2)	0	1	358	1
Bin	(0)(2)	1	0	1869	1
Bin	(0)(1)	0	1	298	1
Bin	(0)(1)	1	0	1977	1
Bin	(0)(0)	0	1	1988	1
Bin	(0)(0)	1	0	347	1

Signal:

TXTB_PARITY_MISMATCH_VLD

	From	To	Count	Threshold
Bin	0	1	2161	1
Bin	1	0	3762	1

Signal:

TXTB_PARITY_MISMATCH_TX

	From	To	Count	Threshold
Bin	0	1	2352	1
Bin	1	0	3953	1

Signal:

TXTB_HW_CMD_UNLOCK

	From	To	Count	Threshold
Bin	0	1	25490	1
Bin	1	0	27091	1

Uncovered expressions:

"or" expression on lines 354 to 356:

 (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or ((a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0)))) 
  <------------------------LHS------------------------>      <--------------------------------------------RHS-------------------------------------------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	True	False	0	1

"and" expression on lines 355 to 356:

 (a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))) 
  <--------------LHS-------------->       <-----------------------RHS----------------------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1

Excluded expressions:

"or" expression on lines 354 to 356:

 (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or ((a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0)))) 
  <------------------------LHS------------------------>      <--------------------------------------------RHS-------------------------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression on lines 355 to 356:

 (a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))) 
  <--------------LHS-------------->       <-----------------------RHS----------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"or" expression on lines 354 to 356:

 (unsigned(a(63 downto 32)) < unsigned(b(63 downto 32))) or ((a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0)))) 
  <------------------------LHS------------------------>      <--------------------------------------------RHS-------------------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	464906	1
Bin	False	True	753	1

"and" expression on lines 355 to 356:

 (a(63 downto 32) = b(63 downto 32)) and (unsigned(a(31 downto 0)) < unsigned(b(31 downto 0))) 
  <--------------LHS-------------->       <-----------------------RHS----------------------->

	LHS	RHS	Count	Threshold
Bin	True	False	397666	1
Bin	True	True	753	1

"=" expression on line 444:

mr_mode_tttm = TTTM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	547733799	1
Bin	True	811937	1

"and" expression on lines 454 to 455:

 (txtb_available(curr_txtb_index_i) = '1') and (tran_frame_valid_com = '1') 
  <-----------------LHS----------------->       <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	25831	1
Bin	True	False	16635	1
Bin	True	True	26158	1

"=" expression on line 454:

txtb_available(curr_txtb_index_i) = '1'

	Evaluated to	Count	Threshold
Bin	False	68655	1
Bin	True	42793	1

"=" expression on line 455:

tran_frame_valid_com = '1'

	Evaluated to	Count	Threshold
Bin	False	59459	1
Bin	True	51989	1

"or" expression on line 459:

 (validated_buffer = '1') or (tx_arb_locked = '1') 
  <--------LHS--------->      <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	28948	1
Bin	False	True	25501	1
Bin	True	False	25723	1

"=" expression on line 459:

validated_buffer = '1'

	Evaluated to	Count	Threshold
Bin	False	54449	1
Bin	True	51201	1

"=" expression on line 459:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	54671	1
Bin	True	50979	1

"=" expression on line 467:

txtb_parity_mismatch(select_buf_index) = '1'

	Evaluated to	Count	Threshold
Bin	False	52817	1
Bin	True	4075	1

"=" expression on line 477:

txtb_parity_mismatch(curr_txtb_index_i) = '1'

	Evaluated to	Count	Threshold
Bin	False	20302	1
Bin	True	2828	1

"and" expression on line 481:

 txtb_parity_mismatch_tx = '1' and txtb_clk_en_q = '1' 
 <------------LHS------------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	81254	1
Bin	True	False	1969	1
Bin	True	True	699	1

"=" expression on line 481:

txtb_parity_mismatch_tx = '1'

	Evaluated to	Count	Threshold
Bin	False	168581	1
Bin	True	2668	1

"=" expression on line 481:

txtb_clk_en_q = '1'

	Evaluated to	Count	Threshold
Bin	False	89296	1
Bin	True	81953	1

"=" expression on line 489:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	60825	1
Bin	True	50397	1

"=" expression on line 497:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	246950	1
Bin	True	180277	1

"=" expression on line 529:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	161617	1
Bin	True	106383	1

"=" expression on line 533:

tx_arb_locked = '1'

	Evaluated to	Count	Threshold
Bin	False	83444	1
Bin	True	180277	1

"=" expression on line 548:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 561:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 564:

store_ts_l_w = '1'

	Evaluated to	Count	Threshold
Bin	False	547147860	1
Bin	True	26474	1

"=" expression on line 575:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 582:

buffer_md_w = '1'

	Evaluated to	Count	Threshold
Bin	False	547148335	1
Bin	True	25999	1

"=" expression on line 597:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 603:

buffer_frame_test_w = '1'

	Evaluated to	Count	Threshold
Bin	False	547148218	1
Bin	True	26116	1

"=" expression on line 619:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 626:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	547148551	1
Bin	True	25783	1

"=" expression on line 641:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 644:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	547148551	1
Bin	True	25783	1

"=" expression on line 655:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 661:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	547148551	1
Bin	True	25783	1

"=" expression on line 672:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 675:

frame_valid_com_set = '1'

	Evaluated to	Count	Threshold
Bin	False	547148551	1
Bin	True	25783	1

"=" expression on line 677:

frame_valid_com_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	547122314	1
Bin	True	26237	1

"=" expression on line 691:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 697:

store_last_txtb_index = '1'

	Evaluated to	Count	Threshold
Bin	False	547148833	1
Bin	True	25501	1

"=" expression on line 702:

commit_dbl_bufs = '1'

	Evaluated to	Count	Threshold
Bin	False	547148551	1
Bin	True	25783	1

"and" expression on line 709:

 last_txtb_index /= curr_txtb_index_i and store_last_txtb_index = '1' 
 <---------------LHS---------------->     <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	25501	1
Bin	True	False	9994	1
Bin	True	True	9992	1

"/=" expression on line 709:

last_txtb_index /= curr_txtb_index_i

	Evaluated to	Count	Threshold
Bin	False	56556	1
Bin	True	19986	1

"=" expression on line 709:

store_last_txtb_index = '1'

	Evaluated to	Count	Threshold
Bin	False	41049	1
Bin	True	35493	1

"=" expression on line 721:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 728:

select_buf_index = select_buf_index_reg

	Evaluated to	Count	Threshold
Bin	False	54283	1
Bin	True	46626	1

"=" expression on line 737:

load_ts_lw_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	353285	1
Bin	True	50823	1

"=" expression on line 738:

load_ts_uw_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	300248	1
Bin	True	53037	1

"=" expression on line 739:

load_ffmt_w_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	247960	1
Bin	True	52288	1

"=" expression on line 740:

load_ident_w_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	195902	1
Bin	True	52058	1

"=" expression on line 741:

load_frame_test_w_addr = '1'

	Evaluated to	Count	Threshold
Bin	False	143258	1
Bin	True	52644	1

"=" expression on line 746:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"or" expression on lines 756 to 757:

 txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' or txtb_hw_cmd.arbl = '1' or txtb_hw_cmd.failed = '1' 
 <----------------------------------LHS----------------------------------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	28692	1
Bin	False	True	9651	1
Bin	True	False	15839	1

"or" expression on lines 756 to 757:

 txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' or txtb_hw_cmd.arbl = '1' 
 <---------------------LHS---------------------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	38343	1
Bin	False	True	455	1
Bin	True	False	15384	1

"or" expression on line 756:

 txtb_hw_cmd.valid = '1' or txtb_hw_cmd.err = '1' 
 <---------LHS--------->    <--------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	38798	1
Bin	False	True	4269	1
Bin	True	False	11115	1

"=" expression on line 756:

txtb_hw_cmd.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	43067	1
Bin	True	11115	1

"=" expression on line 756:

txtb_hw_cmd.err = '1'

	Evaluated to	Count	Threshold
Bin	False	49913	1
Bin	True	4269	1

"=" expression on line 757:

txtb_hw_cmd.arbl = '1'

	Evaluated to	Count	Threshold
Bin	False	53727	1
Bin	True	455	1

"=" expression on line 757:

txtb_hw_cmd.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	44531	1
Bin	True	9651	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_TXARB_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

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