NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_rx_shift_reg.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
G_BYTE_SHIFT_REG(0)	100.0 % (6/6)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (16/16)
G_BYTE_SHIFT_REG(1)	100.0 % (8/8)	100.0 % (8/8)	N.A.	100.0 % (6/6)	N.A.	N.A.	100.0 % (22/22)
G_BYTE_SHIFT_REG(2)	100.0 % (8/8)	100.0 % (8/8)	N.A.	100.0 % (6/6)	N.A.	N.A.	100.0 % (22/22)
G_BYTE_SHIFT_REG(3)	100.0 % (8/8)	100.0 % (8/8)	N.A.	100.0 % (6/6)	N.A.	N.A.	100.0 % (22/22)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

G_BYTE_SHIFT_REG(0)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (16/16)

G_BYTE_SHIFT_REG(1)

100.0 % (8/8)

N.A.

100.0 % (6/6)

N.A.

100.0 % (22/22)

G_BYTE_SHIFT_REG(2)

100.0 % (8/8)

N.A.

100.0 % (6/6)

N.A.

100.0 % (22/22)

G_BYTE_SHIFT_REG(3)

100.0 % (8/8)

N.A.

100.0 % (6/6)

N.A.

100.0 % (22/22)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RX_SHIFT_REG.I_SHIFT_REG_BYTE	N.A.	N.A.	100.0 % (156/156)	N.A.	N.A.	N.A.	100.0 % (156/156)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RX_SHIFT_REG.I_SHIFT_REG_BYTE

N.A.

100.0 % (156/156)

N.A.

100.0 % (156/156)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INPUT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BYTE_CLOCK_ENA

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

BYTE_INPUT_SEL

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file

Covered toggles:

Port:

REG_STAT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	821490	1
Bin	(31)	1	0	1345621	1
Bin	(30)	0	1	741063	1
Bin	(30)	1	0	1364250	1
Bin	(29)	0	1	679201	1
Bin	(29)	1	0	1564358	1
Bin	(28)	0	1	753191	1
Bin	(28)	1	0	1533342	1
Bin	(27)	0	1	716592	1
Bin	(27)	1	0	1553376	1
Bin	(26)	0	1	774303	1
Bin	(26)	1	0	1481210	1
Bin	(25)	0	1	708987	1
Bin	(25)	1	0	1566211	1
Bin	(24)	0	1	782227	1
Bin	(24)	1	0	1536806	1
Bin	(23)	0	1	1299689	1
Bin	(23)	1	0	2228485	1
Bin	(22)	0	1	800257	1
Bin	(22)	1	0	1475792	1
Bin	(21)	0	1	772895	1
Bin	(21)	1	0	1461410	1
Bin	(20)	0	1	847586	1
Bin	(20)	1	0	1412859	1
Bin	(19)	0	1	760846	1
Bin	(19)	1	0	1423695	1
Bin	(18)	0	1	829766	1
Bin	(18)	1	0	1293756	1
Bin	(17)	0	1	789831	1
Bin	(17)	1	0	1325173	1
Bin	(16)	0	1	834415	1
Bin	(16)	1	0	1332726	1
Bin	(15)	0	1	844353	1
Bin	(15)	1	0	1159792	1
Bin	(14)	0	1	1059535	1
Bin	(14)	1	0	1084664	1
Bin	(13)	0	1	892175	1
Bin	(13)	1	0	1264847	1
Bin	(12)	0	1	1049050	1
Bin	(12)	1	0	1142468	1
Bin	(11)	0	1	913738	1
Bin	(11)	1	0	1284051	1
Bin	(10)	0	1	1083815	1
Bin	(10)	1	0	1161786	1
Bin	(9)	0	1	937333	1
Bin	(9)	1	0	1305290	1
Bin	(8)	0	1	1112675	1
Bin	(8)	1	0	1185433	1
Bin	(7)	0	1	995757	1
Bin	(7)	1	0	1360739	1
Bin	(6)	0	1	1080252	1
Bin	(6)	1	0	1058957	1
Bin	(5)	0	1	1063396	1
Bin	(5)	1	0	1151745	1
Bin	(4)	0	1	1139887	1
Bin	(4)	1	0	1127300	1
Bin	(3)	0	1	1058690	1
Bin	(3)	1	0	1255885	1
Bin	(2)	0	1	1740887	1
Bin	(2)	1	0	1641650	1
Bin	(1)	0	1	1079450	1
Bin	(1)	1	0	1110327	1
Bin	(0)	0	1	1134996	1
Bin	(0)	1	0	1071774	1

Signal:

SHIFT_REG_Q

	Element	From	To	Count	Threshold
Bin	(0)(7)	0	1	2563203	1
Bin	(0)(7)	1	0	3291019	1
Bin	(0)(6)	0	1	1109069	1
Bin	(0)(6)	1	0	986368	1
Bin	(0)(5)	0	1	1063396	1
Bin	(0)(5)	1	0	1068426	1
Bin	(0)(4)	0	1	1139887	1
Bin	(0)(4)	1	0	1045328	1
Bin	(0)(3)	0	1	1058690	1
Bin	(0)(3)	1	0	1180079	1
Bin	(0)(2)	0	1	1137763	1
Bin	(0)(2)	1	0	1050292	1
Bin	(0)(1)	0	1	1079450	1
Bin	(0)(1)	1	0	1110327	1
Bin	(0)(0)	0	1	1134996	1
Bin	(0)(0)	1	0	1071774	1
Bin	(1)(7)	0	1	2403237	1
Bin	(1)(7)	1	0	3450985	1
Bin	(1)(6)	0	1	1085136	1
Bin	(1)(6)	1	0	1103259	1
Bin	(1)(5)	0	1	892175	1
Bin	(1)(5)	1	0	1264847	1
Bin	(1)(4)	0	1	1049050	1
Bin	(1)(4)	1	0	1142468	1
Bin	(1)(3)	0	1	913738	1
Bin	(1)(3)	1	0	1284051	1
Bin	(1)(2)	0	1	1083815	1
Bin	(1)(2)	1	0	1161786	1
Bin	(1)(1)	0	1	937333	1
Bin	(1)(1)	1	0	1305290	1
Bin	(1)(0)	0	1	1112675	1
Bin	(1)(0)	1	0	1185433	1
Bin	(2)(7)	0	1	2163312	1
Bin	(2)(7)	1	0	3690910	1
Bin	(2)(6)	0	1	824771	1
Bin	(2)(6)	1	0	1344299	1
Bin	(2)(5)	0	1	772895	1
Bin	(2)(5)	1	0	1301086	1
Bin	(2)(4)	0	1	799008	1
Bin	(2)(4)	1	0	1266679	1
Bin	(2)(3)	0	1	760846	1
Bin	(2)(3)	1	0	1423695	1
Bin	(2)(2)	0	1	829766	1
Bin	(2)(2)	1	0	1293756	1
Bin	(2)(1)	0	1	789831	1
Bin	(2)(1)	1	0	1325173	1
Bin	(2)(0)	0	1	834415	1
Bin	(2)(0)	1	0	1332726	1
Bin	(3)(7)	0	1	821490	1
Bin	(3)(7)	1	0	1345621	1
Bin	(3)(6)	0	1	741063	1
Bin	(3)(6)	1	0	1364250	1
Bin	(3)(5)	0	1	679201	1
Bin	(3)(5)	1	0	1564358	1
Bin	(3)(4)	0	1	753191	1
Bin	(3)(4)	1	0	1533342	1
Bin	(3)(3)	0	1	716592	1
Bin	(3)(3)	1	0	1553376	1
Bin	(3)(2)	0	1	774303	1
Bin	(3)(2)	1	0	1481210	1
Bin	(3)(1)	0	1	708987	1
Bin	(3)(1)	1	0	1566211	1
Bin	(3)(0)	0	1	782227	1
Bin	(3)(0)	1	0	1536806	1

Signal:

SHIFT_REG_IN

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1281195	1
Bin	(3)	1	0	2463475	1
Bin	(2)	0	1	1348759	1
Bin	(2)	1	0	2395911	1
Bin	(1)	0	1	1630967	1
Bin	(1)	1	0	2113703	1
Bin	(0)	0	1	1884049	1
Bin	(0)	1	0	1862222	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RX_SHIFT_REG.I_SHIFT_REG_BYTE

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_rx_shift_reg.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: