NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_RST_REG	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP.I_MAC_FC_ERR_COUNTERS	100.0 % (83/83)	100.0 % (70/70)	100.0 % (508/508)	100.0 % (114/114)	N.A.	N.A.	100.0 % (775/775)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 215 to 225:

215:        if (rst_n = '0') then 
216:            mr_ctr_pres_ptx_q   <= '0'; 
...
224:            mr_ctr_pres_efd_q   <= mr_ctr_pres_efd; 
225:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 216:

216: mr_ctr_pres_ptx_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 217:

217: mr_ctr_pres_prx_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 218:

218: mr_ctr_pres_enorm_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 219:

219: mr_ctr_pres_efd_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 221:

221: mr_ctr_pres_ptx_q <= mr_ctr_pres_ptx;
Count: 547174334
Threshold: 1

Signal assignment statement on line 222:

222: mr_ctr_pres_prx_q <= mr_ctr_pres_prx;
Count: 547174334
Threshold: 1

Signal assignment statement on line 223:

223: mr_ctr_pres_enorm_q <= mr_ctr_pres_enorm;
Count: 547174334
Threshold: 1

Signal assignment statement on line 224:

224: mr_ctr_pres_efd_q <= mr_ctr_pres_efd;
Count: 547174334
Threshold: 1

If statement on lines 228 to 229:

228:    modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else 
229:                    '0';

Count: 217894
Threshold: 1

Signal assignment statement on line 228:

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else
Count: 107346
Threshold: 1

Signal assignment statement on line 229:

229: '0';
Count: 110548
Threshold: 1

If statement on lines 232 to 234:

232:    modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1') 
233:                        else 
234:                    '0';

Count: 309748
Threshold: 1

Signal assignment statement on line 232:

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')
Count: 153289
Threshold: 1

Signal assignment statement on line 234:

234: '0';
Count: 156459
Threshold: 1

If statement on lines 239 to 240:

239:    tx_err_ctr_dec <=  (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else 
240:                       tx_err_ctr_q;

Count: 33872
Threshold: 1

Signal assignment statement on line 239:

239: tx_err_ctr_dec <= (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else
Count: 19782
Threshold: 1

Signal assignment statement on line 240:

240: tx_err_ctr_q;
Count: 14090
Threshold: 1

If statement on lines 244 to 247:

244:    tx_err_ctr_d <= 
245:              unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else 
246:                        tx_err_ctr_q + 8 when (inc_eight = '1') else 
247:                          tx_err_ctr_dec;

Count: 268554
Threshold: 1

Signal assignment statement on line 245:

245: unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else
Count: 20586
Threshold: 1

Signal assignment statement on line 246:

246: tx_err_ctr_q + 8 when (inc_eight = '1') else
Count: 110573
Threshold: 1

Signal assignment statement on line 247:

247: tx_err_ctr_dec;
Count: 137395
Threshold: 1

If statement on lines 251 to 253:

251:    tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else 
252:                     '1' when (mr_ctr_pres_ptx_q = '1') else 
253:                     '0';

Count: 299343
Threshold: 1

Signal assignment statement on line 251:

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else
Count: 83999
Threshold: 1

Signal assignment statement on line 252:

252: '1' when (mr_ctr_pres_ptx_q = '1') else
Count: 19364
Threshold: 1

Signal assignment statement on line 253:

253: '0';
Count: 195980
Threshold: 1

If statement on lines 258 to 260:

258:    res_err_ctrs_d <= '0' when (rst_n = '0' or set_err_active = '1') 
259:                          else 
260:                      '1';

Count: 32632
Threshold: 1

Signal assignment statement on line 258:

258: res_err_ctrs_d <= '0' when (rst_n = '0' or set_err_active = '1')
Count: 14709
Threshold: 1

Signal assignment statement on line 260:

260: '1';
Count: 17923
Threshold: 1

If statement on lines 284 to 290:

284:        if (res_err_ctrs_q_scan = '0') then 
285:            tx_err_ctr_q <= (others => '0'); 
...
289:            end if; 
290:        end if;

Count: 1096794594
Threshold: 1

Signal assignment statement on line 285:

285: tx_err_ctr_q <= (others => '0');
Count: 2455551
Threshold: 1

If statement on lines 287 to 289:

287:            if (tx_err_ctr_ce = '1') then 
288:                tx_err_ctr_q <= tx_err_ctr_d; 
289:            end if;

Count: 547161214
Threshold: 1

Signal assignment statement on line 288:

288: tx_err_ctr_q <= tx_err_ctr_d;
Count: 45126
Threshold: 1

If statement on lines 297 to 299:

297:    rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else 
298:                       (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else 
299:                            rx_err_ctr_q;

Count: 27275
Threshold: 1

Signal assignment statement on line 297:

297: rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else
Count: 8761
Threshold: 1

Signal assignment statement on line 298:

298: (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else
Count: 9004
Threshold: 1

Signal assignment statement on line 299:

299: rx_err_ctr_q;
Count: 9510
Threshold: 1

If statement on lines 303 to 304:

303:    rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else 
304:                      rx_err_ctr_q + 8;

Count: 120762
Threshold: 1

Signal assignment statement on line 303:

303: rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else
Count: 58075
Threshold: 1

Signal assignment statement on line 304:

304: rx_err_ctr_q + 8;
Count: 62687
Threshold: 1

If statement on lines 307 to 308:

307:    rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else 
308:                      rx_err_ctr_inc;

Count: 146436
Threshold: 1

Signal assignment statement on line 307:

307: rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else
Count: 693
Threshold: 1

Signal assignment statement on line 308:

308: rx_err_ctr_inc;
Count: 145743
Threshold: 1

If statement on lines 314 to 316:

314:    rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else 
315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else 
316:                                rx_err_ctr_dec;

Count: 431247
Threshold: 1

Signal assignment statement on line 314:

314: rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else
Count: 22906
Threshold: 1

Signal assignment statement on line 315:

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

Count: 154419
Threshold: 1

Signal assignment statement on line 316:

316: rx_err_ctr_dec;
Count: 253922
Threshold: 1

If statement on lines 320 to 322:

320:    rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else 
321:                     '1' when (mr_ctr_pres_prx_q = '1') else 
322:                     '0';

Count: 412574
Threshold: 1

Signal assignment statement on line 320:

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else
Count: 69204
Threshold: 1

Signal assignment statement on line 321:

321: '1' when (mr_ctr_pres_prx_q = '1') else
Count: 19759
Threshold: 1

Signal assignment statement on line 322:

322: '0';
Count: 323611
Threshold: 1

If statement on lines 329 to 335:

329:        if (res_err_ctrs_q_scan = '0') then 
330:            rx_err_ctr_q <= (others => '0'); 
...
334:            end if; 
335:        end if;

Count: 1096794594
Threshold: 1

Signal assignment statement on line 330:

330: rx_err_ctr_q <= (others => '0');
Count: 2455551
Threshold: 1

If statement on lines 332 to 334:

332:            if (rx_err_ctr_ce = '1') then 
333:                rx_err_ctr_q <= rx_err_ctr_d; 
334:            end if;

Count: 547161214
Threshold: 1

Signal assignment statement on line 333:

333: rx_err_ctr_q <= rx_err_ctr_d;
Count: 47304
Threshold: 1

If statement on lines 346 to 347:

346:    nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else 
347:                       data_err_ctr_q;

Count: 95440
Threshold: 1

Signal assignment statement on line 346:

346: nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else
Count: 54687
Threshold: 1

Signal assignment statement on line 347:

347: data_err_ctr_q;
Count: 40753
Threshold: 1

Signal assignment statement on line 349:

349: nom_dat_sel_ctr_add <= nom_dat_sel_ctr + 1;
Count: 63901
Threshold: 1

If statement on lines 351 to 353:

351:    nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0') 
352:                                         else 
353:                         (others => '0');

Count: 80319
Threshold: 1

Signal assignment statement on line 351:

351: nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0')
Count: 70509
Threshold: 1

Signal assignment statement on line 353:

353: (others => '0');
Count: 9810
Threshold: 1

If statement on lines 355 to 357:

355:    data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0') 
356:                                          else 
357:                         (others => '0');

Count: 80319
Threshold: 1

Signal assignment statement on line 355:

355: data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0')
Count: 65703
Threshold: 1

Signal assignment statement on line 357:

357: (others => '0');
Count: 14616
Threshold: 1

If statement on lines 360 to 364:

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE)) 
363:                          else 
364:                      '0';

Count: 329327
Threshold: 1

Signal assignment statement on line 360:

360: nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or
Count: 130550
Threshold: 1

Signal assignment statement on line 364:

364: '0';
Count: 198777
Threshold: 1

If statement on lines 366 to 370:

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
369:                           else 
370:                       '0';

Count: 329327
Threshold: 1

Signal assignment statement on line 366:

366: data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or
Count: 20317
Threshold: 1

Signal assignment statement on line 370:

370: '0';
Count: 309010
Threshold: 1

If statement on lines 377 to 383:

377:        if (res_err_ctrs_q_scan = '0') then 
378:            nom_err_ctr_q <= (others => '0'); 
...
382:            end if; 
383:        end if;

Count: 1096794594
Threshold: 1

Signal assignment statement on line 378:

378: nom_err_ctr_q <= (others => '0');
Count: 2455551
Threshold: 1

If statement on lines 380 to 382:

380:            if (nom_err_ctr_ce = '1') then 
381:                nom_err_ctr_q <= nom_err_ctr_d; 
382:            end if;

Count: 547161214
Threshold: 1

Signal assignment statement on line 381:

381: nom_err_ctr_q <= nom_err_ctr_d;
Count: 23478
Threshold: 1

If statement on lines 388 to 394:

388:        if (res_err_ctrs_q_scan = '0') then 
389:            data_err_ctr_q <= (others => '0'); 
...
393:            end if; 
394:        end if;

Count: 1096794594
Threshold: 1

Signal assignment statement on line 389:

389: data_err_ctr_q <= (others => '0');
Count: 2455551
Threshold: 1

If statement on lines 391 to 393:

391:            if (data_err_ctr_ce = '1') then 
392:                data_err_ctr_q <= data_err_ctr_d; 
393:            end if;

Count: 547161214
Threshold: 1

Signal assignment statement on line 392:

392: data_err_ctr_q <= data_err_ctr_d;
Count: 17014
Threshold: 1

Signal assignment statement on line 400:

400: rx_err_ctr <= std_logic_vector(rx_err_ctr_q);
Count: 27275
Threshold: 1

Signal assignment statement on line 401:

401: tx_err_ctr <= std_logic_vector(tx_err_ctr_q);
Count: 33872
Threshold: 1

Signal assignment statement on line 403:

403: norm_err_ctr <= std_logic_vector(nom_err_ctr_q);
Count: 27615
Threshold: 1

Signal assignment statement on line 404:

404: data_err_ctr <= std_logic_vector(data_err_ctr_q);
Count: 14578
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 215:

215: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 220:

220: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 228:

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else

	Evaluated to	Count	Threshold
Bin	True	107346	1
Bin	False	110548	1

"if" / "when" / "else" condition on line 232:

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')

	Evaluated to	Count	Threshold
Bin	True	153289	1
Bin	False	156459	1

"if" / "when" / "else" condition on line 239:

239: tx_err_ctr_dec <= (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else

	Evaluated to	Count	Threshold
Bin	True	19782	1
Bin	False	14090	1

"if" / "when" / "else" condition on line 245:

245: unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	20586	1
Bin	False	247968	1

"if" / "when" / "else" condition on line 246:

246: tx_err_ctr_q + 8 when (inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	True	110573	1
Bin	False	137395	1

"if" / "when" / "else" condition on line 251:

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else

	Evaluated to	Count	Threshold
Bin	True	83999	1
Bin	False	215344	1

"if" / "when" / "else" condition on line 252:

252: '1' when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	19364	1
Bin	False	195980	1

"if" / "when" / "else" condition on line 258:

258: res_err_ctrs_d <= '0' when (rst_n = '0' or set_err_active = '1')

	Evaluated to	Count	Threshold
Bin	True	14709	1
Bin	False	17923	1

"if" / "when" / "else" condition on line 284:

284: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2455551	1
Bin	False	1094339043	1

"if" / "when" / "else" condition on line 286:

286: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547161214	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 287:

287: if (tx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	45126	1
Bin	False	547116088	1

"if" / "when" / "else" condition on line 297:

297: rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else

	Evaluated to	Count	Threshold
Bin	True	8761	1
Bin	False	18514	1

"if" / "when" / "else" condition on line 298:

298: (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else

	Evaluated to	Count	Threshold
Bin	True	9004	1
Bin	False	9510	1

"if" / "when" / "else" condition on line 303:

303: rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else

	Evaluated to	Count	Threshold
Bin	True	58075	1
Bin	False	62687	1

"if" / "when" / "else" condition on line 307:

307: rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else

	Evaluated to	Count	Threshold
Bin	True	693	1
Bin	False	145743	1

"if" / "when" / "else" condition on line 314:

314: rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	22906	1
Bin	False	408341	1

"if" / "when" / "else" condition on line 315:

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	True	154419	1
Bin	False	253922	1

"if" / "when" / "else" condition on line 320:

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else

	Evaluated to	Count	Threshold
Bin	True	69204	1
Bin	False	343370	1

"if" / "when" / "else" condition on line 321:

321: '1' when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	19759	1
Bin	False	323611	1

"if" / "when" / "else" condition on line 329:

329: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2455551	1
Bin	False	1094339043	1

"if" / "when" / "else" condition on line 331:

331: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547161214	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 332:

332: if (rx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	47304	1
Bin	False	547113910	1

"if" / "when" / "else" condition on line 346:

346: nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	54687	1
Bin	False	40753	1

"if" / "when" / "else" condition on line 351:

351: nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0')

	Evaluated to	Count	Threshold
Bin	True	70509	1
Bin	False	9810	1

"if" / "when" / "else" condition on line 355:

355: data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0')

	Evaluated to	Count	Threshold
Bin	True	65703	1
Bin	False	14616	1

"if" / "when" / "else" condition on lines 360 to 362:

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE))

	Evaluated to	Count	Threshold
Bin	True	130550	1
Bin	False	198777	1

"if" / "when" / "else" condition on lines 366 to 368:

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE))

	Evaluated to	Count	Threshold
Bin	True	20317	1
Bin	False	309010	1

"if" / "when" / "else" condition on line 377:

377: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2455551	1
Bin	False	1094339043	1

"if" / "when" / "else" condition on line 379:

379: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547161214	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 380:

380: if (nom_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	23478	1
Bin	False	547137736	1

"if" / "when" / "else" condition on line 388:

388: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2455551	1
Bin	False	1094339043	1

"if" / "when" / "else" condition on line 390:

390: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547161214	1
Bin	False	547177829	1

"if" / "when" / "else" condition on line 391:

391: if (data_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	17014	1
Bin	False	547144200	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

INC_ONE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INC_EIGHT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DEC_ONE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SET_ERR_ACTIVE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TRANSMITTER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_RECEIVER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_CTPV

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_CTR_PRES_PTX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_PRX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_ENORM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_EFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Signal:

RX_ERR_CTR_DEC

	Element	From	To	Count	Threshold	Excluded due to
Bin	(8)	0	1	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file

Covered toggles:

Port:

RX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	130	1
Bin	(8)	1	0	1731	1
Bin	(7)	0	1	350	1
Bin	(7)	1	0	1951	1
Bin	(6)	0	1	255	1
Bin	(6)	1	0	1854	1
Bin	(5)	0	1	363	1
Bin	(5)	1	0	1963	1
Bin	(4)	0	1	497	1
Bin	(4)	1	0	2098	1
Bin	(3)	0	1	685	1
Bin	(3)	1	0	2285	1
Bin	(2)	0	1	617	1
Bin	(2)	1	0	2218	1
Bin	(1)	0	1	1191	1
Bin	(1)	1	0	2792	1
Bin	(0)	0	1	11216	1
Bin	(0)	1	0	12809	1

Port:

TX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	249	1
Bin	(8)	1	0	1850	1
Bin	(7)	0	1	517	1
Bin	(7)	1	0	2118	1
Bin	(6)	0	1	501	1
Bin	(6)	1	0	2102	1
Bin	(5)	0	1	805	1
Bin	(5)	1	0	2406	1
Bin	(4)	0	1	1933	1
Bin	(4)	1	0	3534	1
Bin	(3)	0	1	12743	1
Bin	(3)	1	0	14344	1
Bin	(2)	0	1	2955	1
Bin	(2)	1	0	4556	1
Bin	(1)	0	1	3324	1
Bin	(1)	1	0	4925	1
Bin	(0)	0	1	3524	1
Bin	(0)	1	0	5125	1

Port:

NORM_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	1667	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	1668	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	1661	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	1664	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	1668	1
Bin	(9)	0	1	63	1
Bin	(9)	1	0	1662	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1671	1
Bin	(7)	0	1	75	1
Bin	(7)	1	0	1673	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1696	1
Bin	(5)	0	1	155	1
Bin	(5)	1	0	1752	1
Bin	(4)	0	1	276	1
Bin	(4)	1	0	1876	1
Bin	(3)	0	1	608	1
Bin	(3)	1	0	2205	1
Bin	(2)	0	1	1361	1
Bin	(2)	1	0	2958	1
Bin	(1)	0	1	3082	1
Bin	(1)	1	0	4678	1
Bin	(0)	0	1	11727	1
Bin	(0)	1	0	13323	1

Port:

DATA_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	63	1
Bin	(15)	1	0	1661	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1667	1
Bin	(13)	0	1	67	1
Bin	(13)	1	0	1665	1
Bin	(12)	0	1	65	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	61	1
Bin	(11)	1	0	1658	1
Bin	(10)	0	1	64	1
Bin	(10)	1	0	1661	1
Bin	(9)	0	1	75	1
Bin	(9)	1	0	1673	1
Bin	(8)	0	1	85	1
Bin	(8)	1	0	1682	1
Bin	(7)	0	1	98	1
Bin	(7)	1	0	1696	1
Bin	(6)	0	1	133	1
Bin	(6)	1	0	1732	1
Bin	(5)	0	1	209	1
Bin	(5)	1	0	1805	1
Bin	(4)	0	1	352	1
Bin	(4)	1	0	1952	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1295	1
Bin	(2)	1	0	2895	1
Bin	(1)	0	1	2523	1
Bin	(1)	1	0	4120	1
Bin	(0)	0	1	5589	1
Bin	(0)	1	0	7187	1

Signal:

TX_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	647	1
Bin	(8)	1	0	2248	1
Bin	(7)	0	1	3065	1
Bin	(7)	1	0	4666	1
Bin	(6)	0	1	4231	1
Bin	(6)	1	0	5832	1
Bin	(5)	0	1	8083	1
Bin	(5)	1	0	9684	1
Bin	(4)	0	1	33486	1
Bin	(4)	1	0	35087	1
Bin	(3)	0	1	69742	1
Bin	(3)	1	0	71343	1
Bin	(2)	0	1	36328	1
Bin	(2)	1	0	37929	1
Bin	(1)	0	1	48159	1
Bin	(1)	1	0	49760	1
Bin	(0)	0	1	52816	1
Bin	(0)	1	0	54417	1

Signal:

RX_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	304	1
Bin	(8)	1	0	1905	1
Bin	(7)	0	1	24310	1
Bin	(7)	1	0	25911	1
Bin	(6)	0	1	25016	1
Bin	(6)	1	0	26615	1
Bin	(5)	0	1	20973	1
Bin	(5)	1	0	22573	1
Bin	(4)	0	1	7084	1
Bin	(4)	1	0	8685	1
Bin	(3)	0	1	129984	1
Bin	(3)	1	0	131584	1
Bin	(2)	0	1	26045	1
Bin	(2)	1	0	27646	1
Bin	(1)	0	1	28151	1
Bin	(1)	1	0	29752	1
Bin	(0)	0	1	25848	1
Bin	(0)	1	0	27449	1

Signal:

TX_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	249	1
Bin	(8)	1	0	1850	1
Bin	(7)	0	1	517	1
Bin	(7)	1	0	2118	1
Bin	(6)	0	1	501	1
Bin	(6)	1	0	2102	1
Bin	(5)	0	1	805	1
Bin	(5)	1	0	2406	1
Bin	(4)	0	1	1933	1
Bin	(4)	1	0	3534	1
Bin	(3)	0	1	12743	1
Bin	(3)	1	0	14344	1
Bin	(2)	0	1	2955	1
Bin	(2)	1	0	4556	1
Bin	(1)	0	1	3324	1
Bin	(1)	1	0	4925	1
Bin	(0)	0	1	3524	1
Bin	(0)	1	0	5125	1

Signal:

RX_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	130	1
Bin	(8)	1	0	1731	1
Bin	(7)	0	1	350	1
Bin	(7)	1	0	1951	1
Bin	(6)	0	1	255	1
Bin	(6)	1	0	1854	1
Bin	(5)	0	1	363	1
Bin	(5)	1	0	1963	1
Bin	(4)	0	1	497	1
Bin	(4)	1	0	2098	1
Bin	(3)	0	1	685	1
Bin	(3)	1	0	2285	1
Bin	(2)	0	1	617	1
Bin	(2)	1	0	2218	1
Bin	(1)	0	1	1191	1
Bin	(1)	1	0	2792	1
Bin	(0)	0	1	11216	1
Bin	(0)	1	0	12809	1

Signal:

RX_ERR_CTR_INC

	Element	From	To	Count	Threshold
Bin	(8)	0	1	141	1
Bin	(8)	1	0	1742	1
Bin	(7)	0	1	457	1
Bin	(7)	1	0	2058	1
Bin	(6)	0	1	437	1
Bin	(6)	1	0	2036	1
Bin	(5)	0	1	826	1
Bin	(5)	1	0	2426	1
Bin	(4)	0	1	2009	1
Bin	(4)	1	0	3609	1
Bin	(3)	0	1	47910	1
Bin	(3)	1	0	46310	1
Bin	(2)	0	1	5437	1
Bin	(2)	1	0	7038	1
Bin	(1)	0	1	13014	1
Bin	(1)	1	0	14615	1
Bin	(0)	0	1	57159	1
Bin	(0)	1	0	58752	1

Signal:

RX_ERR_CTR_SAT

	Element	From	To	Count	Threshold
Bin	(8)	0	1	639	1
Bin	(8)	1	0	2240	1
Bin	(7)	0	1	754	1
Bin	(7)	1	0	2355	1
Bin	(6)	0	1	826	1
Bin	(6)	1	0	2425	1
Bin	(5)	0	1	1156	1
Bin	(5)	1	0	2756	1
Bin	(4)	0	1	2175	1
Bin	(4)	1	0	3775	1
Bin	(3)	0	1	47951	1
Bin	(3)	1	0	46351	1
Bin	(2)	0	1	5632	1
Bin	(2)	1	0	7233	1
Bin	(1)	0	1	13204	1
Bin	(1)	1	0	14805	1
Bin	(0)	0	1	57496	1
Bin	(0)	1	0	59089	1

Signal:

TX_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	103363	1
Bin	1	0	104964	1

Signal:

RX_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	88963	1
Bin	1	0	90564	1

Signal:

MODIF_TX_CTR

	From	To	Count	Threshold
Bin	0	1	107346	1
Bin	1	0	108947	1

Signal:

MODIF_RX_CTR

	From	To	Count	Threshold
Bin	0	1	153257	1
Bin	1	0	154858	1

Signal:

TX_ERR_CTR_DEC

	Element	From	To	Count	Threshold
Bin	(8)	0	1	232	1
Bin	(8)	1	0	1833	1
Bin	(7)	0	1	493	1
Bin	(7)	1	0	2094	1
Bin	(6)	0	1	501	1
Bin	(6)	1	0	2102	1
Bin	(5)	0	1	751	1
Bin	(5)	1	0	2352	1
Bin	(4)	0	1	1555	1
Bin	(4)	1	0	3156	1
Bin	(3)	0	1	2907	1
Bin	(3)	1	0	4508	1
Bin	(2)	0	1	10864	1
Bin	(2)	1	0	12465	1
Bin	(1)	0	1	10920	1
Bin	(1)	1	0	12521	1
Bin	(0)	0	1	11777	1
Bin	(0)	1	0	13378	1

Signal:

RX_ERR_CTR_DEC

	Element	From	To	Count	Threshold
Bin	(8)	1	0	1601	1
Bin	(7)	1	0	1601	1
Bin	(6)	0	1	430	1
Bin	(6)	1	0	2029	1
Bin	(5)	0	1	476	1
Bin	(5)	1	0	2076	1
Bin	(4)	0	1	599	1
Bin	(4)	1	0	2200	1
Bin	(3)	0	1	838	1
Bin	(3)	1	0	2438	1
Bin	(2)	0	1	528	1
Bin	(2)	1	0	2129	1
Bin	(1)	0	1	750	1
Bin	(1)	1	0	2351	1
Bin	(0)	0	1	1597	1
Bin	(0)	1	0	3198	1

Signal:

NOM_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	3268	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	3269	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	3262	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	3260	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	3265	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	3269	1
Bin	(9)	0	1	4545	1
Bin	(9)	1	0	7745	1
Bin	(8)	0	1	4561	1
Bin	(8)	1	0	7762	1
Bin	(7)	0	1	4625	1
Bin	(7)	1	0	7824	1
Bin	(6)	0	1	4944	1
Bin	(6)	1	0	8144	1
Bin	(5)	0	1	5406	1
Bin	(5)	1	0	8604	1
Bin	(4)	0	1	5975	1
Bin	(4)	1	0	9176	1
Bin	(3)	0	1	6986	1
Bin	(3)	1	0	10184	1
Bin	(2)	0	1	9035	1
Bin	(2)	1	0	12232	1
Bin	(1)	0	1	23496	1
Bin	(1)	1	0	26690	1
Bin	(0)	0	1	27470	1
Bin	(0)	1	0	27475	1

Signal:

DATA_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	3268	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	3269	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	3262	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	3260	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	3265	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	3269	1
Bin	(9)	0	1	4545	1
Bin	(9)	1	0	7745	1
Bin	(8)	0	1	4561	1
Bin	(8)	1	0	7762	1
Bin	(7)	0	1	4625	1
Bin	(7)	1	0	7824	1
Bin	(6)	0	1	4944	1
Bin	(6)	1	0	8144	1
Bin	(5)	0	1	5406	1
Bin	(5)	1	0	8604	1
Bin	(4)	0	1	5953	1
Bin	(4)	1	0	9154	1
Bin	(3)	0	1	6961	1
Bin	(3)	1	0	10159	1
Bin	(2)	0	1	8791	1
Bin	(2)	1	0	11988	1
Bin	(1)	0	1	18958	1
Bin	(1)	1	0	22152	1
Bin	(0)	0	1	27470	1
Bin	(0)	1	0	27475	1

Signal:

NOM_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	1667	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	1668	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	1661	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	1664	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	1668	1
Bin	(9)	0	1	63	1
Bin	(9)	1	0	1662	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1671	1
Bin	(7)	0	1	75	1
Bin	(7)	1	0	1673	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1696	1
Bin	(5)	0	1	155	1
Bin	(5)	1	0	1752	1
Bin	(4)	0	1	276	1
Bin	(4)	1	0	1876	1
Bin	(3)	0	1	608	1
Bin	(3)	1	0	2205	1
Bin	(2)	0	1	1361	1
Bin	(2)	1	0	2958	1
Bin	(1)	0	1	3082	1
Bin	(1)	1	0	4678	1
Bin	(0)	0	1	11727	1
Bin	(0)	1	0	13323	1

Signal:

DATA_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(15)	0	1	63	1
Bin	(15)	1	0	1661	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1667	1
Bin	(13)	0	1	67	1
Bin	(13)	1	0	1665	1
Bin	(12)	0	1	65	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	61	1
Bin	(11)	1	0	1658	1
Bin	(10)	0	1	64	1
Bin	(10)	1	0	1661	1
Bin	(9)	0	1	75	1
Bin	(9)	1	0	1673	1
Bin	(8)	0	1	85	1
Bin	(8)	1	0	1682	1
Bin	(7)	0	1	98	1
Bin	(7)	1	0	1696	1
Bin	(6)	0	1	133	1
Bin	(6)	1	0	1732	1
Bin	(5)	0	1	209	1
Bin	(5)	1	0	1805	1
Bin	(4)	0	1	352	1
Bin	(4)	1	0	1952	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1295	1
Bin	(2)	1	0	2895	1
Bin	(1)	0	1	2523	1
Bin	(1)	1	0	4120	1
Bin	(0)	0	1	5589	1
Bin	(0)	1	0	7187	1

Signal:

NOM_DAT_SEL_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	1667	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	1668	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	1661	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	1664	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	1668	1
Bin	(9)	0	1	4536	1
Bin	(9)	1	0	6135	1
Bin	(8)	0	1	4553	1
Bin	(8)	1	0	6153	1
Bin	(7)	0	1	4615	1
Bin	(7)	1	0	6213	1
Bin	(6)	0	1	4917	1
Bin	(6)	1	0	6516	1
Bin	(5)	0	1	5399	1
Bin	(5)	1	0	6996	1
Bin	(4)	0	1	5832	1
Bin	(4)	1	0	7432	1
Bin	(3)	0	1	6915	1
Bin	(3)	1	0	8512	1
Bin	(2)	0	1	8445	1
Bin	(2)	1	0	10042	1
Bin	(1)	0	1	11795	1
Bin	(1)	1	0	13391	1
Bin	(0)	0	1	23745	1
Bin	(0)	1	0	25341	1

Signal:

NOM_DAT_SEL_CTR_ADD

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	1667	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	1668	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	1661	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	1664	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	1668	1
Bin	(9)	0	1	4545	1
Bin	(9)	1	0	6144	1
Bin	(8)	0	1	4561	1
Bin	(8)	1	0	6161	1
Bin	(7)	0	1	4625	1
Bin	(7)	1	0	6223	1
Bin	(6)	0	1	4944	1
Bin	(6)	1	0	6543	1
Bin	(5)	0	1	5406	1
Bin	(5)	1	0	7003	1
Bin	(4)	0	1	5953	1
Bin	(4)	1	0	7553	1
Bin	(3)	0	1	6961	1
Bin	(3)	1	0	8558	1
Bin	(2)	0	1	8791	1
Bin	(2)	1	0	10387	1
Bin	(1)	0	1	18958	1
Bin	(1)	1	0	20551	1
Bin	(0)	0	1	25341	1
Bin	(0)	1	0	23745	1

Signal:

NOM_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	130518	1
Bin	1	0	132119	1

Signal:

DATA_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	20294	1
Bin	1	0	21895	1

Signal:

RES_ERR_CTRS_D

	From	To	Count	Threshold
Bin	0	1	14721	1
Bin	1	0	14709	1

Signal:

RES_ERR_CTRS_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	14720	1
Bin	1	0	14709	1

Signal:

MR_CTR_PRES_PTX_Q

	From	To	Count	Threshold
Bin	0	1	19364	1
Bin	1	0	20965	1

Signal:

MR_CTR_PRES_PRX_Q

	From	To	Count	Threshold
Bin	0	1	19759	1
Bin	1	0	21360	1

Signal:

MR_CTR_PRES_ENORM_Q

	From	To	Count	Threshold
Bin	0	1	6608	1
Bin	1	0	8209	1

Signal:

MR_CTR_PRES_EFD_Q

	From	To	Count	Threshold
Bin	0	1	6608	1
Bin	1	0	8209	1

Uncovered expressions:

Excluded expressions:

"or" expression on lines 360 to 362:

 (mr_ctr_pres_enorm_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE)) 
  <----------LHS---------->      <-------------------------------RHS-------------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression on lines 361 to 362:

 (inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE) 
  <-------------LHS-------------->       <-----------RHS----------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"or" expression on lines 366 to 368:

 (mr_ctr_pres_efd_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
  <---------LHS--------->      <----------------------------------------------RHS----------------------------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression on lines 367 to 368:

 (inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
  <-------------LHS-------------->       <--------------------------RHS-------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"or" expression on line 368:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

Covered expressions:

"=" expression on line 215:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"or" expression on line 228:

 inc_eight = '1' or dec_one = '1' 
 <-----LHS----->    <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	False	110548	1
Bin	False	True	26067	1
Bin	True	False	81279	1

"=" expression on line 228:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	136615	1
Bin	True	81279	1

"=" expression on line 228:

dec_one = '1'

	Evaluated to	Count	Threshold
Bin	False	191827	1
Bin	True	26067	1

"or" expression on line 232:

 inc_one = '1' or inc_eight = '1' or dec_one = '1' 
 <-------------LHS-------------->    <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	False	156459	1
Bin	False	True	26067	1
Bin	True	False	127222	1

"or" expression on line 232:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	182526	1
Bin	False	True	81279	1
Bin	True	False	45943	1

"=" expression on line 232:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	263805	1
Bin	True	45943	1

"=" expression on line 232:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	228469	1
Bin	True	81279	1

"=" expression on line 232:

dec_one = '1'

	Evaluated to	Count	Threshold
Bin	False	283681	1
Bin	True	26067	1

"=" expression on line 245:

mr_ctr_pres_ptx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	247968	1
Bin	True	20586	1

"=" expression on line 246:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	137395	1
Bin	True	110573	1

"and" expression on line 251:

 modif_tx_ctr = '1' and is_transmitter = '1' 
 <------LHS------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	104765	1
Bin	True	False	23347	1
Bin	True	True	83999	1

"=" expression on line 251:

modif_tx_ctr = '1'

	Evaluated to	Count	Threshold
Bin	False	191997	1
Bin	True	107346	1

"=" expression on line 251:

is_transmitter = '1'

	Evaluated to	Count	Threshold
Bin	False	110579	1
Bin	True	188764	1

"=" expression on line 252:

mr_ctr_pres_ptx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	195980	1
Bin	True	19364	1

"or" expression on line 258:

 rst_n = '0' or set_err_active = '1' 
 <---LHS--->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	17923	1
Bin	False	True	6637	1
Bin	True	False	8072	1

"=" expression on line 258:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	24560	1
Bin	True	8072	1

"=" expression on line 258:

set_err_active = '1'

	Evaluated to	Count	Threshold
Bin	False	25995	1
Bin	True	6637	1

"=" expression on line 284:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094339043	1
Bin	True	2455551	1

"=" expression on line 287:

tx_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	547116088	1
Bin	True	45126	1

"=" expression on line 303:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	62687	1
Bin	True	58075	1

"=" expression on line 314:

mr_ctr_pres_prx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	408341	1
Bin	True	22906	1

"or" expression on line 315:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	253922	1
Bin	False	True	82147	1
Bin	True	False	72272	1

"=" expression on line 315:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	336069	1
Bin	True	72272	1

"=" expression on line 315:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	326194	1
Bin	True	82147	1

"and" expression on line 320:

 modif_rx_ctr = '1' and is_receiver = '1' 
 <------LHS------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	100077	1
Bin	True	False	84053	1
Bin	True	True	69204	1

"=" expression on line 320:

modif_rx_ctr = '1'

	Evaluated to	Count	Threshold
Bin	False	259317	1
Bin	True	153257	1

"=" expression on line 320:

is_receiver = '1'

	Evaluated to	Count	Threshold
Bin	False	243293	1
Bin	True	169281	1

"=" expression on line 321:

mr_ctr_pres_prx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	323611	1
Bin	True	19759	1

"=" expression on line 329:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094339043	1
Bin	True	2455551	1

"=" expression on line 332:

rx_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	547113910	1
Bin	True	47304	1

"=" expression on line 351:

mr_ctr_pres_enorm_q = '0'

	Evaluated to	Count	Threshold
Bin	False	9810	1
Bin	True	70509	1

"=" expression on line 355:

mr_ctr_pres_efd_q = '0'

	Evaluated to	Count	Threshold
Bin	False	14616	1
Bin	True	65703	1

"or" expression on lines 360 to 362:

 (mr_ctr_pres_enorm_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE)) 
  <----------LHS---------->      <-------------------------------RHS-------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	198777	1
Bin	False	True	123942	1

"=" expression on line 360:

mr_ctr_pres_enorm_q = '1'

	Evaluated to	Count	Threshold
Bin	False	322719	1
Bin	True	6608	1

"and" expression on lines 361 to 362:

 (inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE) 
  <-------------LHS-------------->       <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	True	False	13709	1
Bin	True	True	123942	1

"or" expression on line 361:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	185068	1
Bin	False	True	85242	1
Bin	True	False	52409	1

"=" expression on line 361:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	270310	1
Bin	True	52409	1

"=" expression on line 361:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	237477	1
Bin	True	85242	1

"or" expression on lines 366 to 368:

 (mr_ctr_pres_efd_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
  <---------LHS--------->      <----------------------------------------------RHS----------------------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	309010	1
Bin	False	True	13709	1

"=" expression on line 366:

mr_ctr_pres_efd_q = '1'

	Evaluated to	Count	Threshold
Bin	False	322719	1
Bin	True	6608	1

"and" expression on lines 367 to 368:

 (inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
  <-------------LHS-------------->       <--------------------------RHS-------------------------->

	LHS	RHS	Count	Threshold
Bin	True	False	123942	1
Bin	True	True	13709	1

"or" expression on line 367:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	185068	1
Bin	False	True	85242	1
Bin	True	False	52409	1

"=" expression on line 367:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	270310	1
Bin	True	52409	1

"=" expression on line 367:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	237477	1
Bin	True	85242	1

"or" expression on line 368:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	False	123942	1
Bin	False	True	1422	1

"=" expression on line 377:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094339043	1
Bin	True	2455551	1

"=" expression on line 380:

nom_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	547137736	1
Bin	True	23478	1

"=" expression on line 388:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1094339043	1
Bin	True	2455551	1

"=" expression on line 391:

data_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	547144200	1
Bin	True	17014	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_FC_TOP.I_MAC_FC_ERR_COUNTERS

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_fc_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

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Signal assignment statement on line 216:

Signal assignment statement on line 217:

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Signal assignment statement on line 221:

Signal assignment statement on line 222:

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Signal assignment statement on line 224:

If statement on lines 228 to 229:

Signal assignment statement on line 228:

Signal assignment statement on line 229:

If statement on lines 232 to 234:

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Signal assignment statement on line 234:

If statement on lines 239 to 240:

Signal assignment statement on line 239:

Signal assignment statement on line 240:

If statement on lines 244 to 247:

Signal assignment statement on line 245:

Signal assignment statement on line 246:

Signal assignment statement on line 247:

If statement on lines 251 to 253:

Signal assignment statement on line 251:

Signal assignment statement on line 252:

Signal assignment statement on line 253:

If statement on lines 258 to 260:

Signal assignment statement on line 258:

Signal assignment statement on line 260:

If statement on lines 284 to 290:

Signal assignment statement on line 285:

If statement on lines 287 to 289:

Signal assignment statement on line 288:

If statement on lines 297 to 299:

Signal assignment statement on line 297:

Signal assignment statement on line 298:

Signal assignment statement on line 299:

If statement on lines 303 to 304:

Signal assignment statement on line 303:

Signal assignment statement on line 304:

If statement on lines 307 to 308:

Signal assignment statement on line 307:

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If statement on lines 314 to 316:

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Signal assignment statement on line 320:

Signal assignment statement on line 321:

Signal assignment statement on line 322:

If statement on lines 329 to 335:

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If statement on lines 332 to 334:

Signal assignment statement on line 333:

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Signal assignment statement on line 346:

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If statement on lines 351 to 353:

Signal assignment statement on line 351:

Signal assignment statement on line 353:

If statement on lines 355 to 357:

Signal assignment statement on line 355:

Signal assignment statement on line 357:

If statement on lines 360 to 364:

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Signal assignment statement on line 364:

If statement on lines 366 to 370:

Signal assignment statement on line 366:

Signal assignment statement on line 370:

If statement on lines 377 to 383: