NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP.G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_T

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/memory_registers/generated/control_registers_reg_map.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_REG	100.0 % (34/34)	100.0 % (48/48)	100.0 % (58/58)	100.0 % (35/35)	N.A.	N.A.	100.0 % (175/175)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MR_TOP.I_CONTROL_REGISTERS_REG_MAP.G_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_T	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

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The limit of printed items was reached (5000). Total 260336 items are not displayed.

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