NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_CLK_GATE_TXTB_RAM_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (23/23)
I_TXTB_RAM	100.0 % (52/52)	100.0 % (38/38)	100.0 % (2160/2160)	93.1 % (54/58)	N.A.	N.A.	99.8 % (2304/2308)
I_TXTB_FSM	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

I_CLK_GATE_TXTB_RAM_COMP

100.0 % (3/3)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (23/23)

I_TXTB_RAM

100.0 % (52/52)

100.0 % (38/38)

100.0 % (2160/2160)

93.1 % (54/58)

N.A.

99.8 % (2304/2308)

I_TXTB_FSM

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(6).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP	100.0 % (32/32)	100.0 % (20/20)	100.0 % (462/462)	100.0 % (53/53)	N.A.	N.A.	100.0 % (567/567)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(6).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP

100.0 % (32/32)

100.0 % (20/20)

100.0 % (462/462)

100.0 % (53/53)

N.A.

100.0 % (567/567)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

246:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
247:                             else 
248:                         '0';

Count: 23420
Threshold: 1

Signal assignment statement on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 11265
Threshold: 1

Signal assignment statement on line 248:

248: '0';
Count: 12155
Threshold: 1

If statement on lines 259 to 261:

259:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
260:                                                   else 
261:                                    (others => '0');

Count: 5049
Threshold: 1

Signal assignment statement on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 1392
Threshold: 1

Signal assignment statement on line 261:

261: (others => '0');
Count: 3657
Threshold: 1

If statement on lines 269 to 273:

269:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
270:                           else 
271:                       '1' when (mr_tst_control_tmaena = '1') 
272:                           else 
273:                       '0';

Count: 40872
Threshold: 1

Signal assignment statement on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 19866
Threshold: 1

Signal assignment statement on line 271:

271: '1' when (mr_tst_control_tmaena = '1')
Count: 240
Threshold: 1

Signal assignment statement on line 273:

273: '0';
Count: 20766
Threshold: 1

If statement on lines 280 to 284:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID) 
283:                                     else 
284:                                 '0';

Count: 44632
Threshold: 1

Signal assignment statement on line 280:

280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 89
Threshold: 1

Signal assignment statement on line 284:

284: '0';
Count: 44543
Threshold: 1

Signal assignment statement on line 286:

286: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 508
Threshold: 1

If statement on lines 294 to 302:

294:        if (rst_n = '0') then 
295:            mr_tx_command_txce_q <= '0'; 
...
301:            mr_tx_command_txca_q <= mr_tx_command_txca; 
302:        end if;

Count: 35428698
Threshold: 1

Signal assignment statement on line 295:

295: mr_tx_command_txce_q <= '0';
Count: 760440
Threshold: 1

Signal assignment statement on line 296:

296: mr_tx_command_txcr_q <= '0';
Count: 760440
Threshold: 1

Signal assignment statement on line 297:

297: mr_tx_command_txca_q <= '0';
Count: 760440
Threshold: 1

Signal assignment statement on line 299:

299: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 17333685
Threshold: 1

Signal assignment statement on line 300:

300: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 17333685
Threshold: 1

Signal assignment statement on line 301:

301: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 17333685
Threshold: 1

If statement on lines 305 to 307:

305:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
306:                                 else 
307:                             '0';

Count: 919
Threshold: 1

Signal assignment statement on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 24
Threshold: 1

Signal assignment statement on line 307:

307: '0';
Count: 895
Threshold: 1

If statement on lines 308 to 310:

308:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
309:                                 else 
310:                             '0';

Count: 6411
Threshold: 1

Signal assignment statement on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 272
Threshold: 1

Signal assignment statement on line 310:

310: '0';
Count: 6139
Threshold: 1

If statement on lines 312 to 314:

312:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
313:                         else 
314:                     '0';

Count: 1671
Threshold: 1

Signal assignment statement on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 46
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 1625
Threshold: 1

Signal assignment statement on line 317:

317: abort_or_skipped <= abort_applied;
Count: 422
Threshold: 1

Signal assignment statement on line 405:

405: txtb_parity_mismatch <= parity_mismatch;
Count: 1352
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	11265	1
Bin	False	12155	1

"if" / "when" / "else" condition on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	1392	1
Bin	False	3657	1

"if" / "when" / "else" condition on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	19866	1
Bin	False	21006	1

"if" / "when" / "else" condition on line 271:

271: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	240	1
Bin	False	20766	1

"if" / "when" / "else" condition on lines 280 to 282:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	89	1
Bin	False	44543	1

"if" / "when" / "else" condition on line 294:

294: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	760440	1
Bin	False	34668258	1

"if" / "when" / "else" condition on line 298:

298: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	17333685	1
Bin	False	17334573	1

"if" / "when" / "else" condition on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	24	1
Bin	False	895	1

"if" / "when" / "else" condition on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	272	1
Bin	False	6139	1

"if" / "when" / "else" condition on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	46	1
Bin	False	1625	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	121	1
Bin	(31)	1	0	286	1
Bin	(30)	0	1	111	1
Bin	(30)	1	0	276	1
Bin	(29)	0	1	123	1
Bin	(29)	1	0	288	1
Bin	(28)	0	1	146	1
Bin	(28)	1	0	311	1
Bin	(27)	0	1	127	1
Bin	(27)	1	0	292	1
Bin	(26)	0	1	146	1
Bin	(26)	1	0	311	1
Bin	(25)	0	1	127	1
Bin	(25)	1	0	292	1
Bin	(24)	0	1	117	1
Bin	(24)	1	0	282	1
Bin	(23)	0	1	129	1
Bin	(23)	1	0	294	1
Bin	(22)	0	1	129	1
Bin	(22)	1	0	294	1
Bin	(21)	0	1	136	1
Bin	(21)	1	0	301	1
Bin	(20)	0	1	140	1
Bin	(20)	1	0	305	1
Bin	(19)	0	1	130	1
Bin	(19)	1	0	295	1
Bin	(18)	0	1	134	1
Bin	(18)	1	0	299	1
Bin	(17)	0	1	127	1
Bin	(17)	1	0	292	1
Bin	(16)	0	1	128	1
Bin	(16)	1	0	293	1
Bin	(15)	0	1	124	1
Bin	(15)	1	0	289	1
Bin	(14)	0	1	123	1
Bin	(14)	1	0	288	1
Bin	(13)	0	1	130	1
Bin	(13)	1	0	295	1
Bin	(12)	0	1	127	1
Bin	(12)	1	0	292	1
Bin	(11)	0	1	119	1
Bin	(11)	1	0	284	1
Bin	(10)	0	1	134	1
Bin	(10)	1	0	299	1
Bin	(9)	0	1	133	1
Bin	(9)	1	0	298	1
Bin	(8)	0	1	127	1
Bin	(8)	1	0	292	1
Bin	(7)	0	1	135	1
Bin	(7)	1	0	300	1
Bin	(6)	0	1	133	1
Bin	(6)	1	0	298	1
Bin	(5)	0	1	131	1
Bin	(5)	1	0	296	1
Bin	(4)	0	1	131	1
Bin	(4)	1	0	296	1
Bin	(3)	0	1	138	1
Bin	(3)	1	0	303	1
Bin	(2)	0	1	139	1
Bin	(2)	1	0	304	1
Bin	(1)	0	1	128	1
Bin	(1)	1	0	293	1
Bin	(0)	0	1	130	1
Bin	(0)	1	0	295	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	267	1
Bin	(3)	1	0	102	1
Bin	(2)	0	1	198	1
Bin	(2)	1	0	363	1
Bin	(1)	0	1	245	1
Bin	(1)	1	0	410	1
Bin	(0)	0	1	241	1
Bin	(0)	1	0	406	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	341	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	3067	1
Bin	LOCK	1	0	3232	1
Bin	VALID	0	1	1172	1
Bin	VALID	1	0	1337	1
Bin	ERR	0	1	399	1
Bin	ERR	1	0	564	1
Bin	ARBL	0	1	17	1
Bin	ARBL	1	0	182	1
Bin	FAILED	0	1	1476	1
Bin	FAILED	1	0	1641	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	53	1
Bin	(31)	1	0	218	1
Bin	(30)	0	1	49	1
Bin	(30)	1	0	214	1
Bin	(29)	0	1	50	1
Bin	(29)	1	0	215	1
Bin	(28)	0	1	294	1
Bin	(28)	1	0	459	1
Bin	(27)	0	1	246	1
Bin	(27)	1	0	411	1
Bin	(26)	0	1	173	1
Bin	(26)	1	0	338	1
Bin	(25)	0	1	229	1
Bin	(25)	1	0	394	1
Bin	(24)	0	1	253	1
Bin	(24)	1	0	418	1
Bin	(23)	0	1	253	1
Bin	(23)	1	0	418	1
Bin	(22)	0	1	250	1
Bin	(22)	1	0	415	1
Bin	(21)	0	1	216	1
Bin	(21)	1	0	381	1
Bin	(20)	0	1	274	1
Bin	(20)	1	0	439	1
Bin	(19)	0	1	196	1
Bin	(19)	1	0	361	1
Bin	(18)	0	1	167	1
Bin	(18)	1	0	332	1
Bin	(17)	0	1	182	1
Bin	(17)	1	0	347	1
Bin	(16)	0	1	131	1
Bin	(16)	1	0	296	1
Bin	(15)	0	1	198	1
Bin	(15)	1	0	363	1
Bin	(14)	0	1	117	1
Bin	(14)	1	0	282	1
Bin	(13)	0	1	175	1
Bin	(13)	1	0	340	1
Bin	(12)	0	1	218	1
Bin	(12)	1	0	383	1
Bin	(11)	0	1	268	1
Bin	(11)	1	0	433	1
Bin	(10)	0	1	166	1
Bin	(10)	1	0	331	1
Bin	(9)	0	1	275	1
Bin	(9)	1	0	440	1
Bin	(8)	0	1	196	1
Bin	(8)	1	0	361	1
Bin	(7)	0	1	340	1
Bin	(7)	1	0	505	1
Bin	(6)	0	1	321	1
Bin	(6)	1	0	486	1
Bin	(5)	0	1	261	1
Bin	(5)	1	0	426	1
Bin	(4)	0	1	215	1
Bin	(4)	1	0	380	1
Bin	(3)	0	1	231	1
Bin	(3)	1	0	396	1
Bin	(2)	0	1	257	1
Bin	(2)	1	0	422	1
Bin	(1)	0	1	355	1
Bin	(1)	1	0	520	1
Bin	(0)	0	1	329	1
Bin	(0)	1	0	494	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	422	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	385	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	511	1
Bin	1	0	676	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	254	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	385	1
Bin	1	0	220	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	385	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	226	1
Bin	(31)	1	0	381	1
Bin	(30)	0	1	317	1
Bin	(30)	1	0	472	1
Bin	(29)	0	1	201	1
Bin	(29)	1	0	356	1
Bin	(28)	0	1	776	1
Bin	(28)	1	0	925	1
Bin	(27)	0	1	444	1
Bin	(27)	1	0	594	1
Bin	(26)	0	1	475	1
Bin	(26)	1	0	625	1
Bin	(25)	0	1	720	1
Bin	(25)	1	0	872	1
Bin	(24)	0	1	687	1
Bin	(24)	1	0	838	1
Bin	(23)	0	1	678	1
Bin	(23)	1	0	827	1
Bin	(22)	0	1	481	1
Bin	(22)	1	0	631	1
Bin	(21)	0	1	717	1
Bin	(21)	1	0	867	1
Bin	(20)	0	1	719	1
Bin	(20)	1	0	870	1
Bin	(19)	0	1	697	1
Bin	(19)	1	0	846	1
Bin	(18)	0	1	635	1
Bin	(18)	1	0	784	1
Bin	(17)	0	1	585	1
Bin	(17)	1	0	737	1
Bin	(16)	0	1	344	1
Bin	(16)	1	0	498	1
Bin	(15)	0	1	639	1
Bin	(15)	1	0	792	1
Bin	(14)	0	1	476	1
Bin	(14)	1	0	630	1
Bin	(13)	0	1	442	1
Bin	(13)	1	0	596	1
Bin	(12)	0	1	452	1
Bin	(12)	1	0	606	1
Bin	(11)	0	1	651	1
Bin	(11)	1	0	804	1
Bin	(10)	0	1	435	1
Bin	(10)	1	0	588	1
Bin	(9)	0	1	713	1
Bin	(9)	1	0	863	1
Bin	(8)	0	1	690	1
Bin	(8)	1	0	844	1
Bin	(7)	0	1	741	1
Bin	(7)	1	0	883	1
Bin	(6)	0	1	999	1
Bin	(6)	1	0	1148	1
Bin	(5)	0	1	742	1
Bin	(5)	1	0	894	1
Bin	(4)	0	1	586	1
Bin	(4)	1	0	741	1
Bin	(3)	0	1	528	1
Bin	(3)	1	0	675	1
Bin	(2)	0	1	687	1
Bin	(2)	1	0	836	1
Bin	(1)	0	1	1035	1
Bin	(1)	1	0	1182	1
Bin	(0)	0	1	822	1
Bin	(0)	1	0	967	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	254	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	301	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	2882	1
Bin	1	0	3047	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	512	1
Bin	1	0	677	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	189	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	272	1
Bin	1	0	437	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	11265	1
Bin	1	0	11430	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	20106	1
Bin	1	0	20271	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	336637	1
Bin	1	0	336802	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	511	1
Bin	1	0	676	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 246:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	11650	1
Bin	True	False	60	1
Bin	True	True	11265	1

"=" expression on line 246:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	12095	1
Bin	True	11325	1

"=" expression on line 246:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	505	1
Bin	True	22915	1

"=" expression on line 259:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	3657	1
Bin	True	1392	1

"or" expression on line 269:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	21006	1
Bin	False	True	11265	1
Bin	True	False	8601	1

"=" expression on line 269:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	32271	1
Bin	True	8601	1

"=" expression on line 269:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	29607	1
Bin	True	11265	1

"=" expression on line 271:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	20766	1
Bin	True	240	1

"and" expression on lines 280 to 282:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	2667	1
Bin	True	False	981	1
Bin	True	True	89	1

"and" expression on lines 280 to 281:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	17836	1
Bin	True	False	1103	1
Bin	True	True	1070	1

"=" expression on line 280:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	42459	1
Bin	True	2173	1

"=" expression on line 281:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	25726	1
Bin	True	18906	1

"=" expression on line 282:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	41876	1
Bin	True	2756	1

"=" expression on line 294:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	34668258	1
Bin	True	760440	1

"and" expression on line 305:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	96	1
Bin	True	False	116	1
Bin	True	True	24	1

"=" expression on line 305:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	779	1
Bin	True	140	1

"=" expression on line 305:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	799	1
Bin	True	120	1

"and" expression on line 308:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	221	1
Bin	True	False	2737	1
Bin	True	True	272	1

"=" expression on line 308:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	3402	1
Bin	True	3009	1

"=" expression on line 308:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	5918	1
Bin	True	493	1

"and" expression on line 312:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	122	1
Bin	True	False	466	1
Bin	True	True	46	1

"=" expression on line 312:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	1159	1
Bin	True	512	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	1503	1
Bin	True	168	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(6).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/ctu_can_fd_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

Signal assignment statement on line 246:

Signal assignment statement on line 248:

If statement on lines 259 to 261:

Signal assignment statement on line 259:

Signal assignment statement on line 261:

If statement on lines 269 to 273:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 273:

If statement on lines 280 to 284:

Signal assignment statement on line 280:

Signal assignment statement on line 284:

Signal assignment statement on line 286:

If statement on lines 294 to 302:

Signal assignment statement on line 295:

Signal assignment statement on line 296:

Signal assignment statement on line 297:

Signal assignment statement on line 299:

Signal assignment statement on line 300:

Signal assignment statement on line 301:

If statement on lines 305 to 307:

Signal assignment statement on line 305:

Signal assignment statement on line 307:

If statement on lines 308 to 310:

Signal assignment statement on line 308:

Signal assignment statement on line 310:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

Signal assignment statement on line 317:

Signal assignment statement on line 405:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

"if" / "when" / "else" condition on line 259:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on line 271:

"if" / "when" / "else" condition on lines 280 to 282:

"if" / "when" / "else" condition on line 294:

"if" / "when" / "else" condition on line 298:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 308:

"if" / "when" / "else" condition on line 312:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: