Covered statements:
If statement on lines 757 to 759:
757: tran_frame_type_i <= FD_CAN when (tran_frame_type = FD_CAN and mr_mode_fde = '1')
758: else
759: NORMAL_CAN;
Count: 10629
Threshold: 1
Signal assignment statement on line 757:
757: tran_frame_type_i <= FD_CAN when (tran_frame_type = FD_CAN and mr_mode_fde = '1')
Count: 2694
Threshold: 1
Signal assignment statement on line 759:
759: NORMAL_CAN;
Count: 7935
Threshold: 1
If statement on lines 761 to 764:
761: no_data_transmitter <= '1' when (tran_dlc = "0000" or
762: (tran_is_rtr = RTR_FRAME and tran_frame_type_i = NORMAL_CAN))
763: else
764: '0';
Count: 22402
Threshold: 1
Signal assignment statement on line 761:
761: no_data_transmitter <= '1' when (tran_dlc = "0000" or
Count: 10315
Threshold: 1
Signal assignment statement on line 764:
764: '0';
Count: 12087
Threshold: 1
If statement on lines 766 to 768:
766: no_data_receiver <= '1' when (rec_is_rtr = RTR_FRAME or rec_dlc_d = "0000")
767: else
768: '0';
Count: 5079505
Threshold: 1
Signal assignment statement on line 766:
766: no_data_receiver <= '1' when (rec_is_rtr = RTR_FRAME or rec_dlc_d = "0000")
Count: 1070956
Threshold: 1
Signal assignment statement on line 768:
768: '0';
Count: 4008549
Threshold: 1
If statement on lines 770 to 774:
770: no_data_field <= '1' when (is_transmitter = '1' and no_data_transmitter = '1')
771: else
772: '1' when (is_receiver = '1' and no_data_receiver = '1')
773: else
774: '0';
Count: 963457
Threshold: 1
Signal assignment statement on line 770:
770: no_data_field <= '1' when (is_transmitter = '1' and no_data_transmitter = '1')
Count: 42137
Threshold: 1
Signal assignment statement on line 772:
772: '1' when (is_receiver = '1' and no_data_receiver = '1')
Count: 260934
Threshold: 1
Signal assignment statement on line 774:
774: '0';
Count: 660386
Threshold: 1
If statement on lines 776 to 778:
776: go_to_suspend <= '1' when (is_err_passive = '1' and is_transmitter = '1')
777: else
778: '0';
Count: 45783
Threshold: 1
Signal assignment statement on line 776:
776: go_to_suspend <= '1' when (is_err_passive = '1' and is_transmitter = '1')
Count: 2673
Threshold: 1
Signal assignment statement on line 778:
778: '0';
Count: 43110
Threshold: 1
If statement on lines 780 to 782:
780: ide_is_arbitration <= '1' when (tran_ident_type = EXTENDED or is_receiver = '1')
781: else
782: '0';
Count: 71656
Threshold: 1
Signal assignment statement on line 780:
780: ide_is_arbitration <= '1' when (tran_ident_type = EXTENDED or is_receiver = '1')
Count: 33977
Threshold: 1
Signal assignment statement on line 782:
782: '0';
Count: 37679
Threshold: 1
If statement on lines 784 to 787:
784: arbitration_lost_condition <= '1' when (is_transmitter = '1' and tx_data_wbs = RECESSIVE and
785: rx_data_nbs = DOMINANT and rx_trigger = '1')
786: else
787: '0';
Count: 24919251
Threshold: 1
Signal assignment statement on line 784:
784: arbitration_lost_condition <= '1' when (is_transmitter = '1' and tx_data_wbs = RECESSIVE and
Count: 29321
Threshold: 1
Signal assignment statement on line 787:
787: '0';
Count: 24889930
Threshold: 1
If statement on lines 789 to 791:
789: tx_failed <= '1' when (mr_settings_rtrle = '1' and retr_limit_reached = '1')
790: else
791: '0';
Count: 11826
Threshold: 1
Signal assignment statement on line 789:
789: tx_failed <= '1' when (mr_settings_rtrle = '1' and retr_limit_reached = '1')
Count: 2647
Threshold: 1
Signal assignment statement on line 791:
791: '0';
Count: 9179
Threshold: 1
If statement on lines 793 to 797:
793: is_fd_frame <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN)
794: else
795: '1' when (is_receiver = '1' and rec_frame_type = FD_CAN)
796: else
797: '0';
Count: 168576
Threshold: 1
Signal assignment statement on line 793:
793: is_fd_frame <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN)
Count: 35137
Threshold: 1
Signal assignment statement on line 795:
795: '1' when (is_receiver = '1' and rec_frame_type = FD_CAN)
Count: 30872
Threshold: 1
Signal assignment statement on line 797:
797: '0';
Count: 102567
Threshold: 1
If statement on lines 799 to 801:
799: go_to_stuff_count <= '1' when (mr_settings_nisofd = ISO_FD and is_fd_frame = '1')
800: else
801: '0';
Count: 91044
Threshold: 1
Signal assignment statement on line 799:
799: go_to_stuff_count <= '1' when (mr_settings_nisofd = ISO_FD and is_fd_frame = '1')
Count: 42981
Threshold: 1
Signal assignment statement on line 801:
801: '0';
Count: 48063
Threshold: 1
If statement on lines 803 to 805:
803: frame_start <= '1' when (tran_frame_valid = '1' and go_to_suspend = '0') else
804: '1' when (rx_data_nbs = DOMINANT) else
805: '0';
Count: 2857508
Threshold: 1
Signal assignment statement on line 803:
803: frame_start <= '1' when (tran_frame_valid = '1' and go_to_suspend = '0') else
Count: 1134139
Threshold: 1
Signal assignment statement on line 804:
804: '1' when (rx_data_nbs = DOMINANT) else
Count: 849370
Threshold: 1
Signal assignment statement on line 805:
805: '0';
Count: 873999
Threshold: 1
If statement on lines 807 to 811:
807: tx_dominant_ack <= '1' when (crc_match = '1') and
808: ((is_receiver = '1' and mr_mode_acf = '0') or
809: (is_transmitter = '1' and mr_mode_sam = '1'))
810: else
811: '0';
Count: 163620
Threshold: 1
Signal assignment statement on line 807:
807: tx_dominant_ack <= '1' when (crc_match = '1') and
Count: 15138
Threshold: 1
Signal assignment statement on line 811:
811: '0';
Count: 148482
Threshold: 1
If statement on lines 817 to 819:
817: allow_flipped_ack <= '1' when (tx_dominant_ack = '0' or mr_mode_bmm = '1')
818: else
819: '0';
Count: 35109
Threshold: 1
Signal assignment statement on line 817:
817: allow_flipped_ack <= '1' when (tx_dominant_ack = '0' or mr_mode_bmm = '1')
Count: 18380
Threshold: 1
Signal assignment statement on line 819:
819: '0';
Count: 16729
Threshold: 1
If statement on lines 825 to 833:
825: block_txtb_unlock <= '1' when (curr_state = s_pc_act_err_flag or
826: curr_state = s_pc_pas_err_flag or
...
832: else
833: '0';
Count: 839377
Threshold: 1
Signal assignment statement on line 825:
825: block_txtb_unlock <= '1' when (curr_state = s_pc_act_err_flag or
Count: 79815
Threshold: 1
Signal assignment statement on line 833:
833: '0';
Count: 759562
Threshold: 1
If statement on lines 835 to 838:
835: pex_on_fdf_enable <= '1' when (mr_mode_fde = FDE_DISABLE and
836: mr_settings_pex = PROTOCOL_EXCEPTION_ENABLED)
837: else
838: '0';
Count: 3746
Threshold: 1
Signal assignment statement on line 835:
835: pex_on_fdf_enable <= '1' when (mr_mode_fde = FDE_DISABLE and
Count: 35
Threshold: 1
Signal assignment statement on line 838:
838: '0';
Count: 3711
Threshold: 1
If statement on lines 840 to 843:
840: pex_on_res_enable <= '1' when (mr_mode_fde = FDE_ENABLE and
841: mr_settings_pex = PROTOCOL_EXCEPTION_ENABLED)
842: else
843: '0';
Count: 3746
Threshold: 1
Signal assignment statement on line 840:
840: pex_on_res_enable <= '1' when (mr_mode_fde = FDE_ENABLE and
Count: 72
Threshold: 1
Signal assignment statement on line 843:
843: '0';
Count: 3674
Threshold: 1
If statement on lines 848 to 853:
848: integ_restart_edge <= '0' when (mr_mode_fde = FDE_DISABLE and
849: mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED)
850: else
851: '1' when (sync_edge = '1')
852: else
853: '0';
Count: 3130675
Threshold: 1
Signal assignment statement on line 848:
848: integ_restart_edge <= '0' when (mr_mode_fde = FDE_DISABLE and
Count: 7442
Threshold: 1
Signal assignment statement on line 851:
851: '1' when (sync_edge = '1')
Count: 1559043
Threshold: 1
Signal assignment statement on line 853:
853: '0';
Count: 1564190
Threshold: 1
Signal assignment statement on line 858:
858: tran_data_length_i <= to_integer(unsigned(tran_data_length));
Count: 17533
Threshold: 1
Sequential statement on lines 860 to 870:
860: with tran_data_length_i select txtb_num_words_gate <=
861: 4 when 1 | 2 | 3 | 4,
...
869: 19 when 64,
870: 0 when others;
Count: 14331
Threshold: 1
Signal assignment statement on line 861:
861: 4 when 1 | 2 | 3 | 4,
Count: 3694
Threshold: 1
Signal assignment statement on line 862:
862: 5 when 5 | 6 | 7 | 8,
Count: 2576
Threshold: 1
Signal assignment statement on line 863:
863: 6 when 12,
Count: 293
Threshold: 1
Signal assignment statement on line 864:
864: 7 when 16,
Count: 135
Threshold: 1
Signal assignment statement on line 865:
865: 8 when 20,
Count: 68
Threshold: 1
Signal assignment statement on line 866:
866: 9 when 24,
Count: 138
Threshold: 1
Signal assignment statement on line 867:
867: 11 when 32,
Count: 92
Threshold: 1
Signal assignment statement on line 868:
868: 15 when 48,
Count: 102
Threshold: 1
Signal assignment statement on line 869:
869: 19 when 64,
Count: 86
Threshold: 1
Signal assignment statement on line 870:
870: 0 when others;
Count: 7147
Threshold: 1
If statement on lines 872 to 874:
872: txtb_gate_mem_read <= '1' when (txtb_ptr_d > txtb_num_words_gate)
873: else
874: '0';
Count: 114452
Threshold: 1
Signal assignment statement on line 872:
872: txtb_gate_mem_read <= '1' when (txtb_ptr_d > txtb_num_words_gate)
Count: 17003
Threshold: 1
Signal assignment statement on line 874:
874: '0';
Count: 97449
Threshold: 1
If statement on lines 879 to 885:
879: crc_use_21 <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN and
880: to_integer(unsigned(tran_data_length)) > 16)
...
884: else
885: '0';
Count: 292102
Threshold: 1
Signal assignment statement on line 879:
879: crc_use_21 <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN and
Count: 32796
Threshold: 1
Signal assignment statement on line 882:
882: '1' when (is_receiver = '1' and rec_frame_type = FD_CAN and
Count: 20133
Threshold: 1
Signal assignment statement on line 885:
885: '0';
Count: 239173
Threshold: 1
If statement on lines 887 to 893:
887: crc_use_17 <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN and
888: crc_use_21 = '0')
...
892: else
893: '0';
Count: 218210
Threshold: 1
Signal assignment statement on line 887:
887: crc_use_17 <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN and
Count: 25739
Threshold: 1
Signal assignment statement on line 890:
890: '1' when (is_receiver = '1' and rec_frame_type = FD_CAN and
Count: 30870
Threshold: 1
Signal assignment statement on line 893:
893: '0';
Count: 161601
Threshold: 1
If statement on lines 895 to 897:
895: crc_src_i <= C_CRC21_SRC when (crc_use_21 = '1') else
896: C_CRC17_SRC when (crc_use_17 = '1') else
897: C_CRC15_SRC;
Count: 124177
Threshold: 1
Signal assignment statement on line 895:
895: crc_src_i <= C_CRC21_SRC when (crc_use_21 = '1') else
Count: 49644
Threshold: 1
Signal assignment statement on line 896:
896: C_CRC17_SRC when (crc_use_17 = '1') else
Count: 28318
Threshold: 1
Signal assignment statement on line 897:
897: C_CRC15_SRC;
Count: 46215
Threshold: 1
If statement on lines 899 to 901:
899: crc_length_i <= C_CRC15_DURATION when (crc_src_i = C_CRC15_SRC) else
900: C_CRC17_DURATION when (crc_src_i = C_CRC17_SRC) else
901: C_CRC21_DURATION;
Count: 99355
Threshold: 1
Signal assignment statement on line 899:
899: crc_length_i <= C_CRC15_DURATION when (crc_src_i = C_CRC15_SRC) else
Count: 44614
Threshold: 1
Signal assignment statement on line 900:
900: C_CRC17_DURATION when (crc_src_i = C_CRC17_SRC) else
Count: 28318
Threshold: 1
Signal assignment statement on line 901:
901: C_CRC21_DURATION;
Count: 26423
Threshold: 1
If statement on lines 931 to 932:
931: data_length_c <= tran_data_length when (is_transmitter = '1') else
932: rec_data_length_c;
Count: 5237363
Threshold: 1
Signal assignment statement on line 931:
931: data_length_c <= tran_data_length when (is_transmitter = '1') else
Count: 2284437
Threshold: 1
Signal assignment statement on line 932:
932: rec_data_length_c;
Count: 2952926
Threshold: 1
Signal assignment statement on line 935:
935: data_length_shifted_c <= data_length_c & "000";
Count: 2952816
Threshold: 1
Signal assignment statement on line 938:
938: data_length_sub_c <= unsigned(data_length_shifted_c) - 1;
Count: 2954417
Threshold: 1
Signal assignment statement on lines 941 to 942:
941: data_length_bits_c <= std_logic_vector(
942: data_length_sub_c(ctrl_ctr_pload_val'length - 1 downto 0));
Count: 2950840
Threshold: 1
If statement on lines 950 to 958:
950: if (rst_n = '0') then
951: mr_command_ercrst_q <= '0';
...
957: end if;
958: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 951:
951: mr_command_ercrst_q <= '0';
Count: 2422674
Threshold: 1
If statement on lines 953 to 957:
953: if (mr_command_ercrst = '1') then
954: mr_command_ercrst_q <= '1';
955: elsif (rx_trigger = '1' and clr_bus_off_rst_flg = '1') then
956: mr_command_ercrst_q <= '0';
957: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 954:
954: mr_command_ercrst_q <= '1';
Count: 170
Threshold: 1
Signal assignment statement on line 956:
956: mr_command_ercrst_q <= '0';
Count: 170
Threshold: 1
Signal assignment statement on line 970:
970: next_state <= curr_state;
Count: 5165927
Threshold: 1
If statement on lines 972 to 1227:
972: if (err_frm_req = '1') then
973: if (mr_mode_rom = ROM_DISABLED) then
...
1226: ---------------------------------------------------------------------------------------
1227: when s_pc_suspend =>
Count: 5165927
Threshold: 1
If statement on lines 973 to 981:
973: if (mr_mode_rom = ROM_DISABLED) then
974: if (is_err_active = '1') then
...
980: next_state <= s_pc_integrating;
981: end if;
Count: 32430
Threshold: 1
If statement on lines 974 to 978:
974: if (is_err_active = '1') then
975: next_state <= s_pc_act_err_flag;
976: else
977: next_state <= s_pc_pas_err_flag;
978: end if;
Count: 28262
Threshold: 1
Signal assignment statement on line 975:
975: next_state <= s_pc_act_err_flag;
Count: 21117
Threshold: 1
Signal assignment statement on line 977:
977: next_state <= s_pc_pas_err_flag;
Count: 7145
Threshold: 1
Signal assignment statement on line 980:
980: next_state <= s_pc_integrating;
Count: 4168
Threshold: 1
Sequential statement on lines 984 to 1239:
984: case curr_state is
985:
...
1238: end if;
1239:
Count: 5133497
Threshold: 1
Signal assignment statement on line 990:
990: next_state <= s_pc_integrating;
Count: 29881
Threshold: 1
If statement on lines 996 to 998:
996: if (ctrl_ctr_zero = '1') then
997: next_state <= s_pc_idle;
998: end if;
Count: 38688
Threshold: 1
Signal assignment statement on line 997:
997: next_state <= s_pc_idle;
Count: 10791
Threshold: 1
Signal assignment statement on line 1004:
1004: next_state <= s_pc_base_id;
Count: 82520
Threshold: 1
If statement on lines 1010 to 1012:
1010: if (ctrl_ctr_zero = '1') then
1011: next_state <= s_pc_rtr_srr_r1;
1012: end if;
Count: 645915
Threshold: 1
Signal assignment statement on line 1011:
1011: next_state <= s_pc_rtr_srr_r1;
Count: 90437
Threshold: 1
Signal assignment statement on line 1018:
1018: next_state <= s_pc_ide;
Count: 142336
Threshold: 1
If statement on lines 1024 to 1028:
1024: if (rx_data_nbs = DOMINANT) then
1025: next_state <= s_pc_edl_r0;
1026: else
1027: next_state <= s_pc_ext_id;
1028: end if;
Count: 75840
Threshold: 1
Signal assignment statement on line 1025:
1025: next_state <= s_pc_edl_r0;
Count: 36944
Threshold: 1
Signal assignment statement on line 1027:
1027: next_state <= s_pc_ext_id;
Count: 38896
Threshold: 1
If statement on lines 1034 to 1036:
1034: if (ctrl_ctr_zero = '1') then
1035: next_state <= s_pc_rtr_r1;
1036: end if;
Count: 191977
Threshold: 1
Signal assignment statement on line 1035:
1035: next_state <= s_pc_rtr_r1;
Count: 24816
Threshold: 1
Signal assignment statement on line 1042:
1042: next_state <= s_pc_edl_r1;
Count: 41358
Threshold: 1
If statement on lines 1048 to 1056:
1048: if (rx_data_nbs = DOMINANT) then
1049: next_state <= s_pc_r0_ext;
...
1055: end if;
1056: end if;
Count: 33868
Threshold: 1
Signal assignment statement on line 1049:
1049: next_state <= s_pc_r0_ext;
Count: 21624
Threshold: 1
If statement on lines 1051 to 1055:
1051: if (pex_on_fdf_enable = '1') then
1052: next_state <= s_pc_integrating;
1053: else
1054: next_state <= s_pc_r0_fd;
1055: end if;
Count: 12244
Threshold: 1
Signal assignment statement on line 1052:
1052: next_state <= s_pc_integrating;
Count: 16
Threshold: 1
Signal assignment statement on line 1054:
1054: next_state <= s_pc_r0_fd;
Count: 12228
Threshold: 1
Signal assignment statement on line 1062:
1062: next_state <= s_pc_dlc;
Count: 12826
Threshold: 1
If statement on lines 1068 to 1072:
1068: if (rx_data_nbs = RECESSIVE and pex_on_res_enable = '1') then
1069: next_state <= s_pc_integrating;
1070: else
1071: next_state <= s_pc_brs;
1072: end if;
Count: 89288
Threshold: 1
Signal assignment statement on line 1069:
1069: next_state <= s_pc_integrating;
Count: 194
Threshold: 1
Signal assignment statement on line 1071:
1071: next_state <= s_pc_brs;
Count: 89094
Threshold: 1
If statement on lines 1078 to 1087:
1078: if (rx_data_nbs = DOMINANT) then
1079: next_state <= s_pc_dlc;
...
1086: end if;
1087: end if;
Count: 56788
Threshold: 1
Signal assignment statement on line 1079:
1079: next_state <= s_pc_dlc;
Count: 34769
Threshold: 1
If statement on lines 1082 to 1086:
1082: if (pex_on_fdf_enable = '1') then
1083: next_state <= s_pc_integrating;
1084: else
1085: next_state <= s_pc_r0_fd;
1086: end if;
Count: 22019
Threshold: 1
Signal assignment statement on line 1083:
1083: next_state <= s_pc_integrating;
Count: 16
Threshold: 1
Signal assignment statement on line 1085:
1085: next_state <= s_pc_r0_fd;
Count: 22003
Threshold: 1
Signal assignment statement on line 1093:
1093: next_state <= s_pc_esi;
Count: 48838
Threshold: 1
Signal assignment statement on line 1099:
1099: next_state <= s_pc_dlc;
Count: 49545
Threshold: 1
If statement on lines 1105 to 1115:
1105: if (ctrl_ctr_zero = '1') then
1106: if (no_data_field = '1') then
...
1114: end if;
1115: end if;
Count: 207624
Threshold: 1
If statement on lines 1106 to 1114:
1106: if (no_data_field = '1') then
1107: if (go_to_stuff_count = '1') then
...
1113: next_state <= s_pc_data;
1114: end if;
Count: 84965
Threshold: 1
If statement on lines 1107 to 1111:
1107: if (go_to_stuff_count = '1') then
1108: next_state <= s_pc_stuff_count;
1109: else
1110: next_state <= s_pc_crc;
1111: end if;
Count: 34411
Threshold: 1
Signal assignment statement on line 1108:
1108: next_state <= s_pc_stuff_count;
Count: 6391
Threshold: 1
Signal assignment statement on line 1110:
1110: next_state <= s_pc_crc;
Count: 28020
Threshold: 1
Signal assignment statement on line 1113:
1113: next_state <= s_pc_data;
Count: 50554
Threshold: 1
If statement on lines 1121 to 1127:
1121: if (ctrl_ctr_zero = '1') then
1122: if (go_to_stuff_count = '1') then
...
1126: end if;
1127: end if;
Count: 1937716
Threshold: 1
If statement on lines 1122 to 1126:
1122: if (go_to_stuff_count = '1') then
1123: next_state <= s_pc_stuff_count;
1124: else
1125: next_state <= s_pc_crc;
1126: end if;
Count: 64398
Threshold: 1
Signal assignment statement on line 1123:
1123: next_state <= s_pc_stuff_count;
Count: 41212
Threshold: 1
Signal assignment statement on line 1125:
1125: next_state <= s_pc_crc;
Count: 23186
Threshold: 1
If statement on lines 1133 to 1135:
1133: if (ctrl_ctr_zero = '1') then
1134: next_state <= s_pc_crc;
1135: end if;
Count: 84266
Threshold: 1
Signal assignment statement on line 1134:
1134: next_state <= s_pc_crc;
Count: 32480
Threshold: 1
If statement on lines 1141 to 1143:
1141: if (ctrl_ctr_zero = '1') then
1142: next_state <= s_pc_crc_delim;
1143: end if;
Count: 437725
Threshold: 1
Signal assignment statement on line 1142:
1142: next_state <= s_pc_crc_delim;
Count: 88854
Threshold: 1
If statement on lines 1149 to 1153:
1149: if (is_fd_frame = '1') then
1150: next_state <= s_pc_ack_fd_1;
1151: else
1152: next_state <= s_pc_ack;
1153: end if;
Count: 78298
Threshold: 1
Signal assignment statement on line 1150:
1150: next_state <= s_pc_ack_fd_1;
Count: 30711
Threshold: 1
Signal assignment statement on line 1152:
1152: next_state <= s_pc_ack;
Count: 47587
Threshold: 1
Signal assignment statement on line 1159:
1159: next_state <= s_pc_ack_delim;
Count: 33730
Threshold: 1
Signal assignment statement on line 1165:
1165: next_state <= s_pc_ack_fd_2;
Count: 22841
Threshold: 1
Signal assignment statement on line 1171:
1171: next_state <= s_pc_ack_delim;
Count: 22780
Threshold: 1
Signal assignment statement on line 1177:
1177: next_state <= s_pc_eof;
Count: 44983
Threshold: 1
If statement on lines 1184 to 1194:
1184: if (ctrl_ctr_zero = '1') then
1185: if (rx_data_nbs = RECESSIVE) then
...
1193: end if;
1194: end if;
Count: 54626
Threshold: 1
If statement on lines 1185 to 1193:
1185: if (rx_data_nbs = RECESSIVE) then
1186: next_state <= s_pc_intermission;
...
1192: end if;
1193: end if;
Count: 26168
Threshold: 1
Signal assignment statement on line 1186:
1186: next_state <= s_pc_intermission;
Count: 25997
Threshold: 1
If statement on lines 1188 to 1192:
1188: if (mr_mode_rom = ROM_DISABLED) then
1189: next_state <= s_pc_ovr_flag;
1190: else
1191: next_state <= s_pc_integrating;
1192: end if;
Count: 154
Threshold: 1
Signal assignment statement on line 1189:
1189: next_state <= s_pc_ovr_flag;
Count: 150
Threshold: 1
Signal assignment statement on line 1191:
1191: next_state <= s_pc_integrating;
Count: 4
Threshold: 1
If statement on lines 1200 to 1222:
1200: if (is_bus_off = '1') then
1201: next_state <= s_pc_reintegrating_wait;
...
1221: end if;
1222: end if;
Count: 169577
Threshold: 1
Signal assignment statement on line 1201:
1201: next_state <= s_pc_reintegrating_wait;
Count: 216
Threshold: 1
If statement on lines 1205 to 1213:
1205: if (rx_data_nbs = DOMINANT) then
1206: next_state <= s_pc_base_id;
...
1212: next_state <= s_pc_idle;
1213: end if;
Count: 104161
Threshold: 1
Signal assignment statement on line 1206:
1206: next_state <= s_pc_base_id;
Count: 936
Threshold: 1
Signal assignment statement on line 1208:
1208: next_state <= s_pc_suspend;
Count: 5829
Threshold: 1
Signal assignment statement on line 1210:
1210: next_state <= s_pc_sof;
Count: 19786
Threshold: 1
Signal assignment statement on line 1212:
1212: next_state <= s_pc_idle;
Count: 77610
Threshold: 1
If statement on lines 1217 to 1221:
1217: if (mr_mode_rom = ROM_DISABLED) then
1218: next_state <= s_pc_ovr_flag;
1219: else
1220: next_state <= s_pc_integrating;
1221: end if;
Count: 339
Threshold: 1
Signal assignment statement on line 1218:
1218: next_state <= s_pc_ovr_flag;
Count: 310
Threshold: 1
Signal assignment statement on line 1220:
1220: next_state <= s_pc_integrating;
Count: 29
Threshold: 1
If statement on lines 1228 to 1238:
1228: if (rx_data_nbs = DOMINANT) then
1229: next_state <= s_pc_base_id;
...
1237: end if;
1238: end if;
Count: 8519
Threshold: 1
Signal assignment statement on line 1229:
1229: next_state <= s_pc_base_id;
Count: 93
Threshold: 1
If statement on lines 1233 to 1237:
1233: if (tran_frame_valid = '1') then
1234: next_state <= s_pc_sof;
1235: else
1236: next_state <= s_pc_idle;
1237: end if;
Count: 5547
Threshold: 1
Signal assignment statement on line 1234:
1234: next_state <= s_pc_sof;
Count: 793
Threshold: 1
Signal assignment statement on line 1236:
1236: next_state <= s_pc_idle;
Count: 4754
Threshold: 1
If statement on lines 1244 to 1250:
1244: if (is_bus_off = '1') then
1245: next_state <= s_pc_reintegrating_wait;
...
1249: next_state <= s_pc_sof;
1250: end if;
Count: 221431
Threshold: 1
Signal assignment statement on line 1245:
1245: next_state <= s_pc_reintegrating_wait;
Count: 6775
Threshold: 1
Signal assignment statement on line 1247:
1247: next_state <= s_pc_base_id;
Count: 30059
Threshold: 1
Signal assignment statement on line 1249:
1249: next_state <= s_pc_sof;
Count: 20151
Threshold: 1
If statement on lines 1256 to 1258:
1256: if (mr_command_ercrst_q = '1') then
1257: next_state <= s_pc_reintegrating;
1258: end if;
Count: 634
Threshold: 1
Signal assignment statement on line 1257:
1257: next_state <= s_pc_reintegrating;
Count: 170
Threshold: 1
If statement on lines 1264 to 1266:
1264: if (reinteg_ctr_expired = '1' and ctrl_ctr_zero = '1') then
1265: next_state <= s_pc_idle;
1266: end if;
Count: 45940
Threshold: 1
Signal assignment statement on line 1265:
1265: next_state <= s_pc_idle;
Count: 170
Threshold: 1
If statement on lines 1272 to 1274:
1272: if (ctrl_ctr_zero = '1') then
1273: next_state <= s_pc_err_delim_wait;
1274: end if;
Count: 64544
Threshold: 1
Signal assignment statement on line 1273:
1273: next_state <= s_pc_err_delim_wait;
Count: 19712
Threshold: 1
If statement on lines 1280 to 1282:
1280: if (ctrl_ctr_zero = '1') then
1281: next_state <= s_pc_err_delim_wait;
1282: end if;
Count: 23957
Threshold: 1
Signal assignment statement on line 1281:
1281: next_state <= s_pc_err_delim_wait;
Count: 7987
Threshold: 1
If statement on lines 1288 to 1292:
1288: if (rx_data_nbs = RECESSIVE) then
1289: next_state <= s_pc_err_delim;
1290: elsif (ctrl_ctr_zero = '1') then
1291: next_state <= s_pc_err_flag_too_long;
1292: end if;
Count: 76738
Threshold: 1
Signal assignment statement on line 1289:
1289: next_state <= s_pc_err_delim;
Count: 35663
Threshold: 1
Signal assignment statement on line 1291:
1291: next_state <= s_pc_err_flag_too_long;
Count: 20943
Threshold: 1
If statement on lines 1298 to 1300:
1298: if (rx_data_nbs = RECESSIVE) then
1299: next_state <= s_pc_err_delim;
1300: end if;
Count: 618
Threshold: 1
Signal assignment statement on line 1299:
1299: next_state <= s_pc_err_delim;
Count: 146
Threshold: 1
If statement on lines 1306 to 1308:
1306: if (rx_data_nbs = RECESSIVE) then
1307: next_state <= s_pc_ovr_delim;
1308: end if;
Count: 122
Threshold: 1
Signal assignment statement on line 1307:
1307: next_state <= s_pc_ovr_delim;
Count: 34
Threshold: 1
If statement on lines 1314 to 1320:
1314: if (ctrl_ctr_zero = '1') then
1315: if (rx_data_nbs = DOMINANT) then
...
1319: end if;
1320: end if;
Count: 53380
Threshold: 1
If statement on lines 1315 to 1319:
1315: if (rx_data_nbs = DOMINANT) then
1316: next_state <= s_pc_ovr_flag;
1317: else
1318: next_state <= s_pc_intermission;
1319: end if;
Count: 27039
Threshold: 1
Signal assignment statement on line 1316:
1316: next_state <= s_pc_ovr_flag;
Count: 168
Threshold: 1
Signal assignment statement on line 1318:
1318: next_state <= s_pc_intermission;
Count: 26871
Threshold: 1
If statement on lines 1326 to 1328:
1326: if (ctrl_ctr_zero = '1') then
1327: next_state <= s_pc_ovr_delim_wait;
1328: end if;
Count: 1434
Threshold: 1
Signal assignment statement on line 1327:
1327: next_state <= s_pc_ovr_delim_wait;
Count: 778
Threshold: 1
If statement on lines 1334 to 1338:
1334: if (rx_data_nbs = RECESSIVE) then
1335: next_state <= s_pc_ovr_delim;
1336: elsif (ctrl_ctr_zero = '1') then
1337: next_state <= s_pc_ovr_flag_too_long;
1338: end if;
Count: 1408
Threshold: 1
Signal assignment statement on line 1335:
1335: next_state <= s_pc_ovr_delim;
Count: 498
Threshold: 1
Signal assignment statement on line 1337:
1337: next_state <= s_pc_ovr_flag_too_long;
Count: 471
Threshold: 1
If statement on lines 1344 to 1350:
1344: if (ctrl_ctr_zero = '1') then
1345: if (rx_data_nbs = DOMINANT) then
...
1349: end if;
1350: end if;
Count: 938
Threshold: 1
If statement on lines 1345 to 1349:
1345: if (rx_data_nbs = DOMINANT) then
1346: next_state <= s_pc_ovr_flag;
1347: else
1348: next_state <= s_pc_intermission;
1349: end if;
Count: 410
Threshold: 1
Signal assignment statement on line 1346:
1346: next_state <= s_pc_ovr_flag;
Count: 32
Threshold: 1
Signal assignment statement on line 1348:
1348: next_state <= s_pc_intermission;
Count: 378
Threshold: 1
Signal assignment statement on line 1375:
1375: ctrl_ctr_pload_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1376:
1376: ctrl_ctr_pload_val <= (others => '0');
Count: 40929055
Threshold: 1
Signal assignment statement on line 1377:
1377: ctrl_ctr_pload_unaliged <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1378:
1378: ctrl_ctr_ena <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1379:
1379: compl_ctr_ena_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1380:
1380: arbitration_part <= ALC_RSVD;
Count: 40929055
Threshold: 1
Signal assignment statement on line 1383:
1383: store_metadata_d <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1384:
1384: store_data_d <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1385:
1385: rec_valid_d <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1387:
1387: sof_pulse_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1390:
1390: txtb_hw_cmd_d.lock <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1391:
1391: txtb_hw_cmd_d.valid <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1392:
1392: txtb_hw_cmd_d.err <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1393:
1393: txtb_hw_cmd_d.arbl <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1394:
1394: txtb_hw_cmd_d.failed <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1397:
1397: rx_store_base_id_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1398:
1398: rx_store_ext_id_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1399:
1399: rx_store_ide_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1400:
1400: rx_store_rtr_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1401:
1401: rx_store_edl_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1402:
1402: rx_store_dlc_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1403:
1403: rx_store_esi_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1404:
1404: rx_store_brs_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1405:
1405: rx_store_stuff_count_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1407:
1407: rx_shift_ena <= "0000";
Count: 40929055
Threshold: 1
Signal assignment statement on line 1408:
1408: rx_shift_in_sel <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1409:
1409: rx_clear_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1412:
1412: tx_load_base_id_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1413:
1413: tx_load_ext_id_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1414:
1414: tx_load_dlc_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1415:
1415: tx_load_data_word_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1416:
1416: tx_load_stuff_count_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1417:
1417: tx_load_crc_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1419:
1419: tx_shift_ena_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1420:
1420: tx_dominant <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1422:
1422: reinteg_ctr_clr <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1423:
1423: reinteg_ctr_enable <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1424:
1424: is_arbitration_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1425:
1425: tx_dominant <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1426:
1426: crc_check <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1429:
1429: form_err_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1430:
1430: ack_err_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1431:
1431: crc_err_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1432:
1432: bit_err_arb_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1433:
1433: bit_err_disable <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1434:
1434: bit_err_disable_receiver<= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1435:
1435: crc_clear_match_flag <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1436:
1436: err_pos <= ERC_POS_OTHER;
Count: 40929055
Threshold: 1
Signal assignment statement on line 1438:
1438: arbitration_lost_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1439:
1439: set_transmitter_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1440:
1440: set_receiver_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1441:
1441: set_idle_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1443:
1443: sp_control_switch_data <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1444:
1444: sp_control_switch_nominal <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1447:
1447: ssp_reset <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1448:
1448: tran_delay_meas <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1451:
1451: btmc_reset <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1452:
1452: dbt_measure_start <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1453:
1453: gen_first_ssp <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1456:
1456: primary_err_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1457:
1457: err_delim_late_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1458:
1458: first_err_delim_d <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1459:
1459: set_err_active_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1461:
1461: br_shifted_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1464:
1464: fixed_stuff <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1465:
1465: stuff_enable_set <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1466:
1466: stuff_enable_clear <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1467:
1467: destuff_enable_set <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1468:
1468: destuff_enable_clear <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1469:
1469: tx_frame_no_sof_d <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1472:
1472: perform_hsync <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1475:
1475: txtb_ptr_d <= 0;
Count: 40929055
Threshold: 1
Signal assignment statement on line 1478:
1478: crc_enable <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1479:
1479: crc_spec_enable_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1480:
1480: load_init_vect_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1483:
1483: nbt_ctrs_en <= '1';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1484:
1484: dbt_ctrs_en <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1487:
1487: retr_ctr_add_block_clr <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1488:
1488: tick_state_reg <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1491:
1491: pc_dbg.is_control <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1492:
1492: pc_dbg.is_data <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1493:
1493: pc_dbg.is_stuff_count <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1494:
1494: pc_dbg.is_crc <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1495:
1495: pc_dbg.is_crc_delim <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1496:
1496: pc_dbg.is_ack <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1497:
1497: pc_dbg.is_ack_delim <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1498:
1498: pc_dbg.is_eof <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1499:
1499: pc_dbg.is_suspend <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1500:
1500: pc_dbg.is_err <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1501:
1501: pc_dbg.is_overload <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1502:
1502: pc_dbg.is_intermission <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1503:
1503: pc_dbg.is_sof <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1505:
1505: clr_bus_off_rst_flg <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1506:
1506: decrement_rec_i <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1507:
1507: ack_err_flag_clr <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1508:
1508: bit_err_after_ack_err <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1510:
1510: pexs_set <= '0';
Count: 40929055
Threshold: 1
Signal assignment statement on line 1512:
1512: rec_lbpf_d <= rec_lbpf_q;
Count: 40929055
Threshold: 1
Signal assignment statement on line 1513:
1513: rec_ivld_i <= rec_ivld_q;
Count: 40929055
Threshold: 1
If statement on lines 1515 to 1770:
1515: if (err_frm_req = '1') then
1516: tick_state_reg <= '1';
...
1769: end if;
1770: end if;
Count: 40929055
Threshold: 1
Signal assignment statement on line 1516:
1516: tick_state_reg <= '1';
Count: 47062
Threshold: 1
Signal assignment statement on line 1517:
1517: ctrl_ctr_pload_i <= '1';
Count: 47062
Threshold: 1
If statement on lines 1518 to 1523:
1518: if (mr_mode_rom = ROM_DISABLED) then
1519: ctrl_ctr_pload_val <= C_ERR_FLG_DURATION;
1520: else
1521: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1522: set_idle_i <= '1';
1523: end if;
Count: 47062
Threshold: 1
Signal assignment statement on line 1519:
1519: ctrl_ctr_pload_val <= C_ERR_FLG_DURATION;
Count: 42857
Threshold: 1
Signal assignment statement on line 1521:
1521: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 4205
Threshold: 1
Signal assignment statement on line 1522:
1522: set_idle_i <= '1';
Count: 4205
Threshold: 1
Signal assignment statement on line 1525:
1525: crc_clear_match_flag <= '1';
Count: 47062
Threshold: 1
Signal assignment statement on line 1526:
1526: destuff_enable_clear <= '1';
Count: 47062
Threshold: 1
Signal assignment statement on line 1527:
1527: stuff_enable_clear <= '1';
Count: 47062
Threshold: 1
If statement on lines 1529 to 1534:
1529: if (sp_control_q_i = DATA_SAMPLE or
1530: sp_control_q_i = SECONDARY_SAMPLE)
1531: then
1532: sp_control_switch_nominal <= '1';
1533: br_shifted_i <= '1';
1534: end if;
Count: 47062
Threshold: 1
Signal assignment statement on line 1532:
1532: sp_control_switch_nominal <= '1';
Count: 14380
Threshold: 1
Signal assignment statement on line 1533:
1533: br_shifted_i <= '1';
Count: 14380
Threshold: 1
If statement on lines 1536 to 1542:
1536: if (is_transmitter = '1' and block_txtb_unlock = '0') then
1537: if (tx_failed = '1') then
...
1541: end if;
1542: end if;
Count: 47062
Threshold: 1
If statement on lines 1537 to 1541:
1537: if (tx_failed = '1') then
1538: txtb_hw_cmd_d.failed <= '1';
1539: else
1540: txtb_hw_cmd_d.err <= '1';
1541: end if;
Count: 25676
Threshold: 1
Signal assignment statement on line 1538:
1538: txtb_hw_cmd_d.failed <= '1';
Count: 18661
Threshold: 1
Signal assignment statement on line 1540:
1540: txtb_hw_cmd_d.err <= '1';
Count: 7015
Threshold: 1
Signal assignment statement on line 1546:
1546: dbt_ctrs_en <= '1';
Count: 47062
Threshold: 1
Sequential statement on lines 1549 to 1804:
1549: case curr_state is
1550:
...
1803:
1804: if (is_transmitter = '1') then
Count: 40881993
Threshold: 1
If statement on lines 1555 to 1570:
1555: if (mr_settings_ena = CTU_CAN_ENABLED) then
1556: nbt_ctrs_en <= '1';
...
1569: nbt_ctrs_en <= '0';
1570: end if;
Count: 66081
Threshold: 1
Signal assignment statement on line 1556:
1556: nbt_ctrs_en <= '1';
Count: 27464
Threshold: 1
Signal assignment statement on line 1557:
1557: tick_state_reg <= '1';
Count: 27464
Threshold: 1
Signal assignment statement on line 1558:
1558: ctrl_ctr_pload_i <= '1';
Count: 27464
Threshold: 1
Signal assignment statement on line 1559:
1559: bit_err_disable <= '1';
Count: 27464
Threshold: 1
If statement on lines 1563 to 1567:
1563: if (rx_data_nbs = DOMINANT) then
1564: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1565: else
1566: ctrl_ctr_pload_val <= C_FIRST_INTEGRATION_DURATION;
1567: end if;
Count: 27464
Threshold: 1
Signal assignment statement on line 1564:
1564: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 57
Threshold: 1
Signal assignment statement on line 1566:
1566: ctrl_ctr_pload_val <= C_FIRST_INTEGRATION_DURATION;
Count: 27407
Threshold: 1
Signal assignment statement on line 1569:
1569: nbt_ctrs_en <= '0';
Count: 38617
Threshold: 1
Signal assignment statement on line 1576:
1576: bit_err_disable <= '1';
Count: 310207
Threshold: 1
Signal assignment statement on line 1577:
1577: ctrl_ctr_ena <= '1';
Count: 310207
Threshold: 1
Signal assignment statement on line 1578:
1578: perform_hsync <= '1';
Count: 310207
Threshold: 1
If statement on lines 1582 to 1584:
1582: if (rx_data_nbs = DOMINANT or sync_edge = '1') then
1583: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1584: end if;
Count: 310207
Threshold: 1
Signal assignment statement on line 1583:
1583: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 27172
Threshold: 1
If statement on lines 1587 to 1589:
1587: if (rx_data_nbs = DOMINANT) then
1588: ctrl_ctr_pload_i <= '1';
1589: end if;
Count: 310207
Threshold: 1
Signal assignment statement on line 1588:
1588: ctrl_ctr_pload_i <= '1';
Count: 22000
Threshold: 1
If statement on lines 1591 to 1593:
1591: if (integ_restart_edge = '1') then
1592: ctrl_ctr_pload_unaliged <= '1';
1593: end if;
Count: 310207
Threshold: 1
Signal assignment statement on line 1592:
1592: ctrl_ctr_pload_unaliged <= '1';
Count: 5167
Threshold: 1
If statement on lines 1595 to 1607:
1595: if (ctrl_ctr_zero = '1') then
1596: tick_state_reg <= '1';
...
1606: load_init_vect_i <= '1';
1607: end if;
Count: 310207
Threshold: 1
Signal assignment statement on line 1596:
1596: tick_state_reg <= '1';
Count: 32249
Threshold: 1
Signal assignment statement on line 1597:
1597: set_idle_i <= '1';
Count: 32249
Threshold: 1
If statement on lines 1603 to 1605:
1603: if (is_bus_off = '1') then
1604: set_err_active_i <= '1';
1605: end if;
Count: 32249
Threshold: 1
Signal assignment statement on line 1604:
1604: set_err_active_i <= '1';
Count: 19401
Threshold: 1
Signal assignment statement on line 1606:
1606: load_init_vect_i <= '1';
Count: 32249
Threshold: 1
Signal assignment statement on line 1613:
1613: tick_state_reg <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1614:
1614: bit_err_disable <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1615:
1615: ctrl_ctr_pload_i <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1616:
1616: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
Count: 296415
Threshold: 1
Signal assignment statement on line 1617:
1617: tx_load_base_id_i <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1618:
1618: sof_pulse_i <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1619:
1619: rec_ivld_i <= '0';
Count: 296415
Threshold: 1
Signal assignment statement on line 1620:
1620: tx_dominant <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1621:
1621: err_pos <= ERC_POS_SOF;
Count: 296415
Threshold: 1
Signal assignment statement on line 1622:
1622: crc_enable <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1623:
1623: pc_dbg.is_sof <= '1';
Count: 296415
Threshold: 1
Signal assignment statement on line 1631:
1631: perform_hsync <= '1';
Count: 296415
Threshold: 1
If statement on lines 1633 to 1635:
1633: if (rx_data_nbs = RECESSIVE) then
1634: form_err_i <= '1';
1635: end if;
Count: 296415
Threshold: 1
Signal assignment statement on line 1634:
1634: form_err_i <= '1';
Count: 246233
Threshold: 1
Signal assignment statement on line 1641:
1641: bit_err_disable <= '1';
Count: 3468353
Threshold: 1
Signal assignment statement on line 1642:
1642: ctrl_ctr_ena <= '1';
Count: 3468353
Threshold: 1
Signal assignment statement on line 1643:
1643: rx_shift_ena <= "1111";
Count: 3468353
Threshold: 1
Signal assignment statement on line 1644:
1644: is_arbitration_i <= '1';
Count: 3468353
Threshold: 1
Signal assignment statement on line 1645:
1645: tx_shift_ena_i <= '1';
Count: 3468353
Threshold: 1
Signal assignment statement on line 1646:
1646: err_pos <= ERC_POS_ARB;
Count: 3468353
Threshold: 1
Signal assignment statement on line 1647:
1647: crc_enable <= '1';
Count: 3468353
Threshold: 1
Signal assignment statement on line 1648:
1648: arbitration_part <= ALC_BASE_ID;
Count: 3468353
Threshold: 1
If statement on lines 1650 to 1658:
1650: if (arbitration_lost_condition = '1') then
1651: arbitration_lost_i <= '1';
...
1657: end if;
1658: end if;
Count: 3468353
Threshold: 1
Signal assignment statement on line 1651:
1651: arbitration_lost_i <= '1';
Count: 1966
Threshold: 1
Signal assignment statement on line 1652:
1652: stuff_enable_clear <= '1';
Count: 1966
Threshold: 1
If statement on lines 1653 to 1657:
1653: if (tx_failed = '1') then
1654: txtb_hw_cmd_d.failed <= '1';
1655: else
1656: txtb_hw_cmd_d.arbl <= '1';
1657: end if;
Count: 1966
Threshold: 1
Signal assignment statement on line 1654:
1654: txtb_hw_cmd_d.failed <= '1';
Count: 195
Threshold: 1
Signal assignment statement on line 1656:
1656: txtb_hw_cmd_d.arbl <= '1';
Count: 1771
Threshold: 1
If statement on lines 1660 to 1663:
1660: if (ctrl_ctr_zero = '1') then
1661: tick_state_reg <= '1';
1662: rx_store_base_id_i <= '1';
1663: end if;
Count: 3468353
Threshold: 1
Signal assignment statement on line 1661:
1661: tick_state_reg <= '1';
Count: 294847
Threshold: 1
Signal assignment statement on line 1662:
1662: rx_store_base_id_i <= '1';
Count: 294847
Threshold: 1
If statement on lines 1665 to 1667:
1665: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1666: bit_err_arb_i <= '1';
1667: end if;
Count: 3468353
Threshold: 1
Signal assignment statement on line 1666:
1666: bit_err_arb_i <= '1';
Count: 348630
Threshold: 1
Signal assignment statement on line 1673:
1673: tick_state_reg <= '1';
Count: 392853
Threshold: 1
Signal assignment statement on line 1674:
1674: is_arbitration_i <= '1';
Count: 392853
Threshold: 1
Signal assignment statement on line 1675:
1675: bit_err_disable <= '1';
Count: 392853
Threshold: 1
Signal assignment statement on line 1676:
1676: crc_enable <= '1';
Count: 392853
Threshold: 1
Signal assignment statement on line 1677:
1677: rx_store_rtr_i <= '1';
Count: 392853
Threshold: 1
Signal assignment statement on line 1678:
1678: err_pos <= ERC_POS_ARB;
Count: 392853
Threshold: 1
Signal assignment statement on line 1679:
1679: arbitration_part <= ALC_SRR_RTR;
Count: 392853
Threshold: 1
If statement on lines 1681 to 1689:
1681: if (arbitration_lost_condition = '1') then
1682: arbitration_lost_i <= '1';
...
1688: end if;
1689: end if;
Count: 392853
Threshold: 1
Signal assignment statement on line 1682:
1682: arbitration_lost_i <= '1';
Count: 185
Threshold: 1
Signal assignment statement on line 1683:
1683: stuff_enable_clear <= '1';
Count: 185
Threshold: 1
If statement on lines 1684 to 1688:
1684: if (tx_failed = '1') then
1685: txtb_hw_cmd_d.failed <= '1';
1686: else
1687: txtb_hw_cmd_d.arbl <= '1';
1688: end if;
Count: 185
Threshold: 1
Signal assignment statement on line 1685:
1685: txtb_hw_cmd_d.failed <= '1';
Count: 61
Threshold: 1
Signal assignment statement on line 1687:
1687: txtb_hw_cmd_d.arbl <= '1';
Count: 124
Threshold: 1
If statement on lines 1691 to 1695:
1691: if (is_transmitter = '1' and tran_ident_type = BASE) then
1692: if (tran_frame_type_i = FD_CAN or tran_is_rtr = NO_RTR_FRAME) then
1693: tx_dominant <= '1';
1694: end if;
1695: end if;
Count: 392853
Threshold: 1
If statement on lines 1692 to 1694:
1692: if (tran_frame_type_i = FD_CAN or tran_is_rtr = NO_RTR_FRAME) then
1693: tx_dominant <= '1';
1694: end if;
Count: 109982
Threshold: 1
Signal assignment statement on line 1693:
1693: tx_dominant <= '1';
Count: 105017
Threshold: 1
If statement on lines 1697 to 1699:
1697: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1698: bit_err_arb_i <= '1';
1699: end if;
Count: 392853
Threshold: 1
Signal assignment statement on line 1698:
1698: bit_err_arb_i <= '1';
Count: 44396
Threshold: 1
Signal assignment statement on line 1705:
1705: tick_state_reg <= '1';
Count: 217714
Threshold: 1
Signal assignment statement on line 1706:
1706: rx_store_ide_i <= '1';
Count: 217714
Threshold: 1
Signal assignment statement on line 1707:
1707: crc_enable <= '1';
Count: 217714
Threshold: 1
Signal assignment statement on line 1708:
1708: arbitration_part <= ALC_IDE;
Count: 217714
Threshold: 1
If statement on lines 1710 to 1716:
1710: if (rx_data_nbs = RECESSIVE) then
1711: ctrl_ctr_pload_i <= '1';
...
1715: rec_ivld_i <= '1';
1716: end if;
Count: 217714
Threshold: 1
Signal assignment statement on line 1711:
1711: ctrl_ctr_pload_i <= '1';
Count: 111927
Threshold: 1
Signal assignment statement on line 1712:
1712: ctrl_ctr_pload_val <= C_EXT_ID_DURATION;
Count: 111927
Threshold: 1
Signal assignment statement on line 1713:
1713: tx_load_ext_id_i <= '1';
Count: 111927
Threshold: 1
Signal assignment statement on line 1715:
1715: rec_ivld_i <= '1';
Count: 105787
Threshold: 1
If statement on lines 1718 to 1726:
1718: if (ide_is_arbitration = '1' and arbitration_lost_condition = '1') then
1719: arbitration_lost_i <= '1';
...
1725: end if;
1726: end if;
Count: 217714
Threshold: 1
Signal assignment statement on line 1719:
1719: arbitration_lost_i <= '1';
Count: 145
Threshold: 1
Signal assignment statement on line 1720:
1720: stuff_enable_clear <= '1';
Count: 145
Threshold: 1
If statement on lines 1721 to 1725:
1721: if (tx_failed = '1') then
1722: txtb_hw_cmd_d.failed <= '1';
1723: else
1724: txtb_hw_cmd_d.arbl <= '1';
1725: end if;
Count: 145
Threshold: 1
Signal assignment statement on line 1722:
1722: txtb_hw_cmd_d.failed <= '1';
Count: 89
Threshold: 1
Signal assignment statement on line 1724:
1724: txtb_hw_cmd_d.arbl <= '1';
Count: 56
Threshold: 1
If statement on lines 1728 to 1733:
1728: if (ide_is_arbitration = '1') then
1729: is_arbitration_i <= '1';
1730: bit_err_disable <= '1';
1731: else
1732: pc_dbg.is_control <= '1';
1733: end if;
Count: 217714
Threshold: 1
Signal assignment statement on line 1729:
1729: is_arbitration_i <= '1';
Count: 166570
Threshold: 1
Signal assignment statement on line 1730:
1730: bit_err_disable <= '1';
Count: 166570
Threshold: 1
Signal assignment statement on line 1732:
1732: pc_dbg.is_control <= '1';
Count: 51144
Threshold: 1
If statement on lines 1735 to 1737:
1735: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1736: bit_err_arb_i <= '1';
1737: end if;
Count: 217714
Threshold: 1
Signal assignment statement on line 1736:
1736: bit_err_arb_i <= '1';
Count: 9616
Threshold: 1
If statement on lines 1739 to 1741:
1739: if (is_transmitter = '1' and tran_ident_type = BASE) then
1740: tx_dominant <= '1';
1741: end if;
Count: 217714
Threshold: 1
Signal assignment statement on line 1740:
1740: tx_dominant <= '1';
Count: 51128
Threshold: 1
If statement on lines 1743 to 1747:
1743: if (ide_is_arbitration = '1') then
1744: err_pos <= ERC_POS_ARB;
1745: else
1746: err_pos <= ERC_POS_CTRL;
1747: end if;
Count: 217714
Threshold: 1
Signal assignment statement on line 1744:
1744: err_pos <= ERC_POS_ARB;
Count: 166570
Threshold: 1
Signal assignment statement on line 1746:
1746: err_pos <= ERC_POS_CTRL;
Count: 51144
Threshold: 1
Signal assignment statement on line 1753:
1753: ctrl_ctr_ena <= '1';
Count: 1559727
Threshold: 1
Signal assignment statement on line 1754:
1754: rx_shift_ena <= "1111";
Count: 1559727
Threshold: 1
Signal assignment statement on line 1755:
1755: is_arbitration_i <= '1';
Count: 1559727
Threshold: 1
Signal assignment statement on line 1756:
1756: tx_shift_ena_i <= '1';
Count: 1559727
Threshold: 1
Signal assignment statement on line 1757:
1757: err_pos <= ERC_POS_ARB;
Count: 1559727
Threshold: 1
Signal assignment statement on line 1758:
1758: bit_err_disable <= '1';
Count: 1559727
Threshold: 1
Signal assignment statement on line 1759:
1759: crc_enable <= '1';
Count: 1559727
Threshold: 1
Signal assignment statement on line 1760:
1760: arbitration_part <= ALC_EXTENSION;
Count: 1559727
Threshold: 1
If statement on lines 1762 to 1770:
1762: if (arbitration_lost_condition = '1') then
1763: arbitration_lost_i <= '1';
...
1769: end if;
1770: end if;
Count: 1559727
Threshold: 1
Signal assignment statement on line 1763:
1763: arbitration_lost_i <= '1';
Count: 660
Threshold: 1
Signal assignment statement on line 1764:
1764: stuff_enable_clear <= '1';
Count: 660
Threshold: 1
If statement on lines 1765 to 1769:
1765: if (tx_failed = '1') then
1766: txtb_hw_cmd_d.failed <= '1';
1767: else
1768: txtb_hw_cmd_d.arbl <= '1';
1769: end if;
Count: 660
Threshold: 1
Signal assignment statement on line 1766:
1766: txtb_hw_cmd_d.failed <= '1';
Count: 234
Threshold: 1
Signal assignment statement on line 1768:
1768: txtb_hw_cmd_d.arbl <= '1';
Count: 426
Threshold: 1
If statement on lines 1772 to 1775:
1772: if (ctrl_ctr_zero = '1') then
1773: tick_state_reg <= '1';
1774: rx_store_ext_id_i <= '1';
1775: end if;
Count: 1559727
Threshold: 1
Signal assignment statement on line 1773:
1773: tick_state_reg <= '1';
Count: 88365
Threshold: 1
Signal assignment statement on line 1774:
1774: rx_store_ext_id_i <= '1';
Count: 88365
Threshold: 1
If statement on lines 1777 to 1779:
1777: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1778: bit_err_arb_i <= '1';
1779: end if;
Count: 1559727
Threshold: 1
Signal assignment statement on line 1778:
1778: bit_err_arb_i <= '1';
Count: 211077
Threshold: 1
Signal assignment statement on line 1785:
1785: tick_state_reg <= '1';
Count: 113948
Threshold: 1
Signal assignment statement on line 1786:
1786: is_arbitration_i <= '1';
Count: 113948
Threshold: 1
Signal assignment statement on line 1787:
1787: bit_err_disable <= '1';
Count: 113948
Threshold: 1
Signal assignment statement on line 1788:
1788: crc_enable <= '1';
Count: 113948
Threshold: 1
Signal assignment statement on line 1789:
1789: rx_store_rtr_i <= '1';
Count: 113948
Threshold: 1
Signal assignment statement on line 1790:
1790: err_pos <= ERC_POS_ARB;
Count: 113948
Threshold: 1
Signal assignment statement on line 1791:
1791: arbitration_part <= ALC_RTR;
Count: 113948
Threshold: 1
Signal assignment statement on line 1792:
1792: rec_ivld_i <= '1';
Count: 113948
Threshold: 1
If statement on lines 1794 to 1802:
1794: if (arbitration_lost_condition = '1') then
1795: arbitration_lost_i <= '1';
...
1801: end if;
1802: end if;
Count: 113948
Threshold: 1
Signal assignment statement on line 1795:
1795: arbitration_lost_i <= '1';
Count: 48
Threshold: 1
Signal assignment statement on line 1796:
1796: stuff_enable_clear <= '1';
Count: 48
Threshold: 1
If statement on lines 1797 to 1801:
1797: if (tx_failed = '1') then
1798: txtb_hw_cmd_d.failed <= '1';
1799: else
1800: txtb_hw_cmd_d.arbl <= '1';
1801: end if;
Count: 48
Threshold: 1
Signal assignment statement on line 1798:
1798: txtb_hw_cmd_d.failed <= '1';
Count: 20
Threshold: 1
Signal assignment statement on line 1800:
1800: txtb_hw_cmd_d.arbl <= '1';
Count: 28
Threshold: 1
If statement on lines 1804 to 1810:
1804: if (is_transmitter = '1') then
1805: if (tran_frame_type_i = FD_CAN) then
...
1809: end if;
1810: end if;
Count: 113948
Threshold: 1
If statement on lines 1805 to 1809:
1805: if (tran_frame_type_i = FD_CAN) then
1806: tx_dominant <= '1';
1807: elsif (tran_is_rtr = NO_RTR_FRAME) then
1808: tx_dominant <= '1';
1809: end if;
Count: 55903
Threshold: 1
Signal assignment statement on line 1806:
1806: tx_dominant <= '1';
Count: 30963
Threshold: 1
Signal assignment statement on line 1808:
1808: tx_dominant <= '1';
Count: 21404
Threshold: 1
If statement on lines 1812 to 1814:
1812: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1813: bit_err_arb_i <= '1';
1814: end if;
Count: 113948
Threshold: 1
Signal assignment statement on line 1813:
1813: bit_err_arb_i <= '1';
Count: 17452
Threshold: 1
Signal assignment statement on line 1820:
1820: tick_state_reg <= '1';
Count: 94072
Threshold: 1
Signal assignment statement on line 1821:
1821: rx_store_edl_i <= '1';
Count: 94072
Threshold: 1
Signal assignment statement on line 1822:
1822: err_pos <= ERC_POS_CTRL;
Count: 94072
Threshold: 1
Signal assignment statement on line 1823:
1823: crc_enable <= '1';
Count: 94072
Threshold: 1
Signal assignment statement on line 1824:
1824: pc_dbg.is_control <= '1';
Count: 94072
Threshold: 1
Signal assignment statement on line 1825:
1825: bit_err_disable_receiver <= '1';
Count: 94072
Threshold: 1
If statement on lines 1827 to 1833:
1827: if (is_transmitter = '1') then
1828: if (tran_frame_type_i = NORMAL_CAN) then
...
1832: end if;
1833: end if;
Count: 94072
Threshold: 1
If statement on lines 1828 to 1832:
1828: if (tran_frame_type_i = NORMAL_CAN) then
1829: tx_dominant <= '1';
1830: else
1831: ssp_reset <= '1';
1832: end if;
Count: 38873
Threshold: 1
Signal assignment statement on line 1829:
1829: tx_dominant <= '1';
Count: 15964
Threshold: 1
Signal assignment statement on line 1831:
1831: ssp_reset <= '1';
Count: 22909
Threshold: 1
If statement on lines 1836 to 1848:
1836: if (rx_data_nbs = RECESSIVE and mr_mode_fde = FDE_DISABLE)
1837: then
...
1847: end if;
1848: end if;
Count: 94072
Threshold: 1
If statement on lines 1838 to 1847:
1838: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
1839: form_err_i <= '1';
...
1846: pexs_set <= '1';
1847: end if;
Count: 214
Threshold: 1
Signal assignment statement on line 1839:
1839: form_err_i <= '1';
Count: 176
Threshold: 1
Signal assignment statement on line 1843:
1843: destuff_enable_clear <= '1';
Count: 38
Threshold: 1
Signal assignment statement on line 1844:
1844: ctrl_ctr_pload_i <= '1';
Count: 38
Threshold: 1
Signal assignment statement on line 1845:
1845: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 38
Threshold: 1
Signal assignment statement on line 1846:
1846: pexs_set <= '1';
Count: 38
Threshold: 1
Signal assignment statement on line 1854:
1854: tick_state_reg <= '1';
Count: 39619
Threshold: 1
Signal assignment statement on line 1855:
1855: ctrl_ctr_pload_i <= '1';
Count: 39619
Threshold: 1
Signal assignment statement on line 1856:
1856: ctrl_ctr_pload_val <= C_DLC_DURATION;
Count: 39619
Threshold: 1
Signal assignment statement on line 1857:
1857: tx_load_dlc_i <= '1';
Count: 39619
Threshold: 1
Signal assignment statement on line 1858:
1858: err_pos <= ERC_POS_CTRL;
Count: 39619
Threshold: 1
Signal assignment statement on line 1859:
1859: tran_delay_meas <= '1';
Count: 39619
Threshold: 1
Signal assignment statement on line 1860:
1860: crc_enable <= '1';
Count: 39619
Threshold: 1
Signal assignment statement on line 1861:
1861: pc_dbg.is_control <= '1';
Count: 39619
Threshold: 1
Signal assignment statement on line 1862:
1862: bit_err_disable_receiver <= '1';
Count: 39619
Threshold: 1
If statement on lines 1864 to 1866:
1864: if (is_transmitter = '1') then
1865: tx_dominant <= '1';
1866: end if;
Count: 39619
Threshold: 1
Signal assignment statement on line 1865:
1865: tx_dominant <= '1';
Count: 19093
Threshold: 1
Signal assignment statement on line 1872:
1872: tick_state_reg <= '1';
Count: 306879
Threshold: 1
Signal assignment statement on line 1873:
1873: tran_delay_meas <= '1';
Count: 306879
Threshold: 1
Signal assignment statement on line 1874:
1874: err_pos <= ERC_POS_CTRL;
Count: 306879
Threshold: 1
Signal assignment statement on line 1875:
1875: perform_hsync <= '1';
Count: 306879
Threshold: 1
Signal assignment statement on line 1876:
1876: crc_enable <= '1';
Count: 306879
Threshold: 1
Signal assignment statement on line 1877:
1877: pc_dbg.is_control <= '1';
Count: 306879
Threshold: 1
Signal assignment statement on line 1878:
1878: bit_err_disable_receiver <= '1';
Count: 306879
Threshold: 1
If statement on lines 1880 to 1882:
1880: if (is_transmitter = '1') then
1881: tx_dominant <= '1';
1882: end if;
Count: 306879
Threshold: 1
Signal assignment statement on line 1881:
1881: tx_dominant <= '1';
Count: 112723
Threshold: 1
If statement on lines 1886 to 1897:
1886: if (rx_data_nbs = RECESSIVE) then
1887: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
...
1896: end if;
1897: end if;
Count: 306879
Threshold: 1
If statement on lines 1887 to 1896:
1887: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
1888: form_err_i <= '1';
...
1895: pexs_set <= '1';
1896: end if;
Count: 233672
Threshold: 1
Signal assignment statement on line 1888:
1888: form_err_i <= '1';
Count: 233258
Threshold: 1
Signal assignment statement on line 1892:
1892: destuff_enable_clear <= '1';
Count: 414
Threshold: 1
Signal assignment statement on line 1893:
1893: ctrl_ctr_pload_i <= '1';
Count: 414
Threshold: 1
Signal assignment statement on line 1894:
1894: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 414
Threshold: 1
Signal assignment statement on line 1895:
1895: pexs_set <= '1';
Count: 414
Threshold: 1
Signal assignment statement on line 1903:
1903: tick_state_reg <= '1';
Count: 138510
Threshold: 1
Signal assignment statement on line 1904:
1904: rx_store_edl_i <= '1';
Count: 138510
Threshold: 1
Signal assignment statement on line 1905:
1905: err_pos <= ERC_POS_CTRL;
Count: 138510
Threshold: 1
Signal assignment statement on line 1906:
1906: crc_enable <= '1';
Count: 138510
Threshold: 1
Signal assignment statement on line 1907:
1907: pc_dbg.is_control <= '1';
Count: 138510
Threshold: 1
Signal assignment statement on line 1908:
1908: bit_err_disable_receiver <= '1';
Count: 138510
Threshold: 1
If statement on lines 1910 to 1914:
1910: if (rx_data_nbs = DOMINANT) then
1911: ctrl_ctr_pload_i <= '1';
1912: ctrl_ctr_pload_val <= C_DLC_DURATION;
1913: tx_load_dlc_i <= '1';
1914: end if;
Count: 138510
Threshold: 1
Signal assignment statement on line 1911:
1911: ctrl_ctr_pload_i <= '1';
Count: 90562
Threshold: 1
Signal assignment statement on line 1912:
1912: ctrl_ctr_pload_val <= C_DLC_DURATION;
Count: 90562
Threshold: 1
Signal assignment statement on line 1913:
1913: tx_load_dlc_i <= '1';
Count: 90562
Threshold: 1
If statement on lines 1916 to 1920:
1916: if (is_transmitter = '1' and tran_frame_type_i = NORMAL_CAN) then
1917: tx_dominant <= '1';
1918: else
1919: ssp_reset <= '1';
1920: end if;
Count: 138510
Threshold: 1
Signal assignment statement on line 1917:
1917: tx_dominant <= '1';
Count: 20495
Threshold: 1
Signal assignment statement on line 1919:
1919: ssp_reset <= '1';
Count: 118015
Threshold: 1
If statement on lines 1924 to 1935:
1924: if (rx_data_nbs = RECESSIVE and mr_mode_fde = FDE_DISABLE) then
1925: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
...
1934: end if;
1935: end if;
Count: 138510
Threshold: 1
If statement on lines 1925 to 1934:
1925: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
1926: form_err_i <= '1';
...
1933: pexs_set <= '1';
1934: end if;
Count: 120
Threshold: 1
Signal assignment statement on line 1926:
1926: form_err_i <= '1';
Count: 78
Threshold: 1
Signal assignment statement on line 1930:
1930: destuff_enable_clear <= '1';
Count: 42
Threshold: 1
Signal assignment statement on line 1931:
1931: ctrl_ctr_pload_i <= '1';
Count: 42
Threshold: 1
Signal assignment statement on line 1932:
1932: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 42
Threshold: 1
Signal assignment statement on line 1933:
1933: pexs_set <= '1';
Count: 42
Threshold: 1
Signal assignment statement on line 1941:
1941: tick_state_reg <= '1';
Count: 125546
Threshold: 1
Signal assignment statement on line 1942:
1942: rx_store_brs_i <= '1';
Count: 125546
Threshold: 1
Signal assignment statement on line 1943:
1943: err_pos <= ERC_POS_CTRL;
Count: 125546
Threshold: 1
Signal assignment statement on line 1944:
1944: crc_enable <= '1';
Count: 125546
Threshold: 1
Signal assignment statement on line 1945:
1945: pc_dbg.is_control <= '1';
Count: 125546
Threshold: 1
Signal assignment statement on line 1946:
1946: bit_err_disable_receiver <= '1';
Count: 125546
Threshold: 1
Signal assignment statement on line 1947:
1947: dbt_ctrs_en <= '1';
Count: 125546
Threshold: 1
Signal assignment statement on line 1948:
1948: btmc_reset <= '1';
Count: 125546
Threshold: 1
If statement on lines 1950 to 1952:
1950: if (is_transmitter = '1' and tran_brs = BR_NO_SHIFT) then
1951: tx_dominant <= '1';
1952: end if;
Count: 125546
Threshold: 1
Signal assignment statement on line 1951:
1951: tx_dominant <= '1';
Count: 14324
Threshold: 1
If statement on lines 1954 to 1957:
1954: if (rx_data_nbs = RECESSIVE and rx_trigger = '1') then
1955: sp_control_switch_data <= '1';
1956: br_shifted_i <= '1';
1957: end if;
Count: 125546
Threshold: 1
Signal assignment statement on line 1955:
1955: sp_control_switch_data <= '1';
Count: 33427
Threshold: 1
Signal assignment statement on line 1956:
1956: br_shifted_i <= '1';
Count: 33427
Threshold: 1
Signal assignment statement on line 1963:
1963: tick_state_reg <= '1';
Count: 211504
Threshold: 1
Signal assignment statement on line 1964:
1964: ctrl_ctr_pload_i <= '1';
Count: 211504
Threshold: 1
Signal assignment statement on line 1965:
1965: ctrl_ctr_pload_val <= C_DLC_DURATION;
Count: 211504
Threshold: 1
Signal assignment statement on line 1966:
1966: tx_load_dlc_i <= '1';
Count: 211504
Threshold: 1
Signal assignment statement on line 1967:
1967: rx_store_esi_i <= '1';
Count: 211504
Threshold: 1
Signal assignment statement on line 1968:
1968: err_pos <= ERC_POS_CTRL;
Count: 211504
Threshold: 1
Signal assignment statement on line 1969:
1969: crc_enable <= '1';
Count: 211504
Threshold: 1
Signal assignment statement on line 1970:
1970: pc_dbg.is_control <= '1';
Count: 211504
Threshold: 1
Signal assignment statement on line 1971:
1971: bit_err_disable_receiver <= '1';
Count: 211504
Threshold: 1
Signal assignment statement on line 1972:
1972: dbt_ctrs_en <= '1';
Count: 211504
Threshold: 1
If statement on lines 1974 to 1976:
1974: if (is_transmitter = '1' and is_err_active = '1') then
1975: tx_dominant <= '1';
1976: end if;
Count: 211504
Threshold: 1
Signal assignment statement on line 1975:
1975: tx_dominant <= '1';
Count: 79270
Threshold: 1
If statement on lines 1979 to 1982:
1979: if (sp_control_q_i = SECONDARY_SAMPLE) then
1980: dbt_measure_start <= '1';
1981: gen_first_ssp <= '1';
1982: end if;
Count: 211504
Threshold: 1
Signal assignment statement on line 1980:
1980: dbt_measure_start <= '1';
Count: 17525
Threshold: 1
Signal assignment statement on line 1981:
1981: gen_first_ssp <= '1';
Count: 17525
Threshold: 1
Signal assignment statement on line 1988:
1988: ctrl_ctr_ena <= '1';
Count: 1021160
Threshold: 1
Signal assignment statement on line 1989:
1989: rx_shift_ena <= "1111";
Count: 1021160
Threshold: 1
Signal assignment statement on line 1990:
1990: tx_shift_ena_i <= '1';
Count: 1021160
Threshold: 1
Signal assignment statement on line 1991:
1991: err_pos <= ERC_POS_CTRL;
Count: 1021160
Threshold: 1
Signal assignment statement on line 1992:
1992: crc_enable <= '1';
Count: 1021160
Threshold: 1
Signal assignment statement on line 1993:
1993: pc_dbg.is_control <= '1';
Count: 1021160
Threshold: 1
Signal assignment statement on line 1994:
1994: bit_err_disable_receiver <= '1';
Count: 1021160
Threshold: 1
If statement on lines 1996 to 1998:
1996: if (sp_control_q_i /= NOMINAL_SAMPLE) then
1997: dbt_ctrs_en <= '1';
1998: end if;
Count: 1021160
Threshold: 1
Signal assignment statement on line 1997:
1997: dbt_ctrs_en <= '1';
Count: 353238
Threshold: 1
If statement on lines 2003 to 2005:
2003: if (is_transmitter = '1') then
2004: txtb_ptr_d <= 4;
2005: end if;
Count: 1021160
Threshold: 1
Signal assignment statement on line 2004:
2004: txtb_ptr_d <= 4;
Count: 423771
Threshold: 1
If statement on lines 2007 to 2032:
2007: if (ctrl_ctr_zero = '1') then
2008: tick_state_reg <= '1';
...
2031: rx_store_dlc_i <= '1';
2032: end if;
Count: 1021160
Threshold: 1
Signal assignment statement on line 2008:
2008: tick_state_reg <= '1';
Count: 284823
Threshold: 1
Signal assignment statement on line 2009:
2009: ctrl_ctr_pload_i <= '1';
Count: 284823
Threshold: 1
If statement on lines 2011 to 2022:
2011: if (no_data_field = '1') then
2012: if (go_to_stuff_count = '1') then
...
2021: tx_load_data_word_i <= '1';
2022: end if;
Count: 284823
Threshold: 1
If statement on lines 2012 to 2018:
2012: if (go_to_stuff_count = '1') then
2013: ctrl_ctr_pload_val <= C_STUFF_COUNT_DURATION;
...
2017: tx_load_crc_i <= '1';
2018: end if;
Count: 125699
Threshold: 1
Signal assignment statement on line 2013:
2013: ctrl_ctr_pload_val <= C_STUFF_COUNT_DURATION;
Count: 15557
Threshold: 1
Signal assignment statement on line 2014:
2014: tx_load_stuff_count_i <= '1';
Count: 15557
Threshold: 1
Signal assignment statement on line 2016:
2016: ctrl_ctr_pload_val <= crc_length_i;
Count: 110142
Threshold: 1
Signal assignment statement on line 2017:
2017: tx_load_crc_i <= '1';
Count: 110142
Threshold: 1
Signal assignment statement on line 2020:
2020: ctrl_ctr_pload_val <= data_length_bits_c;
Count: 159124
Threshold: 1
Signal assignment statement on line 2021:
2021: tx_load_data_word_i <= '1';
Count: 159124
Threshold: 1
If statement on lines 2024 to 2028:
2024: if (is_transmitter = '1' and mr_settings_ilbp = '1') then
2025: rec_lbpf_d <= LBPF_LOOPBACK;
2026: else
2027: rec_lbpf_d <= LBPF_FOREIGN;
2028: end if;
Count: 284823
Threshold: 1
Signal assignment statement on line 2025:
2025: rec_lbpf_d <= LBPF_LOOPBACK;
Count: 2262
Threshold: 1
Signal assignment statement on line 2027:
2027: rec_lbpf_d <= LBPF_FOREIGN;
Count: 282561
Threshold: 1
Signal assignment statement on line 2030:
2030: store_metadata_d <= '1';
Count: 284823
Threshold: 1
Signal assignment statement on line 2031:
2031: rx_store_dlc_i <= '1';
Count: 284823
Threshold: 1
Signal assignment statement on line 2038:
2038: ctrl_ctr_ena <= '1';
Count: 19763357
Threshold: 1
Signal assignment statement on line 2039:
2039: rx_shift_ena(to_integer(unsigned(ctrl_counted_byte_index))) <= '1';
Count: 19763357
Threshold: 1
Signal assignment statement on line 2040:
2040: rx_shift_in_sel <= '1';
Count: 19763357
Threshold: 1
Signal assignment statement on line 2041:
2041: tx_shift_ena_i <= '1';
Count: 19763357
Threshold: 1
Signal assignment statement on line 2042:
2042: err_pos <= ERC_POS_DATA;
Count: 19763357
Threshold: 1
Signal assignment statement on line 2043:
2043: crc_enable <= '1';
Count: 19763357
Threshold: 1
Signal assignment statement on line 2044:
2044: pc_dbg.is_data <= '1';
Count: 19763357
Threshold: 1
Signal assignment statement on line 2045:
2045: compl_ctr_ena_i <= '1';
Count: 19763357
Threshold: 1
Signal assignment statement on line 2046:
2046: bit_err_disable_receiver <= '1';
Count: 19763357
Threshold: 1
If statement on lines 2048 to 2050:
2048: if (sp_control_q_i /= NOMINAL_SAMPLE) then
2049: dbt_ctrs_en <= '1';
2050: end if;
Count: 19763357
Threshold: 1
Signal assignment statement on line 2049:
2049: dbt_ctrs_en <= '1';
Count: 16284444
Threshold: 1
If statement on lines 2055 to 2057:
2055: if (is_transmitter = '1') then
2056: txtb_ptr_d <= to_integer(unsigned(ctrl_ctr_mem_index));
2057: end if;
Count: 19763357
Threshold: 1
Signal assignment statement on line 2056:
2056: txtb_ptr_d <= to_integer(unsigned(ctrl_ctr_mem_index));
Count: 6967729
Threshold: 1
If statement on lines 2059 to 2073:
2059: if (ctrl_ctr_zero = '1') then
2060: tick_state_reg <= '1';
...
2072: store_data_d <= '1';
2073: end if;
Count: 19763357
Threshold: 1
Signal assignment statement on line 2060:
2060: tick_state_reg <= '1';
Count: 127843
Threshold: 1
Signal assignment statement on line 2061:
2061: ctrl_ctr_pload_i <= '1';
Count: 127843
Threshold: 1
If statement on lines 2063 to 2069:
2063: if (go_to_stuff_count = '1') then
2064: ctrl_ctr_pload_val <= C_STUFF_COUNT_DURATION;
...
2068: tx_load_crc_i <= '1';
2069: end if;
Count: 127843
Threshold: 1
Signal assignment statement on line 2064:
2064: ctrl_ctr_pload_val <= C_STUFF_COUNT_DURATION;
Count: 78871
Threshold: 1
Signal assignment statement on line 2065:
2065: tx_load_stuff_count_i <= '1';
Count: 78871
Threshold: 1
Signal assignment statement on line 2067:
2067: ctrl_ctr_pload_val <= crc_length_i;
Count: 48972
Threshold: 1
Signal assignment statement on line 2068:
2068: tx_load_crc_i <= '1';
Count: 48972
Threshold: 1
Signal assignment statement on line 2072:
2072: store_data_d <= '1';
Count: 127843
Threshold: 1
If statement on lines 2077 to 2083:
2077: if (ctrl_counted_byte = '1' and
2078: ctrl_counted_byte_index = "11" and
...
2082: tx_load_data_word_i <= '1';
2083: end if;
Count: 19763357
Threshold: 1
Signal assignment statement on line 2081:
2081: store_data_d <= '1';
Count: 576777
Threshold: 1
Signal assignment statement on line 2082:
2082: tx_load_data_word_i <= '1';
Count: 576777
Threshold: 1
Signal assignment statement on line 2089:
2089: ctrl_ctr_ena <= '1';
Count: 366575
Threshold: 1
Signal assignment statement on line 2090:
2090: rx_shift_ena <= "1111";
Count: 366575
Threshold: 1
Signal assignment statement on line 2091:
2091: tx_shift_ena_i <= '1';
Count: 366575
Threshold: 1
Signal assignment statement on line 2092:
2092: err_pos <= ERC_POS_CRC;
Count: 366575
Threshold: 1
Signal assignment statement on line 2093:
2093: crc_enable <= '1';
Count: 366575
Threshold: 1
Signal assignment statement on line 2094:
2094: pc_dbg.is_stuff_count <= '1';
Count: 366575
Threshold: 1
Signal assignment statement on line 2095:
2095: bit_err_disable_receiver <= '1';
Count: 366575
Threshold: 1
Signal assignment statement on line 2096:
2096: fixed_stuff <= '1';
Count: 366575
Threshold: 1
If statement on lines 2098 to 2100:
2098: if (sp_control_q_i /= NOMINAL_SAMPLE) then
2099: dbt_ctrs_en <= '1';
2100: end if;
Count: 366575
Threshold: 1
Signal assignment statement on line 2099:
2099: dbt_ctrs_en <= '1';
Count: 190599
Threshold: 1
If statement on lines 2102 to 2108:
2102: if (ctrl_ctr_zero = '1') then
2103: tick_state_reg <= '1';
...
2107: rx_store_stuff_count_i <= '1';
2108: end if;
Count: 366575
Threshold: 1
Signal assignment statement on line 2103:
2103: tick_state_reg <= '1';
Count: 86912
Threshold: 1
Signal assignment statement on line 2104:
2104: ctrl_ctr_pload_val <= crc_length_i;
Count: 86912
Threshold: 1
Signal assignment statement on line 2105:
2105: ctrl_ctr_pload_i <= '1';
Count: 86912
Threshold: 1
Signal assignment statement on line 2106:
2106: tx_load_crc_i <= '1';
Count: 86912
Threshold: 1
Signal assignment statement on line 2107:
2107: rx_store_stuff_count_i <= '1';
Count: 86912
Threshold: 1
Signal assignment statement on line 2114:
2114: ctrl_ctr_ena <= '1';
Count: 2902657
Threshold: 1
Signal assignment statement on line 2115:
2115: rx_shift_ena <= "1111";
Count: 2902657
Threshold: 1
Signal assignment statement on line 2116:
2116: tx_shift_ena_i <= '1';
Count: 2902657
Threshold: 1
Signal assignment statement on line 2117:
2117: err_pos <= ERC_POS_CRC;
Count: 2902657
Threshold: 1
Signal assignment statement on line 2118:
2118: pc_dbg.is_crc <= '1';
Count: 2902657
Threshold: 1
Signal assignment statement on line 2119:
2119: bit_err_disable_receiver <= '1';
Count: 2902657
Threshold: 1
If statement on lines 2121 to 2123:
2121: if (sp_control_q_i /= NOMINAL_SAMPLE) then
2122: dbt_ctrs_en <= '1';
2123: end if;
Count: 2902657
Threshold: 1
Signal assignment statement on line 2122:
2122: dbt_ctrs_en <= '1';
Count: 784476
Threshold: 1
If statement on lines 2125 to 2127:
2125: if (is_fd_frame = '1') then
2126: fixed_stuff <= '1';
2127: end if;
Count: 2902657
Threshold: 1
Signal assignment statement on line 2126:
2126: fixed_stuff <= '1';
Count: 1429429
Threshold: 1
If statement on lines 2129 to 2131:
2129: if (ctrl_ctr_zero = '1') then
2130: tick_state_reg <= '1';
2131: end if;
Count: 2902657
Threshold: 1
Signal assignment statement on line 2130:
2130: tick_state_reg <= '1';
Count: 251470
Threshold: 1
Signal assignment statement on line 2137:
2137: tick_state_reg <= '1';
Count: 175231
Threshold: 1
Signal assignment statement on line 2138:
2138: err_pos <= ERC_POS_ACK;
Count: 175231
Threshold: 1
Signal assignment statement on line 2139:
2139: pc_dbg.is_crc_delim <= '1';
Count: 175231
Threshold: 1
Signal assignment statement on line 2164:
2164: bit_err_disable <= '1';
Count: 175231
Threshold: 1
Signal assignment statement on line 2166:
2166: dbt_ctrs_en <= '1';
Count: 175231
Threshold: 1
Signal assignment statement on line 2167:
2167: destuff_enable_clear <= '1';
Count: 175231
Threshold: 1
Signal assignment statement on line 2168:
2168: stuff_enable_clear <= '1';
Count: 175231
Threshold: 1
If statement on lines 2170 to 2181:
2170: if (rx_trigger = '1') then
2171: crc_check <= '1';
...
2180: end if;
2181: end if;
Count: 175231
Threshold: 1
Signal assignment statement on line 2171:
2171: crc_check <= '1';
Count: 100758
Threshold: 1
If statement on lines 2173 to 2175:
2173: if (rx_data_nbs = DOMINANT) then
2174: form_err_i <= '1';
2175: end if;
Count: 100758
Threshold: 1
Signal assignment statement on line 2174:
2174: form_err_i <= '1';
Count: 34552
Threshold: 1
If statement on lines 2177 to 2180:
2177: if (sp_control_q_i = DATA_SAMPLE or sp_control_q_i = SECONDARY_SAMPLE) then
2178: sp_control_switch_nominal <= '1';
2179: br_shifted_i <= '1';
2180: end if;
Count: 100758
Threshold: 1
Signal assignment statement on line 2178:
2178: sp_control_switch_nominal <= '1';
Count: 21692
Threshold: 1
Signal assignment statement on line 2179:
2179: br_shifted_i <= '1';
Count: 21692
Threshold: 1
Signal assignment statement on line 2187:
2187: tick_state_reg <= '1';
Count: 182701
Threshold: 1
Signal assignment statement on line 2188:
2188: err_pos <= ERC_POS_ACK;
Count: 182701
Threshold: 1
Signal assignment statement on line 2189:
2189: pc_dbg.is_ack <= '1';
Count: 182701
Threshold: 1
Signal assignment statement on line 2190:
2190: dbt_ctrs_en <= '1';
Count: 182701
Threshold: 1
If statement on lines 2192 to 2194:
2192: if (tx_dominant_ack = '1') then
2193: tx_dominant <= '1';
2194: end if;
Count: 182701
Threshold: 1
Signal assignment statement on line 2193:
2193: tx_dominant <= '1';
Count: 94808
Threshold: 1
If statement on lines 2196 to 2198:
2196: if (allow_flipped_ack = '1') then
2197: bit_err_disable <= '1';
2198: end if;
Count: 182701
Threshold: 1
Signal assignment statement on line 2197:
2197: bit_err_disable <= '1';
Count: 97882
Threshold: 1
If statement on lines 2200 to 2202:
2200: if (is_receiver = '1' and crc_match = '1' and rx_data_nbs = DOMINANT) then
2201: decrement_rec_i <= '1';
2202: end if;
Count: 182701
Threshold: 1
Signal assignment statement on line 2201:
2201: decrement_rec_i <= '1';
Count: 24774
Threshold: 1
If statement on lines 2204 to 2206:
2204: if (is_transmitter = '1' and mr_mode_stm = '0' and rx_data_nbs = RECESSIVE) then
2205: ack_err_i <= '1';
2206: end if;
Count: 182701
Threshold: 1
Signal assignment statement on line 2205:
2205: ack_err_i <= '1';
Count: 45671
Threshold: 1
Signal assignment statement on line 2212:
2212: tick_state_reg <= '1';
Count: 118989
Threshold: 1
Signal assignment statement on line 2213:
2213: err_pos <= ERC_POS_ACK;
Count: 118989
Threshold: 1
Signal assignment statement on line 2214:
2214: pc_dbg.is_ack <= '1';
Count: 118989
Threshold: 1
Signal assignment statement on line 2215:
2215: dbt_ctrs_en <= '1';
Count: 118989
Threshold: 1
If statement on lines 2217 to 2219:
2217: if (tx_dominant_ack = '1') then
2218: tx_dominant <= '1';
2219: end if;
Count: 118989
Threshold: 1
Signal assignment statement on line 2218:
2218: tx_dominant <= '1';
Count: 52397
Threshold: 1
If statement on lines 2221 to 2223:
2221: if (allow_flipped_ack = '1') then
2222: bit_err_disable <= '1';
2223: end if;
Count: 118989
Threshold: 1
Signal assignment statement on line 2222:
2222: bit_err_disable <= '1';
Count: 71757
Threshold: 1
If statement on lines 2225 to 2227:
2225: if (is_receiver = '1' and crc_match = '1' and rx_data_nbs = DOMINANT) then
2226: decrement_rec_i <= '1';
2227: end if;
Count: 118989
Threshold: 1
Signal assignment statement on line 2226:
2226: decrement_rec_i <= '1';
Count: 15900
Threshold: 1
Signal assignment statement on line 2233:
2233: tick_state_reg <= '1';
Count: 62562
Threshold: 1
Signal assignment statement on line 2234:
2234: err_pos <= ERC_POS_ACK;
Count: 62562
Threshold: 1
Signal assignment statement on line 2235:
2235: pc_dbg.is_ack <= '1';
Count: 62562
Threshold: 1
Signal assignment statement on line 2236:
2236: dbt_ctrs_en <= '1';
Count: 62562
Threshold: 1
Signal assignment statement on line 2239:
2239: bit_err_disable <= '1';
Count: 62562
Threshold: 1
If statement on lines 2242 to 2246:
2242: if (is_transmitter = '1' and mr_mode_stm = '0' and
2243: rx_data_nbs = RECESSIVE and rx_data_nbs_prev = RECESSIVE)
2244: then
2245: ack_err_i <= '1';
2246: end if;
Count: 62562
Threshold: 1
Signal assignment statement on line 2245:
2245: ack_err_i <= '1';
Count: 1197
Threshold: 1
Signal assignment statement on line 2252:
2252: tick_state_reg <= '1';
Count: 129041
Threshold: 1
Signal assignment statement on line 2253:
2253: ctrl_ctr_pload_i <= '1';
Count: 129041
Threshold: 1
Signal assignment statement on line 2254:
2254: ctrl_ctr_pload_val <= C_EOF_DURATION;
Count: 129041
Threshold: 1
Signal assignment statement on line 2255:
2255: err_pos <= ERC_POS_ACK;
Count: 129041
Threshold: 1
Signal assignment statement on line 2256:
2256: pc_dbg.is_ack_delim <= '1';
Count: 129041
Threshold: 1
Signal assignment statement on line 2257:
2257: bit_err_disable <= '1';
Count: 129041
Threshold: 1
If statement on lines 2259 to 2261:
2259: if (rx_data_nbs = DOMINANT) then
2260: form_err_i <= '1';
2261: end if;
Count: 129041
Threshold: 1
Signal assignment statement on line 2260:
2260: form_err_i <= '1';
Count: 49241
Threshold: 1
If statement on lines 2263 to 2265:
2263: if (is_receiver = '1' and crc_match = '0') then
2264: crc_err_i <= '1';
2265: end if;
Count: 129041
Threshold: 1
Signal assignment statement on line 2264:
2264: crc_err_i <= '1';
Count: 6188
Threshold: 1
Signal assignment statement on line 2272:
2272: ctrl_ctr_ena <= '1';
Count: 510814
Threshold: 1
Signal assignment statement on line 2273:
2273: pc_dbg.is_eof <= '1';
Count: 510814
Threshold: 1
Signal assignment statement on line 2274:
2274: err_pos <= ERC_POS_EOF;
Count: 510814
Threshold: 1
Signal assignment statement on line 2275:
2275: bit_err_disable <= '1';
Count: 510814
Threshold: 1
If statement on lines 2277 to 2299:
2277: if (ctrl_ctr_zero = '1') then
2278: tick_state_reg <= '1';
...
2298: crc_clear_match_flag <= '1';
2299: end if;
Count: 510814
Threshold: 1
Signal assignment statement on line 2278:
2278: tick_state_reg <= '1';
Count: 134706
Threshold: 1
Signal assignment statement on line 2279:
2279: ctrl_ctr_pload_i <= '1';
Count: 134706
Threshold: 1
If statement on lines 2281 to 2296:
2281: if (rx_data_nbs = RECESSIVE) then
2282: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
...
2295: end if;
2296: end if;
Count: 134706
Threshold: 1
Signal assignment statement on line 2282:
2282: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
Count: 134268
Threshold: 1
If statement on lines 2285 to 2287:
2285: if (is_transmitter = '1') then
2286: txtb_hw_cmd_d.valid <= '1';
2287: end if;
Count: 134268
Threshold: 1
Signal assignment statement on line 2286:
2286: txtb_hw_cmd_d.valid <= '1';
Count: 44606
Threshold: 1
If statement on lines 2290 to 2295:
2290: if (mr_mode_rom = ROM_DISABLED) then
2291: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2292: else
2293: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2294: set_idle_i <= '1';
2295: end if;
Count: 387
Threshold: 1
Signal assignment statement on line 2291:
2291: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
Count: 379
Threshold: 1
Signal assignment statement on line 2293:
2293: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 8
Threshold: 1
Signal assignment statement on line 2294:
2294: set_idle_i <= '1';
Count: 8
Threshold: 1
Signal assignment statement on line 2298:
2298: crc_clear_match_flag <= '1';
Count: 134706
Threshold: 1
If statement on lines 2303 to 2305:
2303: if (ctrl_ctr_one = '1' and rx_data_nbs = RECESSIVE) then
2304: rec_valid_d <= '1';
2305: end if;
Count: 510814
Threshold: 1
Signal assignment statement on line 2304:
2304: rec_valid_d <= '1';
Count: 78065
Threshold: 1
If statement on lines 2310 to 2316:
2310: if (rx_data_nbs = DOMINANT) then
2311: if (ctrl_ctr_zero = '0') then
...
2315: end if;
2316: end if;
Count: 510814
Threshold: 1
If statement on lines 2311 to 2315:
2311: if (ctrl_ctr_zero = '0') then
2312: form_err_i <= '1';
2313: elsif (is_transmitter = '1') then
2314: form_err_i <= '1';
2315: end if;
Count: 4105
Threshold: 1
Signal assignment statement on line 2312:
2312: form_err_i <= '1';
Count: 3667
Threshold: 1
Signal assignment statement on line 2314:
2314: form_err_i <= '1';
Count: 51
Threshold: 1
Signal assignment statement on line 2322:
2322: ctrl_ctr_ena <= '1';
Count: 547806
Threshold: 1
Signal assignment statement on line 2323:
2323: pc_dbg.is_intermission <= '1';
Count: 547806
Threshold: 1
Signal assignment statement on line 2324:
2324: retr_ctr_add_block_clr <= '1';
Count: 547806
Threshold: 1
Signal assignment statement on line 2325:
2325: bit_err_disable <= '1';
Count: 547806
Threshold: 1
If statement on lines 2328 to 2394:
2328: if (is_bus_off = '1') then
2329: tick_state_reg <= '1';
...
2393:
2394: end if;
Count: 547806
Threshold: 1
Signal assignment statement on line 2329:
2329: tick_state_reg <= '1';
Count: 432
Threshold: 1
If statement on lines 2333 to 2392:
2333: if (ctrl_ctr_zero = '1') then
2334: tick_state_reg <= '1';
...
2391: end if;
2392: end if;
Count: 547374
Threshold: 1
Signal assignment statement on line 2334:
2334: tick_state_reg <= '1';
Count: 210158
Threshold: 1
Signal assignment statement on line 2335:
2335: ctrl_ctr_pload_i <= '1';
Count: 210158
Threshold: 1
Signal assignment statement on line 2336:
2336: crc_spec_enable_i <= '1';
Count: 210158
Threshold: 1
If statement on lines 2339 to 2350:
2339: if (rx_data_nbs = DOMINANT) then
2340: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
...
2349: ctrl_ctr_pload_val <= C_SUSPEND_DURATION;
2350: end if;
Count: 210158
Threshold: 1
Signal assignment statement on line 2340:
2340: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
Count: 2233
Threshold: 1
Signal assignment statement on line 2341:
2341: tx_load_base_id_i <= '1';
Count: 2233
Threshold: 1
Signal assignment statement on line 2342:
2342: sof_pulse_i <= '1';
Count: 2233
Threshold: 1
Signal assignment statement on line 2343:
2343: rec_ivld_i <= '0';
Count: 2233
Threshold: 1
Signal assignment statement on line 2349:
2349: ctrl_ctr_pload_val <= C_SUSPEND_DURATION;
Count: 207925
Threshold: 1
If statement on lines 2354 to 2365:
2354: if (tran_frame_valid = '1' and go_to_suspend = '0') then
2355: txtb_hw_cmd_d.lock <= '1';
...
2364: set_receiver_i <= '1';
2365: end if;
Count: 210158
Threshold: 1
Signal assignment statement on line 2355:
2355: txtb_hw_cmd_d.lock <= '1';
Count: 32227
Threshold: 1
Signal assignment statement on line 2356:
2356: set_transmitter_i <= '1';
Count: 32227
Threshold: 1
Signal assignment statement on line 2357:
2357: stuff_enable_set <= '1';
Count: 32227
Threshold: 1
If statement on lines 2359 to 2361:
2359: if (rx_data_nbs = DOMINANT) then
2360: tx_frame_no_sof_d <= '1';
2361: end if;
Count: 32227
Threshold: 1
Signal assignment statement on line 2360:
2360: tx_frame_no_sof_d <= '1';
Count: 1033
Threshold: 1
Signal assignment statement on line 2364:
2364: set_receiver_i <= '1';
Count: 1200
Threshold: 1
If statement on lines 2369 to 2372:
2369: if (frame_start = '1') then
2370: destuff_enable_set <= '1';
2371: rx_clear_i <= '1';
2372: end if;
Count: 210158
Threshold: 1
Signal assignment statement on line 2370:
2370: destuff_enable_set <= '1';
Count: 32971
Threshold: 1
Signal assignment statement on line 2371:
2371: rx_clear_i <= '1';
Count: 32971
Threshold: 1
If statement on lines 2376 to 2380:
2376: if (rx_data_nbs = RECESSIVE and tran_frame_valid = '0' and
2377: go_to_suspend = '0')
2378: then
2379: set_idle_i <= '1';
2380: end if;
Count: 210158
Threshold: 1
Signal assignment statement on line 2379:
2379: set_idle_i <= '1';
Count: 165108
Threshold: 1
Signal assignment statement on line 2384:
2384: tick_state_reg <= '1';
Count: 935
Threshold: 1
Signal assignment statement on line 2385:
2385: ctrl_ctr_pload_i <= '1';
Count: 935
Threshold: 1
If statement on lines 2386 to 2391:
2386: if (mr_mode_rom = ROM_DISABLED) then
2387: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2388: else
2389: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2390: set_idle_i <= '1';
2391: end if;
Count: 935
Threshold: 1
Signal assignment statement on line 2387:
2387: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
Count: 875
Threshold: 1
Signal assignment statement on line 2389:
2389: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 60
Threshold: 1
Signal assignment statement on line 2390:
2390: set_idle_i <= '1';
Count: 60
Threshold: 1
If statement on lines 2397 to 2399:
2397: if (ctrl_ctr_zero = '1' or ctrl_ctr_one = '1') then
2398: perform_hsync <= '1';
2399: end if;
Count: 547806
Threshold: 1
Signal assignment statement on line 2398:
2398: perform_hsync <= '1';
Count: 365918
Threshold: 1
If statement on lines 2402 to 2404:
2402: if (ctrl_ctr_zero = '0') then
2403: load_init_vect_i <= '1';
2404: end if;
Count: 547806
Threshold: 1
Signal assignment statement on line 2403:
2403: load_init_vect_i <= '1';
Count: 337540
Threshold: 1
Signal assignment statement on line 2410:
2410: ctrl_ctr_ena <= '1';
Count: 55228
Threshold: 1
Signal assignment statement on line 2411:
2411: perform_hsync <= '1';
Count: 55228
Threshold: 1
Signal assignment statement on line 2412:
2412: crc_spec_enable_i <= '1';
Count: 55228
Threshold: 1
Signal assignment statement on line 2413:
2413: bit_err_disable <= '1';
Count: 55228
Threshold: 1
Signal assignment statement on line 2414:
2414: pc_dbg.is_suspend <= '1';
Count: 55228
Threshold: 1
If statement on lines 2416 to 2440:
2416: if (rx_data_nbs = DOMINANT) then
2417: tick_state_reg <= '1';
...
2439: end if;
2440: end if;
Count: 55228
Threshold: 1
Signal assignment statement on line 2417:
2417: tick_state_reg <= '1';
Count: 279
Threshold: 1
Signal assignment statement on line 2418:
2418: ctrl_ctr_pload_i <= '1';
Count: 279
Threshold: 1
Signal assignment statement on line 2419:
2419: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
Count: 279
Threshold: 1
Signal assignment statement on line 2420:
2420: tx_load_base_id_i <= '1';
Count: 279
Threshold: 1
Signal assignment statement on line 2421:
2421: sof_pulse_i <= '1';
Count: 279
Threshold: 1
Signal assignment statement on line 2422:
2422: rec_ivld_i <= '0';
Count: 279
Threshold: 1
Signal assignment statement on line 2423:
2423: set_receiver_i <= '1';
Count: 279
Threshold: 1
Signal assignment statement on line 2424:
2424: destuff_enable_set <= '1';
Count: 279
Threshold: 1
Signal assignment statement on line 2425:
2425: rx_clear_i <= '1';
Count: 279
Threshold: 1
Signal assignment statement on line 2430:
2430: tick_state_reg <= '1';
Count: 10987
Threshold: 1
If statement on lines 2431 to 2439:
2431: if (tran_frame_valid = '1') then
2432: set_transmitter_i <= '1';
...
2438: set_idle_i <= '1';
2439: end if;
Count: 10987
Threshold: 1
Signal assignment statement on line 2432:
2432: set_transmitter_i <= '1';
Count: 1551
Threshold: 1
Signal assignment statement on line 2433:
2433: txtb_hw_cmd_d.lock <= '1';
Count: 1551
Threshold: 1
Signal assignment statement on line 2434:
2434: rx_clear_i <= '1';
Count: 1551
Threshold: 1
Signal assignment statement on line 2435:
2435: destuff_enable_set <= '1';
Count: 1551
Threshold: 1
Signal assignment statement on line 2436:
2436: stuff_enable_set <= '1';
Count: 1551
Threshold: 1
Signal assignment statement on line 2438:
2438: set_idle_i <= '1';
Count: 9436
Threshold: 1
Signal assignment statement on line 2446:
2446: perform_hsync <= '1';
Count: 5930037
Threshold: 1
Signal assignment statement on line 2447:
2447: crc_spec_enable_i <= '1';
Count: 5930037
Threshold: 1
Signal assignment statement on line 2448:
2448: bit_err_disable <= '1';
Count: 5930037
Threshold: 1
If statement on lines 2450 to 2485:
2450: if (is_bus_off = '0') then
2451: if (rx_data_nbs = DOMINANT) then
...
2484: tick_state_reg <= '1';
2485: end if;
Count: 5930037
Threshold: 1
If statement on lines 2451 to 2458:
2451: if (rx_data_nbs = DOMINANT) then
2452: tick_state_reg <= '1';
...
2457: crc_enable <= '1';
2458: end if;
Count: 5923129
Threshold: 1
Signal assignment statement on line 2452:
2452: tick_state_reg <= '1';
Count: 82873
Threshold: 1
Signal assignment statement on line 2453:
2453: ctrl_ctr_pload_i <= '1';
Count: 82873
Threshold: 1
Signal assignment statement on line 2454:
2454: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
Count: 82873
Threshold: 1
Signal assignment statement on line 2455:
2455: sof_pulse_i <= '1';
Count: 82873
Threshold: 1
Signal assignment statement on line 2456:
2456: rec_ivld_i <= '0';
Count: 82873
Threshold: 1
Signal assignment statement on line 2457:
2457: crc_enable <= '1';
Count: 82873
Threshold: 1
If statement on lines 2460 to 2473:
2460: if (tran_frame_valid = '1') then
2461: tick_state_reg <= '1';
...
2472: set_receiver_i <= '1';
2473: end if;
Count: 5923129
Threshold: 1
Signal assignment statement on line 2461:
2461: tick_state_reg <= '1';
Count: 58695
Threshold: 1
Signal assignment statement on line 2462:
2462: txtb_hw_cmd_d.lock <= '1';
Count: 58695
Threshold: 1
Signal assignment statement on line 2463:
2463: set_transmitter_i <= '1';
Count: 58695
Threshold: 1
Signal assignment statement on line 2464:
2464: tx_load_base_id_i <= '1';
Count: 58695
Threshold: 1
Signal assignment statement on line 2465:
2465: stuff_enable_set <= '1';
Count: 58695
Threshold: 1
If statement on lines 2467 to 2469:
2467: if (rx_data_nbs = DOMINANT) then
2468: tx_frame_no_sof_d <= '1';
2469: end if;
Count: 58695
Threshold: 1
Signal assignment statement on line 2468:
2468: tx_frame_no_sof_d <= '1';
Count: 24
Threshold: 1
Signal assignment statement on line 2472:
2472: set_receiver_i <= '1';
Count: 82849
Threshold: 1
If statement on lines 2477 to 2480:
2477: if (frame_start = '1') then
2478: destuff_enable_set <= '1';
2479: rx_clear_i <= '1';
2480: end if;
Count: 5923129
Threshold: 1
Signal assignment statement on line 2478:
2478: destuff_enable_set <= '1';
Count: 91515
Threshold: 1
Signal assignment statement on line 2479:
2479: rx_clear_i <= '1';
Count: 91515
Threshold: 1
Signal assignment statement on line 2484:
2484: tick_state_reg <= '1';
Count: 6908
Threshold: 1
Signal assignment statement on line 2491:
2491: bit_err_disable <= '1';
Count: 8603
Threshold: 1
If statement on lines 2493 to 2499:
2493: if (mr_command_ercrst_q = '1') then
2494: tick_state_reg <= '1';
...
2498: clr_bus_off_rst_flg <= '1';
2499: end if;
Count: 8603
Threshold: 1
Signal assignment statement on line 2494:
2494: tick_state_reg <= '1';
Count: 425
Threshold: 1
Signal assignment statement on line 2495:
2495: ctrl_ctr_pload_i <= '1';
Count: 425
Threshold: 1
Signal assignment statement on line 2496:
2496: reinteg_ctr_clr <= '1';
Count: 425
Threshold: 1
Signal assignment statement on line 2497:
2497: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 425
Threshold: 1
Signal assignment statement on line 2498:
2498: clr_bus_off_rst_flg <= '1';
Count: 425
Threshold: 1
Signal assignment statement on line 2505:
2505: ctrl_ctr_ena <= '1';
Count: 560353
Threshold: 1
Signal assignment statement on line 2506:
2506: perform_hsync <= '1';
Count: 560353
Threshold: 1
Signal assignment statement on line 2507:
2507: bit_err_disable <= '1';
Count: 560353
Threshold: 1
If statement on lines 2510 to 2512:
2510: if (rx_data_nbs = DOMINANT or sync_edge = '1') then
2511: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2512: end if;
Count: 560353
Threshold: 1
Signal assignment statement on line 2511:
2511: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 6837
Threshold: 1
If statement on lines 2515 to 2517:
2515: if (rx_data_nbs = DOMINANT) then
2516: ctrl_ctr_pload_i <= '1';
2517: end if;
Count: 560353
Threshold: 1
Signal assignment statement on line 2516:
2516: ctrl_ctr_pload_i <= '1';
Count: 4773
Threshold: 1
If statement on lines 2519 to 2521:
2519: if (integ_restart_edge = '1') then
2520: ctrl_ctr_pload_unaliged <= '1';
2521: end if;
Count: 560353
Threshold: 1
Signal assignment statement on line 2520:
2520: ctrl_ctr_pload_unaliged <= '1';
Count: 2064
Threshold: 1
If statement on lines 2523 to 2525:
2523: if (ctrl_ctr_zero = '1') then
2524: reinteg_ctr_enable <= '1';
2525: end if;
Count: 560353
Threshold: 1
Signal assignment statement on line 2524:
2524: reinteg_ctr_enable <= '1';
Count: 65822
Threshold: 1
If statement on lines 2527 to 2530:
2527: if (ctrl_ctr_zero = '1' and reinteg_ctr_expired = '0') then
2528: ctrl_ctr_pload_i <= '1';
2529: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2530: end if;
Count: 560353
Threshold: 1
Signal assignment statement on line 2528:
2528: ctrl_ctr_pload_i <= '1';
Count: 65312
Threshold: 1
Signal assignment statement on line 2529:
2529: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
Count: 65312
Threshold: 1
If statement on lines 2532 to 2537:
2532: if (reinteg_ctr_expired = '1' and ctrl_ctr_zero = '1' and rx_trigger = '1') then
2533: tick_state_reg <= '1';
2534: set_idle_i <= '1';
2535: set_err_active_i <= '1';
2536: load_init_vect_i <= '1';
2537: end if;
Count: 560353
Threshold: 1
Signal assignment statement on line 2533:
2533: tick_state_reg <= '1';
Count: 340
Threshold: 1
Signal assignment statement on line 2534:
2534: set_idle_i <= '1';
Count: 340
Threshold: 1
Signal assignment statement on line 2535:
2535: set_err_active_i <= '1';
Count: 340
Threshold: 1
Signal assignment statement on line 2536:
2536: load_init_vect_i <= '1';
Count: 340
Threshold: 1
Signal assignment statement on line 2543:
2543: ctrl_ctr_ena <= '1';
Count: 386464
Threshold: 1
Signal assignment statement on line 2544:
2544: pc_dbg.is_err <= '1';
Count: 386464
Threshold: 1
Signal assignment statement on line 2545:
2545: tx_dominant <= '1';
Count: 386464
Threshold: 1
Signal assignment statement on line 2546:
2546: err_pos <= ERC_POS_ERR;
Count: 386464
Threshold: 1
If statement on lines 2548 to 2553:
2548: if (ctrl_ctr_zero = '1') then
2549: tick_state_reg <= '1';
2550: ctrl_ctr_pload_i <= '1';
2551: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
2552: first_err_delim_d <= '1';
2553: end if;
Count: 386464
Threshold: 1
Signal assignment statement on line 2549:
2549: tick_state_reg <= '1';
Count: 58123
Threshold: 1
Signal assignment statement on line 2550:
2550: ctrl_ctr_pload_i <= '1';
Count: 58123
Threshold: 1
Signal assignment statement on line 2551:
2551: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
Count: 58123
Threshold: 1
Signal assignment statement on line 2552:
2552: first_err_delim_d <= '1';
Count: 58123
Threshold: 1
Signal assignment statement on line 2559:
2559: ctrl_ctr_ena <= '1';
Count: 147284
Threshold: 1
Signal assignment statement on line 2560:
2560: pc_dbg.is_err <= '1';
Count: 147284
Threshold: 1
Signal assignment statement on line 2561:
2561: err_pos <= ERC_POS_ERR;
Count: 147284
Threshold: 1
Signal assignment statement on line 2565:
2565: bit_err_disable <= '1';
Count: 147284
Threshold: 1
If statement on lines 2569 to 2577:
2569: if (rx_data_nbs_prev /= rx_data_nbs) then
2570: ctrl_ctr_pload_i <= '1';
...
2576: first_err_delim_d <= '1';
2577: end if;
Count: 147284
Threshold: 1
Signal assignment statement on line 2570:
2570: ctrl_ctr_pload_i <= '1';
Count: 14405
Threshold: 1
Signal assignment statement on line 2571:
2571: ctrl_ctr_pload_val <= C_SHORTENED_ERR_FLG_DURATION;
Count: 14405
Threshold: 1
Signal assignment statement on line 2573:
2573: tick_state_reg <= '1';
Count: 24870
Threshold: 1
Signal assignment statement on line 2574:
2574: ctrl_ctr_pload_i <= '1';
Count: 24870
Threshold: 1
Signal assignment statement on line 2575:
2575: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
Count: 24870
Threshold: 1
Signal assignment statement on line 2576:
2576: first_err_delim_d <= '1';
Count: 24870
Threshold: 1
If statement on lines 2581 to 2584:
2581: if (ack_err_flag = '1' and rx_data_nbs = DOMINANT and rx_trigger = '1') then
2582: bit_err_after_ack_err <= '1';
2583: ack_err_flag_clr <= '1';
2584: end if;
Count: 147284
Threshold: 1
Signal assignment statement on line 2582:
2582: bit_err_after_ack_err <= '1';
Count: 16
Threshold: 1
Signal assignment statement on line 2583:
2583: ack_err_flag_clr <= '1';
Count: 16
Threshold: 1
Signal assignment statement on line 2590:
2590: pc_dbg.is_err <= '1';
Count: 200274
Threshold: 1
Signal assignment statement on line 2591:
2591: err_pos <= ERC_POS_ERR;
Count: 200274
Threshold: 1
Signal assignment statement on line 2592:
2592: ack_err_flag_clr <= '1';
Count: 200274
Threshold: 1
Signal assignment statement on line 2596:
2596: bit_err_disable <= '1';
Count: 200274
Threshold: 1
If statement on lines 2598 to 2602:
2598: if (ctrl_ctr_zero = '0') then
2599: ctrl_ctr_ena <= '1';
2600: else
2601: tick_state_reg <= '1';
2602: end if;
Count: 200274
Threshold: 1
Signal assignment statement on line 2599:
2599: ctrl_ctr_ena <= '1';
Count: 168885
Threshold: 1
Signal assignment statement on line 2601:
2601: tick_state_reg <= '1';
Count: 31389
Threshold: 1
If statement on lines 2604 to 2608:
2604: if (rx_data_nbs = RECESSIVE) then
2605: tick_state_reg <= '1';
2606: ctrl_ctr_pload_i <= '1';
2607: ctrl_ctr_pload_val <= C_ERR_DELIM_DURATION;
2608: end if;
Count: 200274
Threshold: 1
Signal assignment statement on line 2605:
2605: tick_state_reg <= '1';
Count: 77250
Threshold: 1
Signal assignment statement on line 2606:
2606: ctrl_ctr_pload_i <= '1';
Count: 77250
Threshold: 1
Signal assignment statement on line 2607:
2607: ctrl_ctr_pload_val <= C_ERR_DELIM_DURATION;
Count: 77250
Threshold: 1
If statement on lines 2612 to 2615:
2612: if (rx_data_nbs = DOMINANT and first_err_delim_q = '1') then
2613: primary_err_i <= '1';
2614: first_err_delim_d <= '0';
2615: end if;
Count: 200274
Threshold: 1
Signal assignment statement on line 2613:
2613: primary_err_i <= '1';
Count: 86453
Threshold: 1
Signal assignment statement on line 2614:
2614: first_err_delim_d <= '0';
Count: 86453
Threshold: 1
Signal assignment statement on line 2622:
2622: pc_dbg.is_err <= '1';
Count: 5861
Threshold: 1
Signal assignment statement on line 2623:
2623: err_pos <= ERC_POS_ERR;
Count: 5861
Threshold: 1
Signal assignment statement on line 2624:
2624: bit_err_disable <= '1';
Count: 5861
Threshold: 1
Signal assignment statement on line 2625:
2625: ctrl_ctr_ena <= '1';
Count: 5861
Threshold: 1
If statement on lines 2627 to 2639:
2627: if (rx_data_nbs = RECESSIVE) then
2628: tick_state_reg <= '1';
...
2638: err_delim_late_i <= '1';
2639: end if;
Count: 5861
Threshold: 1
Signal assignment statement on line 2628:
2628: tick_state_reg <= '1';
Count: 311
Threshold: 1
Signal assignment statement on line 2629:
2629: ctrl_ctr_pload_i <= '1';
Count: 311
Threshold: 1
Signal assignment statement on line 2630:
2630: ctrl_ctr_pload_val <= C_ERR_DELIM_DURATION;
Count: 311
Threshold: 1
Signal assignment statement on line 2635:
2635: tick_state_reg <= '1';
Count: 1190
Threshold: 1
Signal assignment statement on line 2636:
2636: ctrl_ctr_pload_i <= '1';
Count: 1190
Threshold: 1
Signal assignment statement on line 2637:
2637: ctrl_ctr_pload_val <= C_DOMINANT_REPEAT_DURATION;
Count: 1190
Threshold: 1
Signal assignment statement on line 2638:
2638: err_delim_late_i <= '1';
Count: 1190
Threshold: 1
Signal assignment statement on line 2645:
2645: pc_dbg.is_overload <= '1';
Count: 926
Threshold: 1
Signal assignment statement on line 2646:
2646: err_pos <= ERC_POS_OVRL;
Count: 926
Threshold: 1
Signal assignment statement on line 2647:
2647: bit_err_disable <= '1';
Count: 926
Threshold: 1
Signal assignment statement on line 2648:
2648: ctrl_ctr_ena <= '1';
Count: 926
Threshold: 1
If statement on lines 2650 to 2662:
2650: if (rx_data_nbs = RECESSIVE) then
2651: tick_state_reg <= '1';
...
2661: err_delim_late_i <= '1';
2662: end if;
Count: 926
Threshold: 1
Signal assignment statement on line 2651:
2651: tick_state_reg <= '1';
Count: 78
Threshold: 1
Signal assignment statement on line 2652:
2652: ctrl_ctr_pload_i <= '1';
Count: 78
Threshold: 1
Signal assignment statement on line 2653:
2653: ctrl_ctr_pload_val <= C_OVR_DELIM_DURATION;
Count: 78
Threshold: 1
Signal assignment statement on line 2658:
2658: tick_state_reg <= '1';
Count: 224
Threshold: 1
Signal assignment statement on line 2659:
2659: ctrl_ctr_pload_i <= '1';
Count: 224
Threshold: 1
Signal assignment statement on line 2660:
2660: ctrl_ctr_pload_val <= C_DOMINANT_REPEAT_DURATION;
Count: 224
Threshold: 1
Signal assignment statement on line 2661:
2661: err_delim_late_i <= '1';
Count: 224
Threshold: 1
Signal assignment statement on line 2668:
2668: pc_dbg.is_err <= '1';
Count: 444467
Threshold: 1
Signal assignment statement on line 2669:
2669: ctrl_ctr_ena <= '1';
Count: 444467
Threshold: 1
Signal assignment statement on line 2670:
2670: err_pos <= ERC_POS_ERR;
Count: 444467
Threshold: 1
Signal assignment statement on line 2671:
2671: bit_err_disable <= '1';
Count: 444467
Threshold: 1
If statement on lines 2673 to 2684:
2673: if (ctrl_ctr_zero = '1') then
2674: tick_state_reg <= '1';
...
2683: form_err_i <= '1';
2684: end if;
Count: 444467
Threshold: 1
Signal assignment statement on line 2674:
2674: tick_state_reg <= '1';
Count: 79359
Threshold: 1
Signal assignment statement on line 2675:
2675: ctrl_ctr_pload_i <= '1';
Count: 79359
Threshold: 1
If statement on lines 2677 to 2681:
2677: if (rx_data_nbs = DOMINANT) then
2678: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2679: else
2680: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
2681: end if;
Count: 79359
Threshold: 1
Signal assignment statement on line 2678:
2678: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
Count: 376
Threshold: 1
Signal assignment statement on line 2680:
2680: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
Count: 78983
Threshold: 1
Signal assignment statement on line 2683:
2683: form_err_i <= '1';
Count: 697
Threshold: 1
Signal assignment statement on line 2690:
2690: pc_dbg.is_overload <= '1';
Count: 9030
Threshold: 1
Signal assignment statement on line 2691:
2691: ctrl_ctr_ena <= '1';
Count: 9030
Threshold: 1
Signal assignment statement on line 2692:
2692: tx_dominant <= '1';
Count: 9030
Threshold: 1
Signal assignment statement on line 2693:
2693: err_pos <= ERC_POS_OVRL;
Count: 9030
Threshold: 1
If statement on lines 2695 to 2699:
2695: if (ctrl_ctr_zero = '1') then
2696: tick_state_reg <= '1';
2697: ctrl_ctr_pload_i <= '1';
2698: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
2699: end if;
Count: 9030
Threshold: 1
Signal assignment statement on line 2696:
2696: tick_state_reg <= '1';
Count: 1736
Threshold: 1
Signal assignment statement on line 2697:
2697: ctrl_ctr_pload_i <= '1';
Count: 1736
Threshold: 1
Signal assignment statement on line 2698:
2698: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
Count: 1736
Threshold: 1
Signal assignment statement on line 2705:
2705: pc_dbg.is_overload <= '1';
Count: 3563
Threshold: 1
Signal assignment statement on line 2706:
2706: err_pos <= ERC_POS_OVRL;
Count: 3563
Threshold: 1
If statement on lines 2708 to 2712:
2708: if (ctrl_ctr_zero = '0') then
2709: ctrl_ctr_ena <= '1';
2710: else
2711: tick_state_reg <= '1';
2712: end if;
Count: 3563
Threshold: 1
Signal assignment statement on line 2709:
2709: ctrl_ctr_ena <= '1';
Count: 2996
Threshold: 1
Signal assignment statement on line 2711:
2711: tick_state_reg <= '1';
Count: 567
Threshold: 1
Signal assignment statement on line 2716:
2716: bit_err_disable <= '1';
Count: 3563
Threshold: 1
If statement on lines 2718 to 2722:
2718: if (rx_data_nbs = RECESSIVE) then
2719: tick_state_reg <= '1';
2720: ctrl_ctr_pload_i <= '1';
2721: ctrl_ctr_pload_val <= C_OVR_DELIM_DURATION;
2722: end if;
Count: 3563
Threshold: 1
Signal assignment statement on line 2719:
2719: tick_state_reg <= '1';
Count: 1119
Threshold: 1
Signal assignment statement on line 2720:
2720: ctrl_ctr_pload_i <= '1';
Count: 1119
Threshold: 1
Signal assignment statement on line 2721:
2721: ctrl_ctr_pload_val <= C_OVR_DELIM_DURATION;
Count: 1119
Threshold: 1
Signal assignment statement on line 2728:
2728: ctrl_ctr_ena <= '1';
Count: 7582
Threshold: 1
Signal assignment statement on line 2729:
2729: pc_dbg.is_overload <= '1';
Count: 7582
Threshold: 1
Signal assignment statement on line 2730:
2730: err_pos <= ERC_POS_OVRL;
Count: 7582
Threshold: 1
Signal assignment statement on line 2731:
2731: bit_err_disable <= '1';
Count: 7582
Threshold: 1
If statement on lines 2733 to 2744:
2733: if (ctrl_ctr_zero = '1') then
2734: tick_state_reg <= '1';
...
2743: form_err_i <= '1';
2744: end if;
Count: 7582
Threshold: 1
Signal assignment statement on line 2734:
2734: tick_state_reg <= '1';
Count: 1314
Threshold: 1
Signal assignment statement on line 2735:
2735: ctrl_ctr_pload_i <= '1';
Count: 1314
Threshold: 1
If statement on lines 2737 to 2741:
2737: if (rx_data_nbs = DOMINANT) then
2738: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2739: else
2740: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
2741: end if;
Count: 1314
Threshold: 1
Signal assignment statement on line 2738:
2738: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
Count: 92
Threshold: 1
Signal assignment statement on line 2740:
2740: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
Count: 1222
Threshold: 1
Signal assignment statement on line 2743:
2743: form_err_i <= '1';
Count: 244
Threshold: 1
If statement on lines 2754 to 2756:
2754: state_reg_ce <= '1' when (tick_state_reg = '1' and ctrl_signal_upd = '1')
2755: else
2756: '0';
Count: 21661691
Threshold: 1
Signal assignment statement on line 2754:
2754: state_reg_ce <= '1' when (tick_state_reg = '1' and ctrl_signal_upd = '1')
Count: 1156664
Threshold: 1
Signal assignment statement on line 2756:
2756: '0';
Count: 20505027
Threshold: 1
If statement on lines 2760 to 2766:
2760: if (rst_n = '0') then
2761: curr_state <= s_pc_off;
...
2765: end if;
2766: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 2761:
2761: curr_state <= s_pc_off;
Count: 2422674
Threshold: 1
If statement on lines 2763 to 2765:
2763: if (state_reg_ce = '1') then
2764: curr_state <= next_state;
2765: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 2764:
2764: curr_state <= next_state;
Count: 832745
Threshold: 1
If statement on lines 2777 to 2780:
2777: ctrl_ctr_pload <= ctrl_ctr_pload_i when (curr_state = s_pc_off) else
2778: ctrl_ctr_pload_i when (ctrl_signal_upd = '1') else
2779: '1' when (ctrl_ctr_pload_unaliged = '1') else
2780: '0';
Count: 22597073
Threshold: 1
Signal assignment statement on line 2777:
2777: ctrl_ctr_pload <= ctrl_ctr_pload_i when (curr_state = s_pc_off) else
Count: 29257
Threshold: 1
Signal assignment statement on line 2778:
2778: ctrl_ctr_pload_i when (ctrl_signal_upd = '1') else
Count: 12044988
Threshold: 1
Signal assignment statement on line 2779:
2779: '1' when (ctrl_ctr_pload_unaliged = '1') else
Count: 3605
Threshold: 1
Signal assignment statement on line 2780:
2780: '0';
Count: 10519223
Threshold: 1
If statement on lines 2790 to 2812:
2790: if (rst_n = '0') then
2791: store_metadata <= '0';
...
2811:
2812: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 2791:
2791: store_metadata <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2792:
2792: store_data <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2793:
2793: rec_valid <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2794:
2794: rec_abort <= '0';
Count: 2422674
Threshold: 1
If statement on lines 2799 to 2808:
2799: if ((is_receiver = '1' or mr_settings_ilbp = '1') and (rx_trigger = '1'))
2800: then
...
2807: rec_valid <= '0';
2808: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 2801:
2801: store_metadata <= store_metadata_d;
Count: 4378865
Threshold: 1
Signal assignment statement on line 2802:
2802: store_data <= store_data_d;
Count: 4378865
Threshold: 1
Signal assignment statement on line 2803:
2803: rec_valid <= rec_valid_d;
Count: 4378865
Threshold: 1
Signal assignment statement on line 2805:
2805: store_metadata <= '0';
Count: 542795469
Threshold: 1
Signal assignment statement on line 2806:
2806: store_data <= '0';
Count: 542795469
Threshold: 1
Signal assignment statement on line 2807:
2807: rec_valid <= '0';
Count: 542795469
Threshold: 1
Signal assignment statement on line 2810:
2810: rec_abort <= err_frm_req;
Count: 547174334
Threshold: 1
If statement on lines 2815 to 2817:
2815: ctrl_signal_upd <= '1' when (rx_trigger = '1' or err_frm_req = '1')
2816: else
2817: '0';
Count: 20869985
Threshold: 1
Signal assignment statement on line 2815:
2815: ctrl_signal_upd <= '1' when (rx_trigger = '1' or err_frm_req = '1')
Count: 10443396
Threshold: 1
Signal assignment statement on line 2817:
2817: '0';
Count: 10426589
Threshold: 1
If statement on lines 2819 to 2821:
2819: rec_ivld_d <= rec_ivld_i when (rx_trigger = '1')
2820: else
2821: rec_ivld_q;
Count: 20983206
Threshold: 1
Signal assignment statement on line 2819:
2819: rec_ivld_d <= rec_ivld_i when (rx_trigger = '1')
Count: 10563354
Threshold: 1
Signal assignment statement on line 2821:
2821: rec_ivld_q;
Count: 10419852
Threshold: 1
If statement on lines 2828 to 2834:
2828: if (rst_n = '0') then
2829: rec_lbpf_q <= '0';
...
2833: rec_ivld_q <= rec_ivld_d;
2834: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 2829:
2829: rec_lbpf_q <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2830:
2830: rec_ivld_q <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2832:
2832: rec_lbpf_q <= rec_lbpf_d;
Count: 547174334
Threshold: 1
Signal assignment statement on line 2833:
2833: rec_ivld_q <= rec_ivld_d;
Count: 547174334
Threshold: 1
If statement on lines 2842 to 2854:
2842: if (rst_n = '0') then
2843: txtb_hw_cmd_q.lock <= '0';
...
2853: end if;
2854: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 2843:
2843: txtb_hw_cmd_q.lock <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2844:
2844: txtb_hw_cmd_q.valid <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2845:
2845: txtb_hw_cmd_q.err <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2846:
2846: txtb_hw_cmd_q.arbl <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 2847:
2847: txtb_hw_cmd_q.failed <= '0';
Count: 2422674
Threshold: 1
If statement on lines 2849 to 2853:
2849: if (ctrl_signal_upd = '1') then
2850: txtb_hw_cmd_q <= txtb_hw_cmd_d;
2851: else
2852: txtb_hw_cmd_q <= ('0', '0', '0', '0', '0');
2853: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 2850:
2850: txtb_hw_cmd_q <= txtb_hw_cmd_d;
Count: 10432415
Threshold: 1
Signal assignment statement on line 2852:
2852: txtb_hw_cmd_q <= ('0', '0', '0', '0', '0');
Count: 536741919
Threshold: 1
Signal assignment statement on line 2861:
2861: rx_store_base_id <= rx_store_base_id_i and rx_trigger;
Count: 20859473
Threshold: 1
Signal assignment statement on line 2862:
2862: rx_store_ext_id <= rx_store_ext_id_i and rx_trigger;
Count: 20822405
Threshold: 1
Signal assignment statement on line 2863:
2863: rx_store_ide <= rx_store_ide_i and rx_trigger;
Count: 20911620
Threshold: 1
Signal assignment statement on line 2864:
2864: rx_store_rtr <= rx_store_rtr_i and rx_trigger;
Count: 20945974
Threshold: 1
Signal assignment statement on line 2865:
2865: rx_store_edl <= rx_store_edl_i and rx_trigger;
Count: 20907632
Threshold: 1
Signal assignment statement on line 2866:
2866: rx_store_dlc <= rx_store_dlc_i and rx_trigger;
Count: 20855349
Threshold: 1
Signal assignment statement on line 2867:
2867: rx_store_esi <= rx_store_esi_i and rx_trigger;
Count: 20861500
Threshold: 1
Signal assignment statement on line 2868:
2868: rx_store_brs <= rx_store_brs_i and rx_trigger;
Count: 20861596
Threshold: 1
Signal assignment statement on line 2869:
2869: rx_store_stuff_count <= rx_store_stuff_count_i and rx_trigger;
Count: 20831134
Threshold: 1
Signal assignment statement on line 2875:
2875: tx_load_base_id <= tx_load_base_id_i and rx_trigger;
Count: 20856616
Threshold: 1
Signal assignment statement on line 2876:
2876: tx_load_ext_id <= tx_load_ext_id_i and rx_trigger;
Count: 20849669
Threshold: 1
Signal assignment statement on line 2877:
2877: tx_load_dlc <= tx_load_dlc_i and rx_trigger;
Count: 20928470
Threshold: 1
Signal assignment statement on line 2878:
2878: tx_load_data_word <= tx_load_data_word_i and rx_trigger;
Count: 20847561
Threshold: 1
Signal assignment statement on line 2879:
2879: tx_load_stuff_count <= tx_load_stuff_count_i and rx_trigger;
Count: 20846306
Threshold: 1
Signal assignment statement on line 2880:
2880: tx_load_crc <= tx_load_crc_i and rx_trigger;
Count: 20863445
Threshold: 1
If statement on lines 2885 to 2887:
2885: tx_shift_ena <= '1' when (tx_shift_ena_i = '1' and is_transmitter = '1')
2886: else
2887: '0';
Count: 294405
Threshold: 1
Signal assignment statement on line 2885:
2885: tx_shift_ena <= '1' when (tx_shift_ena_i = '1' and is_transmitter = '1')
Count: 57392
Threshold: 1
Signal assignment statement on line 2887:
2887: '0';
Count: 237013
Threshold: 1
Signal assignment statement on line 2892:
2892: form_err <= form_err_i and rx_trigger;
Count: 20911786
Threshold: 1
Signal assignment statement on line 2893:
2893: ack_err <= ack_err_i and rx_trigger;
Count: 20813610
Threshold: 1
Signal assignment statement on line 2894:
2894: crc_err <= crc_err_i and rx_trigger;
Count: 20806950
Threshold: 1
Signal assignment statement on line 2895:
2895: bit_err_arb <= bit_err_arb_i and rx_trigger;
Count: 20942885
Threshold: 1
Signal assignment statement on line 2903:
2903: decrement_rec <= decrement_rec_i;
Count: 33106
Threshold: 1
If statement on lines 2908 to 2911:
2908: switch_to_ssp <= '1' when (sp_control_switch_data = '1' and is_transmitter = '1' and
2909: mr_ssp_cfg_ssp_src /= SSP_SRC_NO_SSP)
2910: else
2911: '0';
Count: 87723
Threshold: 1
Signal assignment statement on line 2908:
2908: switch_to_ssp <= '1' when (sp_control_switch_data = '1' and is_transmitter = '1' and
Count: 2174
Threshold: 1
Signal assignment statement on line 2911:
2911: '0';
Count: 85549
Threshold: 1
If statement on lines 2913 to 2919:
2913: sp_control_d <= NOMINAL_SAMPLE when (sp_control_switch_nominal = '1')
2914: else
...
2918: else
2919: sp_control_q_i;
Count: 142468
Threshold: 1
Signal assignment statement on line 2913:
2913: sp_control_d <= NOMINAL_SAMPLE when (sp_control_switch_nominal = '1')
Count: 46644
Threshold: 1
Signal assignment statement on line 2915:
2915: SECONDARY_SAMPLE when (switch_to_ssp = '1')
Count: 6499
Threshold: 1
Signal assignment statement on line 2917:
2917: DATA_SAMPLE when (sp_control_switch_data = '1')
Count: 37924
Threshold: 1
Signal assignment statement on line 2919:
2919: sp_control_q_i;
Count: 51401
Threshold: 1
If statement on lines 2921 to 2923:
2921: sp_control_ce <= '1' when (sp_control_switch_nominal = '1') else
2922: '1' when (sp_control_switch_data = '1') else
2923: '0';
Count: 96421
Threshold: 1
Signal assignment statement on line 2921:
2921: sp_control_ce <= '1' when (sp_control_switch_nominal = '1') else
Count: 26572
Threshold: 1
Signal assignment statement on line 2922:
2922: '1' when (sp_control_switch_data = '1') else
Count: 20049
Threshold: 1
Signal assignment statement on line 2923:
2923: '0';
Count: 49800
Threshold: 1
If statement on lines 2927 to 2933:
2927: if (rst_n = '0') then
2928: sp_control_q_i <= NOMINAL_SAMPLE;
...
2932: end if;
2933: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 2928:
2928: sp_control_q_i <= NOMINAL_SAMPLE;
Count: 2422674
Threshold: 1
If statement on lines 2930 to 2932:
2930: if (sp_control_ce = '1') then
2931: sp_control_q_i <= sp_control_d;
2932: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 2931:
2931: sp_control_q_i <= sp_control_d;
Count: 40098
Threshold: 1
If statement on lines 2936 to 2937:
2936: sp_control <= sp_control_d when (br_shifted_i = '1') else
2937: sp_control_q_i;
Count: 195016
Threshold: 1
Signal assignment statement on line 2936:
2936: sp_control <= sp_control_d when (br_shifted_i = '1') else
Count: 135491
Threshold: 1
Signal assignment statement on line 2937:
2937: sp_control_q_i;
Count: 59525
Threshold: 1
If statement on lines 2944 to 2946:
2944: act_err_ovr_flag <= '1' when (curr_state = s_pc_act_err_flag) else
2945: '1' when (curr_state = s_pc_ovr_flag) else
2946: '0';
Count: 839377
Threshold: 1
Signal assignment statement on line 2944:
2944: act_err_ovr_flag <= '1' when (curr_state = s_pc_act_err_flag) else
Count: 19278
Threshold: 1
Signal assignment statement on line 2945:
2945: '1' when (curr_state = s_pc_ovr_flag) else
Count: 561
Threshold: 1
Signal assignment statement on line 2946:
2946: '0';
Count: 819538
Threshold: 1
If statement on lines 2950 to 2956:
2950: if (rst_n = '0') then
2951: first_err_delim_q <= '0';
...
2955: end if;
2956: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 2951:
2951: first_err_delim_q <= '0';
Count: 2422674
Threshold: 1
If statement on lines 2953 to 2955:
2953: if (rx_trigger = '1') then
2954: first_err_delim_q <= first_err_delim_d;
2955: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 2954:
2954: first_err_delim_q <= first_err_delim_d;
Count: 10400889
Threshold: 1
If statement on lines 2963 to 2965:
2963: primary_err <= '1' when (primary_err_i = '1' and rx_trigger = '1')
2964: else
2965: '0';
Count: 20828081
Threshold: 1
Signal assignment statement on line 2963:
2963: primary_err <= '1' when (primary_err_i = '1' and rx_trigger = '1')
Count: 22749
Threshold: 1
Signal assignment statement on line 2965:
2965: '0';
Count: 20805332
Threshold: 1
If statement on lines 2967 to 2969:
2967: err_delim_late <= '1' when (err_delim_late_i = '1' and rx_trigger = '1')
2968: else
2969: '0';
Count: 20805478
Threshold: 1
Signal assignment statement on line 2967:
2967: err_delim_late <= '1' when (err_delim_late_i = '1' and rx_trigger = '1')
Count: 390
Threshold: 1
Signal assignment statement on line 2969:
2969: '0';
Count: 20805088
Threshold: 1
If statement on lines 2971 to 2973:
2971: set_err_active <= '1' when (set_err_active_i = '1' and rx_trigger = '1')
2972: else
2973: '0';
Count: 20812309
Threshold: 1
Signal assignment statement on line 2971:
2971: set_err_active <= '1' when (set_err_active_i = '1' and rx_trigger = '1')
Count: 6637
Threshold: 1
Signal assignment statement on line 2973:
2973: '0';
Count: 20805672
Threshold: 1
If statement on lines 2975 to 2977:
2975: rx_clear <= '1' when (rx_clear_i = '1' and rx_trigger = '1')
2976: else
2977: '0';
Count: 20927025
Threshold: 1
Signal assignment statement on line 2975:
2975: rx_clear <= '1' when (rx_clear_i = '1' and rx_trigger = '1')
Count: 70965
Threshold: 1
Signal assignment statement on line 2977:
2977: '0';
Count: 20856060
Threshold: 1
If statement on lines 2985 to 2987:
2985: bit_err_enable <= '0' when (bit_err_disable = '1') else
2986: '0' when (bit_err_disable_receiver = '1' and is_receiver = '1') else
2987: '1';
Count: 260101
Threshold: 1
Signal assignment statement on line 2985:
2985: bit_err_enable <= '0' when (bit_err_disable = '1') else
Count: 139474
Threshold: 1
Signal assignment statement on line 2986:
2986: '0' when (bit_err_disable_receiver = '1' and is_receiver = '1') else
Count: 28663
Threshold: 1
Signal assignment statement on line 2987:
2987: '1';
Count: 91964
Threshold: 1
If statement on lines 2996 to 3000:
2996: retr_ctr_add_i <= '0' when (retr_ctr_clear_i = '1' or mr_settings_rtrle = '0'
2997: or is_receiver = '1' or retr_ctr_add_block = '1') else
2998: '1' when (arbitration_lost_i = '1' and rx_trigger = '1') else
2999: '1' when (err_frm_req = '1') else
3000: '0';
Count: 20967795
Threshold: 1
Signal assignment statement on line 2996:
2996: retr_ctr_add_i <= '0' when (retr_ctr_clear_i = '1' or mr_settings_rtrle = '0'
Count: 15293049
Threshold: 1
Signal assignment statement on line 2998:
2998: '1' when (arbitration_lost_i = '1' and rx_trigger = '1') else
Count: 307
Threshold: 1
Signal assignment statement on line 2999:
2999: '1' when (err_frm_req = '1') else
Count: 11460
Threshold: 1
Signal assignment statement on line 3000:
3000: '0';
Count: 5662979
Threshold: 1
If statement on lines 3007 to 3009:
3007: retr_ctr_clear_i <= '1' when (txtb_hw_cmd_d.valid = '1' and rx_trigger = '1') else
3008: '1' when (txtb_hw_cmd_d.failed = '1') else
3009: '0';
Count: 20835774
Threshold: 1
Signal assignment statement on line 3007:
3007: retr_ctr_clear_i <= '1' when (txtb_hw_cmd_d.valid = '1' and rx_trigger = '1') else
Count: 11115
Threshold: 1
Signal assignment statement on line 3008:
3008: '1' when (txtb_hw_cmd_d.failed = '1') else
Count: 15634
Threshold: 1
Signal assignment statement on line 3009:
3009: '0';
Count: 20809025
Threshold: 1
If statement on lines 3018 to 3026:
3018: if (rst_n = '0') then
3019: retr_ctr_add_block <= '0';
...
3025: end if;
3026: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3019:
3019: retr_ctr_add_block <= '0';
Count: 2422674
Threshold: 1
If statement on lines 3021 to 3025:
3021: if (retr_ctr_add_i = '1') then
3022: retr_ctr_add_block <= '1';
3023: elsif (retr_ctr_add_block_clr = '1') then
3024: retr_ctr_add_block <= '0';
3025: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 3022:
3022: retr_ctr_add_block <= '1';
Count: 1122
Threshold: 1
Signal assignment statement on line 3024:
3024: retr_ctr_add_block <= '0';
Count: 10958401
Threshold: 1
If statement on lines 3031 to 3033:
3031: sof_pulse <= '1' when (sof_pulse_i = '1' and rx_trigger = '1')
3032: else
3033: '0';
Count: 20886431
Threshold: 1
Signal assignment statement on line 3031:
3031: sof_pulse <= '1' when (sof_pulse_i = '1' and rx_trigger = '1')
Count: 81099
Threshold: 1
Signal assignment statement on line 3033:
3033: '0';
Count: 20805332
Threshold: 1
If statement on lines 3038 to 3040:
3038: compl_ctr_ena <= '1' when (compl_ctr_ena_i = '1' and rx_trigger = '1')
3039: else
3040: '0';
Count: 20878642
Threshold: 1
Signal assignment statement on line 3038:
3038: compl_ctr_ena <= '1' when (compl_ctr_ena_i = '1' and rx_trigger = '1')
Count: 4505707
Threshold: 1
Signal assignment statement on line 3040:
3040: '0';
Count: 16372935
Threshold: 1
If statement on lines 3045 to 3047:
3045: set_transmitter <= '1' when (set_transmitter_i = '1' and rx_trigger = '1')
3046: else
3047: '0';
Count: 20866218
Threshold: 1
Signal assignment statement on line 3045:
3045: set_transmitter <= '1' when (set_transmitter_i = '1' and rx_trigger = '1')
Count: 40515
Threshold: 1
Signal assignment statement on line 3047:
3047: '0';
Count: 20825703
Threshold: 1
If statement on lines 3055 to 3057:
3055: set_receiver <= '1' when (set_receiver_i = '1')
3056: else
3057: '0';
Count: 64102
Threshold: 1
Signal assignment statement on line 3055:
3055: set_receiver <= '1' when (set_receiver_i = '1')
Count: 30450
Threshold: 1
Signal assignment statement on line 3057:
3057: '0';
Count: 33652
Threshold: 1
If statement on lines 3064 to 3066:
3064: set_idle <= '1' when (set_idle_i = '1' and (rx_trigger = '1' or err_frm_req = '1'))
3065: else
3066: '0';
Count: 20971640
Threshold: 1
Signal assignment statement on line 3064:
3064: set_idle <= '1' when (set_idle_i = '1' and (rx_trigger = '1' or err_frm_req = '1'))
Count: 96990
Threshold: 1
Signal assignment statement on line 3066:
3066: '0';
Count: 20874650
Threshold: 1
If statement on lines 3077 to 3080:
3077: crc_calc_from_rx <= '1' when (crc_spec_enable_i = '1') else
3078: '1' when (is_arbitration_i = '1') else
3079: '1' when (is_receiver = '1') else
3080: '0';
Count: 342802
Threshold: 1
Signal assignment statement on line 3077:
3077: crc_calc_from_rx <= '1' when (crc_spec_enable_i = '1') else
Count: 139834
Threshold: 1
Signal assignment statement on line 3078:
3078: '1' when (is_arbitration_i = '1') else
Count: 56542
Threshold: 1
Signal assignment statement on line 3079:
3079: '1' when (is_receiver = '1') else
Count: 58123
Threshold: 1
Signal assignment statement on line 3080:
3080: '0';
Count: 88303
Threshold: 1
If statement on lines 3082 to 3084:
3082: load_init_vect <= '1' when (load_init_vect_i = '1' and rx_trigger = '1')
3083: else
3084: '0';
Count: 20817415
Threshold: 1
Signal assignment statement on line 3082:
3082: load_init_vect <= '1' when (load_init_vect_i = '1' and rx_trigger = '1')
Count: 113844
Threshold: 1
Signal assignment statement on line 3084:
3084: '0';
Count: 20703571
Threshold: 1
If statement on lines 3091 to 3101:
3091: if (rst_n = '0') then
3092: stuff_enable <= '0';
...
3100: end if;
3101: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3092:
3092: stuff_enable <= '0';
Count: 2422674
Threshold: 1
If statement on lines 3094 to 3100:
3094: if (ctrl_signal_upd = '1') then
3095: if (stuff_enable_set = '1') then
...
3099: end if;
3100: end if;
Count: 547174334
Threshold: 1
If statement on lines 3095 to 3099:
3095: if (stuff_enable_set = '1') then
3096: stuff_enable <= '1';
3097: elsif (stuff_enable_clear = '1') then
3098: stuff_enable <= '0';
3099: end if;
Count: 10432415
Threshold: 1
Signal assignment statement on line 3096:
3096: stuff_enable <= '1';
Count: 25501
Threshold: 1
Signal assignment statement on line 3098:
3098: stuff_enable <= '0';
Count: 61940
Threshold: 1
If statement on lines 3109 to 3119:
3109: if (rst_n = '0') then
3110: destuff_enable <= '0';
...
3118: end if;
3119: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3110:
3110: destuff_enable <= '0';
Count: 2422674
Threshold: 1
If statement on lines 3112 to 3118:
3112: if (ctrl_signal_upd = '1') then
3113: if (destuff_enable_set = '1') then
...
3117: end if;
3118: end if;
Count: 547174334
Threshold: 1
If statement on lines 3113 to 3117:
3113: if (destuff_enable_set = '1') then
3114: destuff_enable <= '1';
3115: elsif (destuff_enable_clear = '1') then
3116: destuff_enable <= '0';
3117: end if;
Count: 10432415
Threshold: 1
Signal assignment statement on line 3114:
3114: destuff_enable <= '1';
Count: 55951
Threshold: 1
Signal assignment statement on line 3116:
3116: destuff_enable <= '0';
Count: 61315
Threshold: 1
If statement on lines 3126 to 3132:
3126: sync_control_d <= NO_SYNC when ((sp_control_switch_data = '1' and is_transmitter = '1') or
3127: sp_control_q_i = SECONDARY_SAMPLE or
...
3131: else
3132: RE_SYNC;
Count: 410606
Threshold: 1
Signal assignment statement on line 3126:
3126: sync_control_d <= NO_SYNC when ((sp_control_switch_data = '1' and is_transmitter = '1') or
Count: 23088
Threshold: 1
Signal assignment statement on line 3130:
3130: HARD_SYNC when (perform_hsync = '1')
Count: 182173
Threshold: 1
Signal assignment statement on line 3132:
3132: RE_SYNC;
Count: 205345
Threshold: 1
If statement on lines 3136 to 3140:
3136: if (rst_n = '0') then
3137: sync_control_q <= HARD_SYNC;
3138: elsif (rising_edge(clk_sys)) then
3139: sync_control_q <= sync_control_d;
3140: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3137:
3137: sync_control_q <= HARD_SYNC;
Count: 2422674
Threshold: 1
Signal assignment statement on line 3139:
3139: sync_control_q <= sync_control_d;
Count: 547174334
Threshold: 1
If statement on lines 3148 to 3154:
3148: if (rst_n = '0') then
3149: txtb_ptr_q <= 0;
...
3153: end if;
3154: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3149:
3149: txtb_ptr_q <= 0;
Count: 2422674
Threshold: 1
If statement on lines 3151 to 3153:
3151: if (txtb_clk_en_d = '1') then
3152: txtb_ptr_q <= txtb_ptr_d;
3153: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 3152:
3152: txtb_ptr_q <= txtb_ptr_d;
Count: 80871
Threshold: 1
If statement on lines 3159 to 3161:
3159: txtb_clk_en_d <= '1' when (txtb_ptr_q /= txtb_ptr_d and txtb_gate_mem_read = '0')
3160: else
3161: '0';
Count: 219465
Threshold: 1
Signal assignment statement on line 3159:
3159: txtb_clk_en_d <= '1' when (txtb_ptr_q /= txtb_ptr_d and txtb_gate_mem_read = '0')
Count: 97874
Threshold: 1
Signal assignment statement on line 3161:
3161: '0';
Count: 121591
Threshold: 1
If statement on lines 3168 to 3172:
3168: if (rst_n = '0') then
3169: txtb_clk_en_q <= '0';
3170: elsif (rising_edge(clk_sys)) then
3171: txtb_clk_en_q <= txtb_clk_en_d;
3172: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3169:
3169: txtb_clk_en_q <= '0';
Count: 2422674
Threshold: 1
Signal assignment statement on line 3171:
3171: txtb_clk_en_q <= txtb_clk_en_d;
Count: 547174334
Threshold: 1
If statement on lines 3180 to 3186:
3180: if (rst_n = '0') then
3181: tx_frame_no_sof_q <= '0';
...
3185: end if;
3186: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3181:
3181: tx_frame_no_sof_q <= '0';
Count: 2422674
Threshold: 1
If statement on lines 3183 to 3185:
3183: if (rx_trigger = '1') then
3184: tx_frame_no_sof_q <= tx_frame_no_sof_d;
3185: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 3184:
3184: tx_frame_no_sof_q <= tx_frame_no_sof_d;
Count: 10400889
Threshold: 1
If statement on lines 3194 to 3200:
3194: if (rst_n = '0') then
3195: rx_data_nbs_prev <= RECESSIVE;
...
3199: end if;
3200: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3195:
3195: rx_data_nbs_prev <= RECESSIVE;
Count: 2422674
Threshold: 1
If statement on lines 3197 to 3199:
3197: if (rx_trigger = '1') then
3198: rx_data_nbs_prev <= rx_data_nbs;
3199: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 3198:
3198: rx_data_nbs_prev <= rx_data_nbs;
Count: 10400889
Threshold: 1
If statement on lines 3208 to 3216:
3208: if (rst_n = '0') then
3209: ack_err_flag <= '0';
...
3215: end if;
3216: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3209:
3209: ack_err_flag <= '0';
Count: 2422674
Threshold: 1
If statement on lines 3211 to 3215:
3211: if (ack_err_i = '1' and rx_trigger = '1') then
3212: ack_err_flag <= '1';
3213: elsif (ack_err_flag_clr = '1') then
3214: ack_err_flag <= '0';
3215: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 3212:
3212: ack_err_flag <= '1';
Count: 1326
Threshold: 1
Signal assignment statement on line 3214:
3214: ack_err_flag <= '0';
Count: 2281475
Threshold: 1
If statement on lines 3224 to 3232:
3224: if (rst_n = '0') then
3225: mr_status_pexs <= '0';
...
3231: end if;
3232: end if;
Count: 1096781321
Threshold: 1
Signal assignment statement on line 3225:
3225: mr_status_pexs <= '0';
Count: 2422674
Threshold: 1
If statement on lines 3227 to 3231:
3227: if (pexs_set = '1') then
3228: mr_status_pexs <= '1';
3229: elsif (mr_command_cpexs = '1') then
3230: mr_status_pexs <= '0';
3231: end if;
Count: 547174334
Threshold: 1
Signal assignment statement on line 3228:
3228: mr_status_pexs <= '1';
Count: 6010
Threshold: 1
Signal assignment statement on line 3230:
3230: mr_status_pexs <= '0';
Count: 60
Threshold: 1
Signal assignment statement on line 3238:
3238: crc_src <= crc_src_i;
Count: 99355
Threshold: 1
Signal assignment statement on line 3239:
3239: txtb_hw_cmd <= txtb_hw_cmd_q;
Count: 105184
Threshold: 1
Signal assignment statement on line 3240:
3240: tran_valid <= txtb_hw_cmd_q.valid;
Count: 25432
Threshold: 1
Signal assignment statement on line 3241:
3241: sync_control <= sync_control_q;
Count: 201865
Threshold: 1
Signal assignment statement on line 3242:
3242: txtb_ptr <= txtb_ptr_q;
Count: 82472
Threshold: 1
Signal assignment statement on line 3243:
3243: br_shifted <= br_shifted_i;
Count: 96398
Threshold: 1
Signal assignment statement on line 3244:
3244: sp_control_q <= sp_control_q_i;
Count: 43300
Threshold: 1
Signal assignment statement on line 3245:
3245: crc_spec_enable <= crc_spec_enable_i;
Count: 230939
Threshold: 1
Signal assignment statement on line 3246:
3246: retr_ctr_clear <= retr_ctr_clear_i;
Count: 44758
Threshold: 1
Signal assignment statement on line 3247:
3247: arbitration_lost <= arbitration_lost_i;
Count: 5552
Threshold: 1
Signal assignment statement on line 3248:
3248: retr_ctr_add <= retr_ctr_add_i;
Count: 24748
Threshold: 1
Signal assignment statement on line 3249:
3249: tx_frame_no_sof <= tx_frame_no_sof_q;
Count: 3908
Threshold: 1
Signal assignment statement on line 3250:
3250: txtb_clk_en <= txtb_clk_en_q;
Count: 164944
Threshold: 1
Signal assignment statement on line 3251:
3251: pc_dbg.is_arbitration <= is_arbitration_i;
Count: 115022
Threshold: 1
Signal assignment statement on line 3252:
3252: rec_lbpf <= rec_lbpf_q;
Count: 3562
Threshold: 1
Signal assignment statement on line 3253:
3253: rec_ivld <= rec_ivld_q;
Count: 105553
Threshold: 1