NVC code coverage report

Signal assignment statement on line 877:

877:    pc_rx_data_nbs <= bds_data_out; 
Count: 2799074
Threshold: 1

---

Signal assignment statement on line 878:

878:    bst_data_in <= pc_tx_data_nbs; 
Count: 1296894
Threshold: 1

---

Signal assignment statement on line 885:

885:    crc_data_tx_nbs <= pc_tx_data_nbs; 
Count: 1296894
Threshold: 1

---

Signal assignment statement on line 886:

886:    crc_data_rx_nbs <= bds_data_out; 
Count: 2799074
Threshold: 1

---

Signal assignment statement on line 893:

893:    crc_data_tx_wbs <= bst_data_out; 
Count: 1276992
Threshold: 1

---

Signal assignment statement on line 895:

895:    lpb_dominant <= rx_data_wbs and bst_data_out; 
Count: 4089498
Threshold: 1

---

If statement on lines 905 to 907:

905:    bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else 
906:                   lpb_dominant when (mr_mode_bmm = '1') else 
907:                    rx_data_wbs; 
Count: 6936694
Threshold: 1

---

Signal assignment statement on line 905:

905:    bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else 
Count: 334229
Threshold: 1

---

Signal assignment statement on line 906:

906:                   lpb_dominant when (mr_mode_bmm = '1') else 
Count: 1469
Threshold: 1

---

Signal assignment statement on line 907:

907:                    rx_data_wbs; 
Count: 6600996
Threshold: 1

---

If statement on lines 913 to 915:

913:    tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else 
914:                     RECESSIVE when (mr_mode_bmm = '1') else 
915:                     bst_data_out; 
Count: 1291567
Threshold: 1

---

Signal assignment statement on line 913:

913:    tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else 
Count: 8081
Threshold: 1

---

Signal assignment statement on line 914:

914:                     RECESSIVE when (mr_mode_bmm = '1') else 
Count: 50
Threshold: 1

---

Signal assignment statement on line 915:

915:                     bst_data_out; 
Count: 1283436
Threshold: 1

---

If statement on lines 921 to 922:

921:    no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else 
922:                     '0'; 
Count: 1276962
Threshold: 1

---

Signal assignment statement on line 921:

921:    no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else 
Count: 636881
Threshold: 1

---

Signal assignment statement on line 922:

922:                     '0'; 
Count: 640081
Threshold: 1

---

Signal assignment statement on line 927:

927:    cc_stat.is_err_active   <= is_err_active; 
Count: 18442
Threshold: 1

---

Signal assignment statement on line 928:

928:    cc_stat.is_err_passive  <= is_err_passive; 
Count: 4744
Threshold: 1

---

Signal assignment statement on line 929:

929:    cc_stat.is_bus_off      <= is_bus_off_i; 
Count: 18066
Threshold: 1

---

Signal assignment statement on line 930:

930:    cc_stat.is_transmitter  <= is_transmitter; 
Count: 44322
Threshold: 1

---

Signal assignment statement on line 931:

931:    cc_stat.is_receiver     <= is_receiver; 
Count: 64941
Threshold: 1

---

Signal assignment statement on line 932:

932:    cc_stat.is_idle         <= is_idle; 
Count: 115398
Threshold: 1

---

Signal assignment statement on line 933:

933:    cc_stat.tx_err_ctr      <= tx_err_ctr; 
Count: 33872
Threshold: 1

---

Signal assignment statement on line 934:

934:    cc_stat.rx_err_ctr      <= rx_err_ctr; 
Count: 27275
Threshold: 1

---

Signal assignment statement on line 935:

935:    cc_stat.status_pexs     <= mr_status_pexs; 
Count: 3352
Threshold: 1

---

Signal assignment statement on line 936:

936:    cc_stat.norm_err_ctr    <= norm_err_ctr; 
Count: 27615
Threshold: 1

---

Signal assignment statement on line 937:

937:    cc_stat.data_err_ctr    <= data_err_ctr; 
Count: 14578
Threshold: 1

---

Signal assignment statement on line 938:

938:    cc_stat.err_type        <= err_capt_err_type; 
Count: 7061
Threshold: 1

---

Signal assignment statement on line 939:

939:    cc_stat.err_erp         <= err_capt_err_erp; 
Count: 3792
Threshold: 1

---

Signal assignment statement on line 940:

940:    cc_stat.err_pos         <= err_capt_err_pos; 
Count: 12035
Threshold: 1

---

Signal assignment statement on line 941:

941:    cc_stat.retr_ctr        <= retr_ctr; 
Count: 4527
Threshold: 1

---

Signal assignment statement on line 942:

942:    cc_stat.alc_bit         <= alc_alc_bit; 
Count: 3825
Threshold: 1

---

Signal assignment statement on line 943:

943:    cc_stat.alc_id_field    <= alc_alc_id_field; 
Count: 3473
Threshold: 1

---

Signal assignment statement on line 944:

944:    cc_stat.rx_frame_ctr    <= rx_frame_ctr; 
Count: 15394
Threshold: 1

---

Signal assignment statement on line 945:

945:    cc_stat.tx_frame_ctr    <= tx_frame_ctr; 
Count: 8155
Threshold: 1

---

Signal assignment statement on line 946:

946:    cc_stat.bst_ctr         <= bst_ctr; 
Count: 298951
Threshold: 1

---

Signal assignment statement on line 947:

947:    cc_stat.dst_ctr         <= dst_ctr; 
Count: 999446
Threshold: 1

---

Signal assignment statement on line 948:

948:    cc_stat.status_ewl      <= mr_status_ewl; 
Count: 4761
Threshold: 1

---

Signal assignment statement on line 953:

953:    rec_valid               <= rec_valid_i; 
Count: 33500
Threshold: 1

---

Signal assignment statement on line 954:

954:    arbitration_lost        <= arbitration_lost_i; 
Count: 5552
Threshold: 1

---

Signal assignment statement on line 955:

955:    tran_valid              <= tran_valid_i; 
Count: 25432
Threshold: 1

---

Signal assignment statement on line 956:

956:    err_detected            <= err_detected_i; 
Count: 255608
Threshold: 1

---

Signal assignment statement on line 957:

957:    tx_data_wbs             <= tx_data_wbs_i; 
Count: 1276962
Threshold: 1

---

Signal assignment statement on line 958:

958:    sp_control              <= sp_control_i; 
Count: 58520
Threshold: 1

---

Signal assignment statement on line 961:

961:    pc_rx_trigger           <= pc_rx_trigger_i; 
Count: 20805332
Threshold: 1

"if" / "when" / "else" condition on line 905:

905:    bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else 

	Evaluated to	Count	Threshold
Bin	True	334229	1
Bin	False	6602465	1

---

"if" / "when" / "else" condition on line 906:

906:                   lpb_dominant when (mr_mode_bmm = '1') else 

	Evaluated to	Count	Threshold
Bin	True	1469	1
Bin	False	6600996	1

---

"if" / "when" / "else" condition on line 913:

913:    tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else 

	Evaluated to	Count	Threshold
Bin	True	8081	1
Bin	False	1283486	1

---

"if" / "when" / "else" condition on line 914:

914:                     RECESSIVE when (mr_mode_bmm = '1') else 

	Evaluated to	Count	Threshold
Bin	True	50	1
Bin	False	1283436	1

---

"if" / "when" / "else" condition on line 921:

921:    no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else 

	Evaluated to	Count	Threshold
Bin	True	636881	1
Bin	False	640081	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SCAN_MODE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_ACF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_STM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_FDE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_TSTM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_SAM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_NISOFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_RTRTH

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_RTRLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_ILBP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PEX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_ERCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_RXFCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_TXFCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_CPEXS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SSP_CFG_SSP_SRC

	Element	From	To	Count	Threshold	Excluded due to
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_EWL_EW_LIMIT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_ERP_ERP_LIMIT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_CTPV

	Element	From	To	Count	Threshold	Excluded due to
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_PTX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_PRX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_ENORM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_EFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_WORD

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TRAN_DLC

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TRAN_IS_RTR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_IDENT_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_FRAME_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_BRS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_IDENTIFIER

	Element	From	To	Count	Threshold	Excluded due to
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TRAN_FRAME_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_FRAME_PARITY_ERROR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_CHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RX_TRIGGERS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RX_DATA_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 BIT_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SYNC_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

 CC_STAT

	Element	From	To	Count	Threshold
Bin	IS_ERR_ACTIVE	0	1	8426	1
Bin	IS_ERR_ACTIVE	1	0	8415	1
Bin	IS_ERR_PASSIVE	0	1	771	1
Bin	IS_ERR_PASSIVE	1	0	2372	1
Bin	IS_BUS_OFF	0	1	8227	1
Bin	IS_BUS_OFF	1	0	8238	1
Bin	IS_TRANSMITTER	0	1	20560	1
Bin	IS_TRANSMITTER	1	0	22161	1
Bin	IS_RECEIVER	0	1	30873	1
Bin	IS_RECEIVER	1	0	32467	1
Bin	IS_IDLE	0	1	56100	1
Bin	IS_IDLE	1	0	57697	1
Bin	TX_ERR_CTR(8)	0	1	249	1
Bin	TX_ERR_CTR(8)	1	0	1850	1
Bin	TX_ERR_CTR(7)	0	1	517	1
Bin	TX_ERR_CTR(7)	1	0	2118	1
Bin	TX_ERR_CTR(6)	0	1	501	1
Bin	TX_ERR_CTR(6)	1	0	2102	1
Bin	TX_ERR_CTR(5)	0	1	805	1
Bin	TX_ERR_CTR(5)	1	0	2406	1
Bin	TX_ERR_CTR(4)	0	1	1933	1
Bin	TX_ERR_CTR(4)	1	0	3534	1
Bin	TX_ERR_CTR(3)	0	1	12743	1
Bin	TX_ERR_CTR(3)	1	0	14344	1
Bin	TX_ERR_CTR(2)	0	1	2955	1
Bin	TX_ERR_CTR(2)	1	0	4556	1
Bin	TX_ERR_CTR(1)	0	1	3324	1
Bin	TX_ERR_CTR(1)	1	0	4925	1
Bin	TX_ERR_CTR(0)	0	1	3524	1
Bin	TX_ERR_CTR(0)	1	0	5125	1
Bin	RX_ERR_CTR(8)	0	1	130	1
Bin	RX_ERR_CTR(8)	1	0	1731	1
Bin	RX_ERR_CTR(7)	0	1	350	1
Bin	RX_ERR_CTR(7)	1	0	1951	1
Bin	RX_ERR_CTR(6)	0	1	255	1
Bin	RX_ERR_CTR(6)	1	0	1854	1
Bin	RX_ERR_CTR(5)	0	1	363	1
Bin	RX_ERR_CTR(5)	1	0	1963	1
Bin	RX_ERR_CTR(4)	0	1	497	1
Bin	RX_ERR_CTR(4)	1	0	2098	1
Bin	RX_ERR_CTR(3)	0	1	685	1
Bin	RX_ERR_CTR(3)	1	0	2285	1
Bin	RX_ERR_CTR(2)	0	1	617	1
Bin	RX_ERR_CTR(2)	1	0	2218	1
Bin	RX_ERR_CTR(1)	0	1	1191	1
Bin	RX_ERR_CTR(1)	1	0	2792	1
Bin	RX_ERR_CTR(0)	0	1	11216	1
Bin	RX_ERR_CTR(0)	1	0	12809	1
Bin	STATUS_PEXS	0	1	75	1
Bin	STATUS_PEXS	1	0	1676	1
Bin	NORM_ERR_CTR(15)	0	1	69	1
Bin	NORM_ERR_CTR(15)	1	0	1667	1
Bin	NORM_ERR_CTR(14)	0	1	67	1
Bin	NORM_ERR_CTR(14)	1	0	1668	1
Bin	NORM_ERR_CTR(13)	0	1	64	1
Bin	NORM_ERR_CTR(13)	1	0	1661	1
Bin	NORM_ERR_CTR(12)	0	1	62	1
Bin	NORM_ERR_CTR(12)	1	0	1659	1
Bin	NORM_ERR_CTR(11)	0	1	64	1
Bin	NORM_ERR_CTR(11)	1	0	1664	1
Bin	NORM_ERR_CTR(10)	0	1	69	1
Bin	NORM_ERR_CTR(10)	1	0	1668	1
Bin	NORM_ERR_CTR(9)	0	1	63	1
Bin	NORM_ERR_CTR(9)	1	0	1662	1
Bin	NORM_ERR_CTR(8)	0	1	71	1
Bin	NORM_ERR_CTR(8)	1	0	1671	1
Bin	NORM_ERR_CTR(7)	0	1	75	1
Bin	NORM_ERR_CTR(7)	1	0	1673	1
Bin	NORM_ERR_CTR(6)	0	1	97	1
Bin	NORM_ERR_CTR(6)	1	0	1696	1
Bin	NORM_ERR_CTR(5)	0	1	155	1
Bin	NORM_ERR_CTR(5)	1	0	1752	1
Bin	NORM_ERR_CTR(4)	0	1	276	1
Bin	NORM_ERR_CTR(4)	1	0	1876	1
Bin	NORM_ERR_CTR(3)	0	1	608	1
Bin	NORM_ERR_CTR(3)	1	0	2205	1
Bin	NORM_ERR_CTR(2)	0	1	1361	1
Bin	NORM_ERR_CTR(2)	1	0	2958	1
Bin	NORM_ERR_CTR(1)	0	1	3082	1
Bin	NORM_ERR_CTR(1)	1	0	4678	1
Bin	NORM_ERR_CTR(0)	0	1	11727	1
Bin	NORM_ERR_CTR(0)	1	0	13323	1
Bin	DATA_ERR_CTR(15)	0	1	63	1
Bin	DATA_ERR_CTR(15)	1	0	1661	1
Bin	DATA_ERR_CTR(14)	0	1	68	1
Bin	DATA_ERR_CTR(14)	1	0	1667	1
Bin	DATA_ERR_CTR(13)	0	1	67	1
Bin	DATA_ERR_CTR(13)	1	0	1665	1
Bin	DATA_ERR_CTR(12)	0	1	65	1
Bin	DATA_ERR_CTR(12)	1	0	1665	1
Bin	DATA_ERR_CTR(11)	0	1	61	1
Bin	DATA_ERR_CTR(11)	1	0	1658	1
Bin	DATA_ERR_CTR(10)	0	1	64	1
Bin	DATA_ERR_CTR(10)	1	0	1661	1
Bin	DATA_ERR_CTR(9)	0	1	75	1
Bin	DATA_ERR_CTR(9)	1	0	1673	1
Bin	DATA_ERR_CTR(8)	0	1	85	1
Bin	DATA_ERR_CTR(8)	1	0	1682	1
Bin	DATA_ERR_CTR(7)	0	1	98	1
Bin	DATA_ERR_CTR(7)	1	0	1696	1
Bin	DATA_ERR_CTR(6)	0	1	133	1
Bin	DATA_ERR_CTR(6)	1	0	1732	1
Bin	DATA_ERR_CTR(5)	0	1	209	1
Bin	DATA_ERR_CTR(5)	1	0	1805	1
Bin	DATA_ERR_CTR(4)	0	1	352	1
Bin	DATA_ERR_CTR(4)	1	0	1952	1
Bin	DATA_ERR_CTR(3)	0	1	680	1
Bin	DATA_ERR_CTR(3)	1	0	2278	1
Bin	DATA_ERR_CTR(2)	0	1	1295	1
Bin	DATA_ERR_CTR(2)	1	0	2895	1
Bin	DATA_ERR_CTR(1)	0	1	2523	1
Bin	DATA_ERR_CTR(1)	1	0	4120	1
Bin	DATA_ERR_CTR(0)	0	1	5589	1
Bin	DATA_ERR_CTR(0)	1	0	7187	1
Bin	ERR_TYPE(2)	0	1	800	1
Bin	ERR_TYPE(2)	1	0	2399	1
Bin	ERR_TYPE(1)	0	1	1263	1
Bin	ERR_TYPE(1)	1	0	2861	1
Bin	ERR_TYPE(0)	0	1	333	1
Bin	ERR_TYPE(0)	1	0	1933	1
Bin	ERR_ERP	0	1	295	1
Bin	ERR_ERP	1	0	1896	1
Bin	ERR_POS(3)	0	1	4188	1
Bin	ERR_POS(3)	1	0	2595	1
Bin	ERR_POS(2)	0	1	4427	1
Bin	ERR_POS(2)	1	0	2828	1
Bin	ERR_POS(1)	0	1	3627	1
Bin	ERR_POS(1)	1	0	2031	1
Bin	ERR_POS(0)	0	1	3049	1
Bin	ERR_POS(0)	1	0	1449	1
Bin	RETR_CTR(3)	0	1	55	1
Bin	RETR_CTR(3)	1	0	1656	1
Bin	RETR_CTR(2)	0	1	134	1
Bin	RETR_CTR(2)	1	0	1735	1
Bin	RETR_CTR(1)	0	1	265	1
Bin	RETR_CTR(1)	1	0	1866	1
Bin	RETR_CTR(0)	0	1	646	1
Bin	RETR_CTR(0)	1	0	2247	1
Bin	ALC_BIT(4)	0	1	69	1
Bin	ALC_BIT(4)	1	0	1668	1
Bin	ALC_BIT(3)	0	1	90	1
Bin	ALC_BIT(3)	1	0	1689	1
Bin	ALC_BIT(2)	0	1	103	1
Bin	ALC_BIT(2)	1	0	1702	1
Bin	ALC_BIT(1)	0	1	173	1
Bin	ALC_BIT(1)	1	0	1772	1
Bin	ALC_BIT(0)	0	1	299	1
Bin	ALC_BIT(0)	1	0	1898	1
Bin	ALC_ID_FIELD(2)	0	1	33	1
Bin	ALC_ID_FIELD(2)	1	0	1634	1
Bin	ALC_ID_FIELD(1)	0	1	42	1
Bin	ALC_ID_FIELD(1)	1	0	1641	1
Bin	ALC_ID_FIELD(0)	0	1	95	1
Bin	ALC_ID_FIELD(0)	1	0	1696	1
Bin	RX_FRAME_CTR(31)	0	1	50	1
Bin	RX_FRAME_CTR(31)	1	0	1649	1
Bin	RX_FRAME_CTR(30)	0	1	56	1
Bin	RX_FRAME_CTR(30)	1	0	1654	1
Bin	RX_FRAME_CTR(29)	0	1	51	1
Bin	RX_FRAME_CTR(29)	1	0	1648	1
Bin	RX_FRAME_CTR(28)	0	1	53	1
Bin	RX_FRAME_CTR(28)	1	0	1652	1
Bin	RX_FRAME_CTR(27)	0	1	47	1
Bin	RX_FRAME_CTR(27)	1	0	1646	1
Bin	RX_FRAME_CTR(26)	0	1	53	1
Bin	RX_FRAME_CTR(26)	1	0	1653	1
Bin	RX_FRAME_CTR(25)	0	1	51	1
Bin	RX_FRAME_CTR(25)	1	0	1649	1
Bin	RX_FRAME_CTR(24)	0	1	47	1
Bin	RX_FRAME_CTR(24)	1	0	1646	1
Bin	RX_FRAME_CTR(23)	0	1	53	1
Bin	RX_FRAME_CTR(23)	1	0	1651	1
Bin	RX_FRAME_CTR(22)	0	1	56	1
Bin	RX_FRAME_CTR(22)	1	0	1655	1
Bin	RX_FRAME_CTR(21)	0	1	50	1
Bin	RX_FRAME_CTR(21)	1	0	1650	1
Bin	RX_FRAME_CTR(20)	0	1	52	1
Bin	RX_FRAME_CTR(20)	1	0	1651	1
Bin	RX_FRAME_CTR(19)	0	1	50	1
Bin	RX_FRAME_CTR(19)	1	0	1649	1
Bin	RX_FRAME_CTR(18)	0	1	51	1
Bin	RX_FRAME_CTR(18)	1	0	1651	1
Bin	RX_FRAME_CTR(17)	0	1	52	1
Bin	RX_FRAME_CTR(17)	1	0	1652	1
Bin	RX_FRAME_CTR(16)	0	1	60	1
Bin	RX_FRAME_CTR(16)	1	0	1658	1
Bin	RX_FRAME_CTR(15)	0	1	50	1
Bin	RX_FRAME_CTR(15)	1	0	1649	1
Bin	RX_FRAME_CTR(14)	0	1	51	1
Bin	RX_FRAME_CTR(14)	1	0	1651	1
Bin	RX_FRAME_CTR(13)	0	1	46	1
Bin	RX_FRAME_CTR(13)	1	0	1647	1
Bin	RX_FRAME_CTR(12)	0	1	48	1
Bin	RX_FRAME_CTR(12)	1	0	1648	1
Bin	RX_FRAME_CTR(11)	0	1	53	1
Bin	RX_FRAME_CTR(11)	1	0	1651	1
Bin	RX_FRAME_CTR(10)	0	1	62	1
Bin	RX_FRAME_CTR(10)	1	0	1659	1
Bin	RX_FRAME_CTR(9)	0	1	55	1
Bin	RX_FRAME_CTR(9)	1	0	1654	1
Bin	RX_FRAME_CTR(8)	0	1	65	1
Bin	RX_FRAME_CTR(8)	1	0	1665	1
Bin	RX_FRAME_CTR(7)	0	1	79	1
Bin	RX_FRAME_CTR(7)	1	0	1678	1
Bin	RX_FRAME_CTR(6)	0	1	111	1
Bin	RX_FRAME_CTR(6)	1	0	1710	1
Bin	RX_FRAME_CTR(5)	0	1	220	1
Bin	RX_FRAME_CTR(5)	1	0	1820	1
Bin	RX_FRAME_CTR(4)	0	1	354	1
Bin	RX_FRAME_CTR(4)	1	0	1952	1
Bin	RX_FRAME_CTR(3)	0	1	751	1
Bin	RX_FRAME_CTR(3)	1	0	2351	1
Bin	RX_FRAME_CTR(2)	0	1	1498	1
Bin	RX_FRAME_CTR(2)	1	0	3095	1
Bin	RX_FRAME_CTR(1)	0	1	2960	1
Bin	RX_FRAME_CTR(1)	1	0	4559	1
Bin	RX_FRAME_CTR(0)	0	1	5900	1
Bin	RX_FRAME_CTR(0)	1	0	7500	1
Bin	TX_FRAME_CTR(31)	0	1	92	1
Bin	TX_FRAME_CTR(31)	1	0	1693	1
Bin	TX_FRAME_CTR(30)	0	1	102	1
Bin	TX_FRAME_CTR(30)	1	0	1703	1
Bin	TX_FRAME_CTR(29)	0	1	108	1
Bin	TX_FRAME_CTR(29)	1	0	1709	1
Bin	TX_FRAME_CTR(28)	0	1	102	1
Bin	TX_FRAME_CTR(28)	1	0	1703	1
Bin	TX_FRAME_CTR(27)	0	1	99	1
Bin	TX_FRAME_CTR(27)	1	0	1700	1
Bin	TX_FRAME_CTR(26)	0	1	111	1
Bin	TX_FRAME_CTR(26)	1	0	1712	1
Bin	TX_FRAME_CTR(25)	0	1	106	1
Bin	TX_FRAME_CTR(25)	1	0	1707	1
Bin	TX_FRAME_CTR(24)	0	1	108	1
Bin	TX_FRAME_CTR(24)	1	0	1709	1
Bin	TX_FRAME_CTR(23)	0	1	100	1
Bin	TX_FRAME_CTR(23)	1	0	1701	1
Bin	TX_FRAME_CTR(22)	0	1	99	1
Bin	TX_FRAME_CTR(22)	1	0	1700	1
Bin	TX_FRAME_CTR(21)	0	1	104	1
Bin	TX_FRAME_CTR(21)	1	0	1705	1
Bin	TX_FRAME_CTR(20)	0	1	104	1
Bin	TX_FRAME_CTR(20)	1	0	1705	1
Bin	TX_FRAME_CTR(19)	0	1	104	1
Bin	TX_FRAME_CTR(19)	1	0	1705	1
Bin	TX_FRAME_CTR(18)	0	1	95	1
Bin	TX_FRAME_CTR(18)	1	0	1696	1
Bin	TX_FRAME_CTR(17)	0	1	101	1
Bin	TX_FRAME_CTR(17)	1	0	1702	1
Bin	TX_FRAME_CTR(16)	0	1	95	1
Bin	TX_FRAME_CTR(16)	1	0	1696	1
Bin	TX_FRAME_CTR(15)	0	1	106	1
Bin	TX_FRAME_CTR(15)	1	0	1707	1
Bin	TX_FRAME_CTR(14)	0	1	105	1
Bin	TX_FRAME_CTR(14)	1	0	1706	1
Bin	TX_FRAME_CTR(13)	0	1	109	1
Bin	TX_FRAME_CTR(13)	1	0	1710	1
Bin	TX_FRAME_CTR(12)	0	1	110	1
Bin	TX_FRAME_CTR(12)	1	0	1711	1
Bin	TX_FRAME_CTR(11)	0	1	98	1
Bin	TX_FRAME_CTR(11)	1	0	1699	1
Bin	TX_FRAME_CTR(10)	0	1	105	1
Bin	TX_FRAME_CTR(10)	1	0	1706	1
Bin	TX_FRAME_CTR(9)	0	1	102	1
Bin	TX_FRAME_CTR(9)	1	0	1703	1
Bin	TX_FRAME_CTR(8)	0	1	105	1
Bin	TX_FRAME_CTR(8)	1	0	1706	1
Bin	TX_FRAME_CTR(7)	0	1	112	1
Bin	TX_FRAME_CTR(7)	1	0	1713	1
Bin	TX_FRAME_CTR(6)	0	1	110	1
Bin	TX_FRAME_CTR(6)	1	0	1711	1
Bin	TX_FRAME_CTR(5)	0	1	126	1
Bin	TX_FRAME_CTR(5)	1	0	1727	1
Bin	TX_FRAME_CTR(4)	0	1	154	1
Bin	TX_FRAME_CTR(4)	1	0	1755	1
Bin	TX_FRAME_CTR(3)	0	1	261	1
Bin	TX_FRAME_CTR(3)	1	0	1862	1
Bin	TX_FRAME_CTR(2)	0	1	603	1
Bin	TX_FRAME_CTR(2)	1	0	2204	1
Bin	TX_FRAME_CTR(1)	0	1	1075	1
Bin	TX_FRAME_CTR(1)	1	0	2676	1
Bin	TX_FRAME_CTR(0)	0	1	2217	1
Bin	TX_FRAME_CTR(0)	1	0	3818	1
Bin	BST_CTR(2)	0	1	33793	1
Bin	BST_CTR(2)	1	0	35393	1
Bin	BST_CTR(1)	0	1	71746	1
Bin	BST_CTR(1)	1	0	73346	1
Bin	BST_CTR(0)	0	1	142471	1
Bin	BST_CTR(0)	1	0	144071	1
Bin	DST_CTR(2)	0	1	117167	1
Bin	DST_CTR(2)	1	0	118766	1
Bin	DST_CTR(1)	0	1	243244	1
Bin	DST_CTR(1)	1	0	244841	1
Bin	DST_CTR(0)	0	1	487033	1
Bin	DST_CTR(0)	1	0	488629	1
Bin	STATUS_EWL	0	1	780	1
Bin	STATUS_EWL	1	0	2380	1

---

Port:

 PC_DBG

	Element	From	To	Count	Threshold
Bin	IS_SOF	0	1	25148	1
Bin	IS_SOF	1	0	26749	1
Bin	IS_ARBITRATION	0	1	55910	1
Bin	IS_ARBITRATION	1	0	57511	1
Bin	IS_CONTROL	0	1	51266	1
Bin	IS_CONTROL	1	0	52867	1
Bin	IS_DATA	0	1	36655	1
Bin	IS_DATA	1	0	38256	1
Bin	IS_STUFF_COUNT	0	1	13017	1
Bin	IS_STUFF_COUNT	1	0	14618	1
Bin	IS_CRC	0	1	31164	1
Bin	IS_CRC	1	0	32765	1
Bin	IS_CRC_DELIM	0	1	29702	1
Bin	IS_CRC_DELIM	1	0	31303	1
Bin	IS_ACK	0	1	29548	1
Bin	IS_ACK	1	0	31149	1
Bin	IS_ACK_DELIM	0	1	28120	1
Bin	IS_ACK_DELIM	1	0	29721	1
Bin	IS_EOF	0	1	27225	1
Bin	IS_EOF	1	0	28826	1
Bin	IS_OVERLOAD	0	1	529	1
Bin	IS_OVERLOAD	1	0	2130	1
Bin	IS_ERR	0	1	27358	1
Bin	IS_ERR	1	0	28953	1
Bin	IS_INTERMISSION	0	1	51904	1
Bin	IS_INTERMISSION	1	0	53504	1
Bin	IS_SUSPEND	0	1	2849	1
Bin	IS_SUSPEND	1	0	4450	1

---

Port:

 TRAN_FRAME_TEST

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	58	1
Bin	TPRM(4)	1	0	3273	1
Bin	TPRM(3)	0	1	189	1
Bin	TPRM(3)	1	0	1838	1
Bin	TPRM(2)	0	1	209	1
Bin	TPRM(2)	1	0	1858	1
Bin	TPRM(1)	0	1	431	1
Bin	TPRM(1)	1	0	2080	1
Bin	TPRM(0)	0	1	653	1
Bin	TPRM(0)	1	0	2302	1

---

Port:

 TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	25501	1
Bin	LOCK	1	0	27102	1
Bin	VALID	0	1	11115	1
Bin	VALID	1	0	12716	1
Bin	ERR	0	1	4269	1
Bin	ERR	1	0	5870	1
Bin	ARBL	0	1	455	1
Bin	ARBL	1	0	2056	1
Bin	FAILED	0	1	9651	1
Bin	FAILED	1	0	11252	1

---

Port:

 TXTB_CLK_EN

	From	To	Count	Threshold
Bin	0	1	80871	1
Bin	1	0	82472	1

---

Port:

 REC_IDENT

	Element	From	To	Count	Threshold
Bin	(28)	0	1	34977	1
Bin	(28)	1	0	30496	1
Bin	(27)	0	1	25797	1
Bin	(27)	1	0	19553	1
Bin	(26)	0	1	37882	1
Bin	(26)	1	0	32084	1
Bin	(25)	0	1	24607	1
Bin	(25)	1	0	19093	1
Bin	(24)	0	1	39861	1
Bin	(24)	1	0	33029	1
Bin	(23)	0	1	29050	1
Bin	(23)	1	0	21721	1
Bin	(22)	0	1	38673	1
Bin	(22)	1	0	32610	1
Bin	(21)	0	1	28017	1
Bin	(21)	1	0	21307	1
Bin	(20)	0	1	35404	1
Bin	(20)	1	0	30052	1
Bin	(19)	0	1	27909	1
Bin	(19)	1	0	21692	1
Bin	(18)	0	1	39548	1
Bin	(18)	1	0	33394	1
Bin	(17)	0	1	7607	1
Bin	(17)	1	0	74542	1
Bin	(16)	0	1	7853	1
Bin	(16)	1	0	75645	1
Bin	(15)	0	1	7230	1
Bin	(15)	1	0	73728	1
Bin	(14)	0	1	6467	1
Bin	(14)	1	0	72889	1
Bin	(13)	0	1	5983	1
Bin	(13)	1	0	71406	1
Bin	(12)	0	1	5952	1
Bin	(12)	1	0	71054	1
Bin	(11)	0	1	7821	1
Bin	(11)	1	0	75578	1
Bin	(10)	0	1	6986	1
Bin	(10)	1	0	73569	1
Bin	(9)	0	1	8103	1
Bin	(9)	1	0	76097	1
Bin	(8)	0	1	6851	1
Bin	(8)	1	0	73339	1
Bin	(7)	0	1	6667	1
Bin	(7)	1	0	72831	1
Bin	(6)	0	1	6776	1
Bin	(6)	1	0	73783	1
Bin	(5)	0	1	8585	1
Bin	(5)	1	0	77083	1
Bin	(4)	0	1	8155	1
Bin	(4)	1	0	76624	1
Bin	(3)	0	1	7407	1
Bin	(3)	1	0	74440	1
Bin	(2)	0	1	7143	1
Bin	(2)	1	0	74078	1
Bin	(1)	0	1	7990	1
Bin	(1)	1	0	75461	1
Bin	(0)	0	1	8801	1
Bin	(0)	1	0	77239	1

---

Port:

 REC_DLC

	Element	From	To	Count	Threshold
Bin	(3)	0	1	20131	1
Bin	(3)	1	0	58391	1
Bin	(2)	0	1	21272	1
Bin	(2)	1	0	26763	1
Bin	(1)	0	1	21528	1
Bin	(1)	1	0	26802	1
Bin	(0)	0	1	26961	1
Bin	(0)	1	0	33166	1

---

Port:

 REC_IDENT_TYPE

	From	To	Count	Threshold
Bin	0	1	18796	1
Bin	1	0	20395	1

---

Port:

 REC_FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	28449	1
Bin	1	0	30044	1

---

Port:

 REC_LBPF

	From	To	Count	Threshold
Bin	0	1	180	1
Bin	1	0	1781	1

---

Port:

 REC_IS_RTR

	From	To	Count	Threshold
Bin	0	1	23636	1
Bin	1	0	25235	1

---

Port:

 REC_BRS

	From	To	Count	Threshold
Bin	0	1	20049	1
Bin	1	0	21644	1

---

Port:

 REC_ESI

	From	To	Count	Threshold
Bin	0	1	2581	1
Bin	1	0	4181	1

---

Port:

 REC_IVLD

	From	To	Count	Threshold
Bin	0	1	51180	1
Bin	1	0	52772	1

---

Port:

 REC_VALID

	From	To	Count	Threshold
Bin	0	1	15149	1
Bin	1	0	16750	1

---

Port:

 STORE_METADATA

	From	To	Count	Threshold
Bin	0	1	28503	1
Bin	1	0	30104	1

---

Port:

 STORE_DATA

	From	To	Count	Threshold
Bin	0	1	88175	1
Bin	1	0	89776	1

---

Port:

 STORE_DATA_WORD

	Element	From	To	Count	Threshold
Bin	(31)	0	1	241881	1
Bin	(31)	1	0	243480	1
Bin	(30)	0	1	249246	1
Bin	(30)	1	0	250844	1
Bin	(29)	0	1	260271	1
Bin	(29)	1	0	261865	1
Bin	(28)	0	1	268608	1
Bin	(28)	1	0	270208	1
Bin	(27)	0	1	278547	1
Bin	(27)	1	0	280145	1
Bin	(26)	0	1	285999	1
Bin	(26)	1	0	287597	1
Bin	(25)	0	1	294448	1
Bin	(25)	1	0	296044	1
Bin	(24)	0	1	303485	1
Bin	(24)	1	0	305082	1
Bin	(23)	0	1	293024	1
Bin	(23)	1	0	294621	1
Bin	(22)	0	1	301366	1
Bin	(22)	1	0	302962	1
Bin	(21)	0	1	308903	1
Bin	(21)	1	0	310500	1
Bin	(20)	0	1	316916	1
Bin	(20)	1	0	318513	1
Bin	(19)	0	1	330277	1
Bin	(19)	1	0	331873	1
Bin	(18)	0	1	337604	1
Bin	(18)	1	0	339201	1
Bin	(17)	0	1	343625	1
Bin	(17)	1	0	345223	1
Bin	(16)	0	1	351617	1
Bin	(16)	1	0	353214	1
Bin	(15)	0	1	393220	1
Bin	(15)	1	0	394817	1
Bin	(14)	0	1	406974	1
Bin	(14)	1	0	408571	1
Bin	(13)	0	1	417088	1
Bin	(13)	1	0	418686	1
Bin	(12)	0	1	427426	1
Bin	(12)	1	0	429024	1
Bin	(11)	0	1	439739	1
Bin	(11)	1	0	441334	1
Bin	(10)	0	1	452521	1
Bin	(10)	1	0	454115	1
Bin	(9)	0	1	462227	1
Bin	(9)	1	0	463824	1
Bin	(8)	0	1	474822	1
Bin	(8)	1	0	476418	1
Bin	(7)	0	1	520277	1
Bin	(7)	1	0	521874	1
Bin	(6)	0	1	533435	1
Bin	(6)	1	0	535030	1
Bin	(5)	0	1	542598	1
Bin	(5)	1	0	544193	1
Bin	(4)	0	1	554073	1
Bin	(4)	1	0	555666	1
Bin	(3)	0	1	565790	1
Bin	(3)	1	0	567385	1
Bin	(2)	0	1	577333	1
Bin	(2)	1	0	578928	1
Bin	(1)	0	1	586688	1
Bin	(1)	1	0	588280	1
Bin	(0)	0	1	595853	1
Bin	(0)	1	0	597445	1

---

Port:

 REC_ABORT

	From	To	Count	Threshold
Bin	0	1	31526	1
Bin	1	0	33127	1

---

Port:

 SOF_PULSE

	From	To	Count	Threshold
Bin	0	1	81099	1
Bin	1	0	82700	1

---

Port:

 ARBITRATION_LOST

	From	To	Count	Threshold
Bin	0	1	1175	1
Bin	1	0	2776	1

---

Port:

 TRAN_VALID

	From	To	Count	Threshold
Bin	0	1	11115	1
Bin	1	0	12716	1

---

Port:

 BR_SHIFTED

	From	To	Count	Threshold
Bin	0	1	46598	1
Bin	1	0	48199	1

---

Port:

 ERR_DETECTED

	From	To	Count	Threshold
Bin	0	1	126203	1
Bin	1	0	127804	1

---

Port:

 FCS_CHANGED

	From	To	Count	Threshold
Bin	0	1	15993	1
Bin	1	0	17594	1

---

Port:

 ERR_WARNING_LIMIT_PULSE

	From	To	Count	Threshold
Bin	0	1	3160	1
Bin	1	0	4761	1

---

Port:

 SYNC_CONTROL

	Element	From	To	Count	Threshold
Bin	(1)	0	1	100135	1
Bin	(1)	1	0	100129	1
Bin	(0)	0	1	92433	1
Bin	(0)	1	0	92439	1

---

Port:

 NO_POS_RESYNC

	From	To	Count	Threshold
Bin	0	1	636881	1
Bin	1	0	638480	1

---

Port:

 SP_CONTROL

	Element	From	To	Count	Threshold
Bin	(1)	0	1	3751	1
Bin	(1)	1	0	5352	1
Bin	(0)	0	1	24995	1
Bin	(0)	1	0	26596	1

---

Port:

 NBT_CTRS_EN

	From	To	Count	Threshold
Bin	0	1	6483	1
Bin	1	0	8072	1

---

Port:

 DBT_CTRS_EN

	From	To	Count	Threshold
Bin	0	1	67683	1
Bin	1	0	69284	1

---

Port:

 TX_DATA_WBS

	From	To	Count	Threshold
Bin	0	1	638480	1
Bin	1	0	636881	1

---

Port:

 SSP_RESET

	From	To	Count	Threshold
Bin	0	1	32708	1
Bin	1	0	34309	1

---

Port:

 TRAN_DELAY_MEAS

	From	To	Count	Threshold
Bin	0	1	37635	1
Bin	1	0	39236	1

---

Port:

 BTMC_RESET

	From	To	Count	Threshold
Bin	0	1	28132	1
Bin	1	0	29733	1

---

Port:

 DBT_MEASURE_START

	From	To	Count	Threshold
Bin	0	1	2151	1
Bin	1	0	3752	1

---

Port:

 GEN_FIRST_SSP

	From	To	Count	Threshold
Bin	0	1	2151	1
Bin	1	0	3752	1

---

Port:

 BIT_ERR_ENABLE

	From	To	Count	Threshold
Bin	0	1	67584	1
Bin	1	0	65993	1

---

Port:

 PC_RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10401065	1
Bin	1	0	10402666	1

---

Signal:

 ALC_ALC_BIT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	69	1
Bin	(4)	1	0	1668	1
Bin	(3)	0	1	90	1
Bin	(3)	1	0	1689	1
Bin	(2)	0	1	103	1
Bin	(2)	1	0	1702	1
Bin	(1)	0	1	173	1
Bin	(1)	1	0	1772	1
Bin	(0)	0	1	299	1
Bin	(0)	1	0	1898	1

---

Signal:

 ALC_ALC_ID_FIELD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33	1
Bin	(2)	1	0	1634	1
Bin	(1)	0	1	42	1
Bin	(1)	1	0	1641	1
Bin	(0)	0	1	95	1
Bin	(0)	1	0	1696	1

---

Signal:

 ERR_CAPT_ERR_TYPE

	Element	From	To	Count	Threshold
Bin	(2)	0	1	800	1
Bin	(2)	1	0	2399	1
Bin	(1)	0	1	1263	1
Bin	(1)	1	0	2861	1
Bin	(0)	0	1	333	1
Bin	(0)	1	0	1933	1

---

Signal:

 ERR_CAPT_ERR_POS

	Element	From	To	Count	Threshold
Bin	(3)	0	1	4188	1
Bin	(3)	1	0	2595	1
Bin	(2)	0	1	4427	1
Bin	(2)	1	0	2828	1
Bin	(1)	0	1	3627	1
Bin	(1)	1	0	2031	1
Bin	(0)	0	1	3049	1
Bin	(0)	1	0	1449	1

---

Signal:

 ERR_CAPT_ERR_ERP

	From	To	Count	Threshold
Bin	0	1	295	1
Bin	1	0	1896	1

---

Signal:

 IS_TRANSMITTER

	From	To	Count	Threshold
Bin	0	1	20560	1
Bin	1	0	22161	1

---

Signal:

 IS_RECEIVER

	From	To	Count	Threshold
Bin	0	1	30873	1
Bin	1	0	32467	1

---

Signal:

 IS_IDLE

	From	To	Count	Threshold
Bin	0	1	56100	1
Bin	1	0	57697	1

---

Signal:

 ARBITRATION_LOST_I

	From	To	Count	Threshold
Bin	0	1	1175	1
Bin	1	0	2776	1

---

Signal:

 SET_TRANSMITTER

	From	To	Count	Threshold
Bin	0	1	40515	1
Bin	1	0	42116	1

---

Signal:

 SET_RECEIVER

	From	To	Count	Threshold
Bin	0	1	30450	1
Bin	1	0	32051	1

---

Signal:

 SET_IDLE

	From	To	Count	Threshold
Bin	0	1	96971	1
Bin	1	0	98572	1

---

Signal:

 IS_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	8426	1
Bin	1	0	8415	1

---

Signal:

 IS_ERR_PASSIVE

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	2372	1

---

Signal:

 IS_BUS_OFF_I

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8238	1

---

Signal:

 ERR_DETECTED_I

	From	To	Count	Threshold
Bin	0	1	126203	1
Bin	1	0	127804	1

---

Signal:

 PRIMARY_ERR

	From	To	Count	Threshold
Bin	0	1	22749	1
Bin	1	0	24350	1

---

Signal:

 ACT_ERR_OVR_FLAG

	From	To	Count	Threshold
Bin	0	1	19765	1
Bin	1	0	21364	1

---

Signal:

 ERR_DELIM_LATE

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1991	1

---

Signal:

 SET_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	6637	1
Bin	1	0	8238	1

---

Signal:

 ERR_CTRS_UNCHANGED

	From	To	Count	Threshold
Bin	0	1	800	1
Bin	1	0	2401	1

---

Signal:

 STUFF_ENABLE

	From	To	Count	Threshold
Bin	0	1	25501	1
Bin	1	0	27102	1

---

Signal:

 DESTUFF_ENABLE

	From	To	Count	Threshold
Bin	0	1	55951	1
Bin	1	0	57552	1

---

Signal:

 FIXED_STUFF

	From	To	Count	Threshold
Bin	0	1	13027	1
Bin	1	0	14628	1

---

Signal:

 TX_FRAME_NO_SOF

	From	To	Count	Threshold
Bin	0	1	353	1
Bin	1	0	1954	1

---

Signal:

 DST_CTR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	117167	1
Bin	(2)	1	0	118766	1
Bin	(1)	0	1	243244	1
Bin	(1)	1	0	244841	1
Bin	(0)	0	1	487033	1
Bin	(0)	1	0	488629	1

---

Signal:

 BST_CTR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33793	1
Bin	(2)	1	0	35393	1
Bin	(1)	0	1	71746	1
Bin	(1)	1	0	73346	1
Bin	(0)	0	1	142471	1
Bin	(0)	1	0	144071	1

---

Signal:

 STUFF_ERR

	From	To	Count	Threshold
Bin	0	1	20507	1
Bin	1	0	22108	1

---

Signal:

 CRC_ENABLE

	From	To	Count	Threshold
Bin	0	1	55951	1
Bin	1	0	57552	1

---

Signal:

 CRC_SPEC_ENABLE

	From	To	Count	Threshold
Bin	0	1	113871	1
Bin	1	0	115467	1

---

Signal:

 CRC_CALC_FROM_RX

	From	To	Count	Threshold
Bin	0	1	85112	1
Bin	1	0	86702	1

---

Signal:

 CRC_15

	Element	From	To	Count	Threshold
Bin	(14)	0	1	1464603	1
Bin	(14)	1	0	1466201	1
Bin	(13)	0	1	1414055	1
Bin	(13)	1	0	1415654	1
Bin	(12)	0	1	1426975	1
Bin	(12)	1	0	1428575	1
Bin	(11)	0	1	1440706	1
Bin	(11)	1	0	1442303	1
Bin	(10)	0	1	1457147	1
Bin	(10)	1	0	1458746	1
Bin	(9)	0	1	1452500	1
Bin	(9)	1	0	1454099	1
Bin	(8)	0	1	1468253	1
Bin	(8)	1	0	1469850	1
Bin	(7)	0	1	1492277	1
Bin	(7)	1	0	1493877	1
Bin	(6)	0	1	1438993	1
Bin	(6)	1	0	1440591	1
Bin	(5)	0	1	1451287	1
Bin	(5)	1	0	1452883	1
Bin	(4)	0	1	1465089	1
Bin	(4)	1	0	1466687	1
Bin	(3)	0	1	1462665	1
Bin	(3)	1	0	1464264	1
Bin	(2)	0	1	1454912	1
Bin	(2)	1	0	1456508	1
Bin	(1)	0	1	1468642	1
Bin	(1)	1	0	1470239	1
Bin	(0)	0	1	1481303	1
Bin	(0)	1	0	1482900	1

---

Signal:

 CRC_17

	Element	From	To	Count	Threshold
Bin	(16)	0	1	1741970	1
Bin	(16)	1	0	1743562	1
Bin	(15)	0	1	1764187	1
Bin	(15)	1	0	1765784	1
Bin	(14)	0	1	1780164	1
Bin	(14)	1	0	1781764	1
Bin	(13)	0	1	1765799	1
Bin	(13)	1	0	1767396	1
Bin	(12)	0	1	1705977	1
Bin	(12)	1	0	1707575	1
Bin	(11)	0	1	1721037	1
Bin	(11)	1	0	1722635	1
Bin	(10)	0	1	1670589	1
Bin	(10)	1	0	1672188	1
Bin	(9)	0	1	1684025	1
Bin	(9)	1	0	1685624	1
Bin	(8)	0	1	1696838	1
Bin	(8)	1	0	1698438	1
Bin	(7)	0	1	1711115	1
Bin	(7)	1	0	1712714	1
Bin	(6)	0	1	1725313	1
Bin	(6)	1	0	1726913	1
Bin	(5)	0	1	1725755	1
Bin	(5)	1	0	1727353	1
Bin	(4)	0	1	1738877	1
Bin	(4)	1	0	1740474	1
Bin	(3)	0	1	1759160	1
Bin	(3)	1	0	1760759	1
Bin	(2)	0	1	1733187	1
Bin	(2)	1	0	1734787	1
Bin	(1)	0	1	1749134	1
Bin	(1)	1	0	1750732	1
Bin	(0)	0	1	1770346	1
Bin	(0)	1	0	1771943	1

---

Signal:

 CRC_21

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1750548	1
Bin	(20)	1	0	1752139	1
Bin	(19)	0	1	1703965	1
Bin	(19)	1	0	1705564	1
Bin	(18)	0	1	1719889	1
Bin	(18)	1	0	1721489	1
Bin	(17)	0	1	1733300	1
Bin	(17)	1	0	1734899	1
Bin	(16)	0	1	1746057	1
Bin	(16)	1	0	1747657	1
Bin	(15)	0	1	1761040	1
Bin	(15)	1	0	1762637	1
Bin	(14)	0	1	1773792	1
Bin	(14)	1	0	1775388	1
Bin	(13)	0	1	1788103	1
Bin	(13)	1	0	1789698	1
Bin	(12)	0	1	1735619	1
Bin	(12)	1	0	1737217	1
Bin	(11)	0	1	1750649	1
Bin	(11)	1	0	1752247	1
Bin	(10)	0	1	1735803	1
Bin	(10)	1	0	1737400	1
Bin	(9)	0	1	1750856	1
Bin	(9)	1	0	1752454	1
Bin	(8)	0	1	1764927	1
Bin	(8)	1	0	1766523	1
Bin	(7)	0	1	1779762	1
Bin	(7)	1	0	1781362	1
Bin	(6)	0	1	1715511	1
Bin	(6)	1	0	1717109	1
Bin	(5)	0	1	1729494	1
Bin	(5)	1	0	1731092	1
Bin	(4)	0	1	1743073	1
Bin	(4)	1	0	1744671	1
Bin	(3)	0	1	1769789	1
Bin	(3)	1	0	1771385	1
Bin	(2)	0	1	1767065	1
Bin	(2)	1	0	1768664	1
Bin	(1)	0	1	1779026	1
Bin	(1)	1	0	1780626	1
Bin	(0)	0	1	1792348	1
Bin	(0)	1	0	1793943	1

---

Signal:

 SP_CONTROL_I

	Element	From	To	Count	Threshold
Bin	(1)	0	1	3751	1
Bin	(1)	1	0	5352	1
Bin	(0)	0	1	24995	1
Bin	(0)	1	0	26596	1

---

Signal:

 SP_CONTROL_Q

	Element	From	To	Count	Threshold
Bin	(1)	0	1	2174	1
Bin	(1)	1	0	3775	1
Bin	(0)	0	1	17875	1
Bin	(0)	1	0	19476	1

---

Signal:

 TRAN_VALID_I

	From	To	Count	Threshold
Bin	0	1	11115	1
Bin	1	0	12716	1

---

Signal:

 REC_VALID_I

	From	To	Count	Threshold
Bin	0	1	15149	1
Bin	1	0	16750	1

---

Signal:

 TX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	249	1
Bin	(8)	1	0	1850	1
Bin	(7)	0	1	517	1
Bin	(7)	1	0	2118	1
Bin	(6)	0	1	501	1
Bin	(6)	1	0	2102	1
Bin	(5)	0	1	805	1
Bin	(5)	1	0	2406	1
Bin	(4)	0	1	1933	1
Bin	(4)	1	0	3534	1
Bin	(3)	0	1	12743	1
Bin	(3)	1	0	14344	1
Bin	(2)	0	1	2955	1
Bin	(2)	1	0	4556	1
Bin	(1)	0	1	3324	1
Bin	(1)	1	0	4925	1
Bin	(0)	0	1	3524	1
Bin	(0)	1	0	5125	1

---

Signal:

 RX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	130	1
Bin	(8)	1	0	1731	1
Bin	(7)	0	1	350	1
Bin	(7)	1	0	1951	1
Bin	(6)	0	1	255	1
Bin	(6)	1	0	1854	1
Bin	(5)	0	1	363	1
Bin	(5)	1	0	1963	1
Bin	(4)	0	1	497	1
Bin	(4)	1	0	2098	1
Bin	(3)	0	1	685	1
Bin	(3)	1	0	2285	1
Bin	(2)	0	1	617	1
Bin	(2)	1	0	2218	1
Bin	(1)	0	1	1191	1
Bin	(1)	1	0	2792	1
Bin	(0)	0	1	11216	1
Bin	(0)	1	0	12809	1

---

Signal:

 NORM_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	69	1
Bin	(15)	1	0	1667	1
Bin	(14)	0	1	67	1
Bin	(14)	1	0	1668	1
Bin	(13)	0	1	64	1
Bin	(13)	1	0	1661	1
Bin	(12)	0	1	62	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	64	1
Bin	(11)	1	0	1664	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	1668	1
Bin	(9)	0	1	63	1
Bin	(9)	1	0	1662	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1671	1
Bin	(7)	0	1	75	1
Bin	(7)	1	0	1673	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1696	1
Bin	(5)	0	1	155	1
Bin	(5)	1	0	1752	1
Bin	(4)	0	1	276	1
Bin	(4)	1	0	1876	1
Bin	(3)	0	1	608	1
Bin	(3)	1	0	2205	1
Bin	(2)	0	1	1361	1
Bin	(2)	1	0	2958	1
Bin	(1)	0	1	3082	1
Bin	(1)	1	0	4678	1
Bin	(0)	0	1	11727	1
Bin	(0)	1	0	13323	1

---

Signal:

 DATA_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	63	1
Bin	(15)	1	0	1661	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1667	1
Bin	(13)	0	1	67	1
Bin	(13)	1	0	1665	1
Bin	(12)	0	1	65	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	61	1
Bin	(11)	1	0	1658	1
Bin	(10)	0	1	64	1
Bin	(10)	1	0	1661	1
Bin	(9)	0	1	75	1
Bin	(9)	1	0	1673	1
Bin	(8)	0	1	85	1
Bin	(8)	1	0	1682	1
Bin	(7)	0	1	98	1
Bin	(7)	1	0	1696	1
Bin	(6)	0	1	133	1
Bin	(6)	1	0	1732	1
Bin	(5)	0	1	209	1
Bin	(5)	1	0	1805	1
Bin	(4)	0	1	352	1
Bin	(4)	1	0	1952	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1295	1
Bin	(2)	1	0	2895	1
Bin	(1)	0	1	2523	1
Bin	(1)	1	0	4120	1
Bin	(0)	0	1	5589	1
Bin	(0)	1	0	7187	1

---

Signal:

 PC_TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11432038	1
Bin	1	0	11433636	1

---

Signal:

 PC_RX_TRIGGER_I

	From	To	Count	Threshold
Bin	0	1	10401065	1
Bin	1	0	10402666	1

---

Signal:

 PC_TX_DATA_NBS

	From	To	Count	Threshold
Bin	0	1	648446	1
Bin	1	0	646847	1

---

Signal:

 PC_RX_DATA_NBS

	From	To	Count	Threshold
Bin	0	1	1399537	1
Bin	1	0	1397936	1

---

Signal:

 CRC_DATA_TX_WBS

	From	To	Count	Threshold
Bin	0	1	638495	1
Bin	1	0	636896	1

---

Signal:

 CRC_DATA_TX_NBS

	From	To	Count	Threshold
Bin	0	1	648446	1
Bin	1	0	646847	1

---

Signal:

 CRC_DATA_RX_WBS

	From	To	Count	Threshold
Bin	0	1	1404357	1
Bin	1	0	1405947	1

---

Signal:

 CRC_DATA_RX_NBS

	From	To	Count	Threshold
Bin	0	1	1399537	1
Bin	1	0	1397936	1

---

Signal:

 CRC_TRIG_TX_WBS

	From	To	Count	Threshold
Bin	0	1	11464973	1
Bin	1	0	11466574	1

---

Signal:

 CRC_TRIG_TX_NBS

	From	To	Count	Threshold
Bin	0	1	11432038	1
Bin	1	0	11433636	1

---

Signal:

 CRC_TRIG_RX_WBS

	From	To	Count	Threshold
Bin	0	1	11346413	1
Bin	1	0	11348014	1

---

Signal:

 CRC_TRIG_RX_NBS

	From	To	Count	Threshold
Bin	0	1	10401065	1
Bin	1	0	10402666	1

---

Signal:

 BST_DATA_IN

	From	To	Count	Threshold
Bin	0	1	648446	1
Bin	1	0	646847	1

---

Signal:

 BST_DATA_OUT

	From	To	Count	Threshold
Bin	0	1	638495	1
Bin	1	0	636896	1

---

Signal:

 BST_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11432038	1
Bin	1	0	11433636	1

---

Signal:

 DATA_HALT

	From	To	Count	Threshold
Bin	0	1	947582	1
Bin	1	0	949183	1

---

Signal:

 BDS_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1410211	1
Bin	1	0	1408610	1

---

Signal:

 BDS_DATA_OUT

	From	To	Count	Threshold
Bin	0	1	1399537	1
Bin	1	0	1397936	1

---

Signal:

 BDS_TRIGGER

	From	To	Count	Threshold
Bin	0	1	22860061	1
Bin	1	0	22861662	1

---

Signal:

 DESTUFFED

	From	To	Count	Threshold
Bin	0	1	1022144	1
Bin	1	0	1023745	1

---

Signal:

 TX_FRAME_CTR

	Element	From	To	Count	Threshold
Bin	(31)	0	1	92	1
Bin	(31)	1	0	1693	1
Bin	(30)	0	1	102	1
Bin	(30)	1	0	1703	1
Bin	(29)	0	1	108	1
Bin	(29)	1	0	1709	1
Bin	(28)	0	1	102	1
Bin	(28)	1	0	1703	1
Bin	(27)	0	1	99	1
Bin	(27)	1	0	1700	1
Bin	(26)	0	1	111	1
Bin	(26)	1	0	1712	1
Bin	(25)	0	1	106	1
Bin	(25)	1	0	1707	1
Bin	(24)	0	1	108	1
Bin	(24)	1	0	1709	1
Bin	(23)	0	1	100	1
Bin	(23)	1	0	1701	1
Bin	(22)	0	1	99	1
Bin	(22)	1	0	1700	1
Bin	(21)	0	1	104	1
Bin	(21)	1	0	1705	1
Bin	(20)	0	1	104	1
Bin	(20)	1	0	1705	1
Bin	(19)	0	1	104	1
Bin	(19)	1	0	1705	1
Bin	(18)	0	1	95	1
Bin	(18)	1	0	1696	1
Bin	(17)	0	1	101	1
Bin	(17)	1	0	1702	1
Bin	(16)	0	1	95	1
Bin	(16)	1	0	1696	1
Bin	(15)	0	1	106	1
Bin	(15)	1	0	1707	1
Bin	(14)	0	1	105	1
Bin	(14)	1	0	1706	1
Bin	(13)	0	1	109	1
Bin	(13)	1	0	1710	1
Bin	(12)	0	1	110	1
Bin	(12)	1	0	1711	1
Bin	(11)	0	1	98	1
Bin	(11)	1	0	1699	1
Bin	(10)	0	1	105	1
Bin	(10)	1	0	1706	1
Bin	(9)	0	1	102	1
Bin	(9)	1	0	1703	1
Bin	(8)	0	1	105	1
Bin	(8)	1	0	1706	1
Bin	(7)	0	1	112	1
Bin	(7)	1	0	1713	1
Bin	(6)	0	1	110	1
Bin	(6)	1	0	1711	1
Bin	(5)	0	1	126	1
Bin	(5)	1	0	1727	1
Bin	(4)	0	1	154	1
Bin	(4)	1	0	1755	1
Bin	(3)	0	1	261	1
Bin	(3)	1	0	1862	1
Bin	(2)	0	1	603	1
Bin	(2)	1	0	2204	1
Bin	(1)	0	1	1075	1
Bin	(1)	1	0	2676	1
Bin	(0)	0	1	2217	1
Bin	(0)	1	0	3818	1

---

Signal:

 RX_FRAME_CTR

	Element	From	To	Count	Threshold
Bin	(31)	0	1	50	1
Bin	(31)	1	0	1649	1
Bin	(30)	0	1	56	1
Bin	(30)	1	0	1654	1
Bin	(29)	0	1	51	1
Bin	(29)	1	0	1648	1
Bin	(28)	0	1	53	1
Bin	(28)	1	0	1652	1
Bin	(27)	0	1	47	1
Bin	(27)	1	0	1646	1
Bin	(26)	0	1	53	1
Bin	(26)	1	0	1653	1
Bin	(25)	0	1	51	1
Bin	(25)	1	0	1649	1
Bin	(24)	0	1	47	1
Bin	(24)	1	0	1646	1
Bin	(23)	0	1	53	1
Bin	(23)	1	0	1651	1
Bin	(22)	0	1	56	1
Bin	(22)	1	0	1655	1
Bin	(21)	0	1	50	1
Bin	(21)	1	0	1650	1
Bin	(20)	0	1	52	1
Bin	(20)	1	0	1651	1
Bin	(19)	0	1	50	1
Bin	(19)	1	0	1649	1
Bin	(18)	0	1	51	1
Bin	(18)	1	0	1651	1
Bin	(17)	0	1	52	1
Bin	(17)	1	0	1652	1
Bin	(16)	0	1	60	1
Bin	(16)	1	0	1658	1
Bin	(15)	0	1	50	1
Bin	(15)	1	0	1649	1
Bin	(14)	0	1	51	1
Bin	(14)	1	0	1651	1
Bin	(13)	0	1	46	1
Bin	(13)	1	0	1647	1
Bin	(12)	0	1	48	1
Bin	(12)	1	0	1648	1
Bin	(11)	0	1	53	1
Bin	(11)	1	0	1651	1
Bin	(10)	0	1	62	1
Bin	(10)	1	0	1659	1
Bin	(9)	0	1	55	1
Bin	(9)	1	0	1654	1
Bin	(8)	0	1	65	1
Bin	(8)	1	0	1665	1
Bin	(7)	0	1	79	1
Bin	(7)	1	0	1678	1
Bin	(6)	0	1	111	1
Bin	(6)	1	0	1710	1
Bin	(5)	0	1	220	1
Bin	(5)	1	0	1820	1
Bin	(4)	0	1	354	1
Bin	(4)	1	0	1952	1
Bin	(3)	0	1	751	1
Bin	(3)	1	0	2351	1
Bin	(2)	0	1	1498	1
Bin	(2)	1	0	3095	1
Bin	(1)	0	1	2960	1
Bin	(1)	1	0	4559	1
Bin	(0)	0	1	5900	1
Bin	(0)	1	0	7500	1

---

Signal:

 TX_DATA_WBS_I

	From	To	Count	Threshold
Bin	0	1	638480	1
Bin	1	0	636881	1

---

Signal:

 LPB_DOMINANT

	From	To	Count	Threshold
Bin	0	1	1403806	1
Bin	1	0	1402207	1

---

Signal:

 FORM_ERR

	From	To	Count	Threshold
Bin	0	1	89135	1
Bin	1	0	90736	1

---

Signal:

 ACK_ERR

	From	To	Count	Threshold
Bin	0	1	8278	1
Bin	1	0	9879	1

---

Signal:

 CRC_ERR

	From	To	Count	Threshold
Bin	0	1	1618	1
Bin	1	0	3219	1

---

Signal:

 LOAD_INIT_VECT

	From	To	Count	Threshold
Bin	0	1	113844	1
Bin	1	0	115445	1

---

Signal:

 RETR_CTR

	Element	From	To	Count	Threshold
Bin	(3)	0	1	55	1
Bin	(3)	1	0	1656	1
Bin	(2)	0	1	134	1
Bin	(2)	1	0	1735	1
Bin	(1)	0	1	265	1
Bin	(1)	1	0	1866	1
Bin	(0)	0	1	646	1
Bin	(0)	1	0	2247	1

---

Signal:

 DECREMENT_REC

	From	To	Count	Threshold
Bin	0	1	14952	1
Bin	1	0	16553	1

---

Signal:

 BIT_ERR_AFTER_ACK_ERR

	From	To	Count	Threshold
Bin	0	1	8	1
Bin	1	0	1609	1

---

Signal:

 MR_STATUS_PEXS

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1676	1

---

Signal:

 MR_STATUS_EWL

	From	To	Count	Threshold
Bin	0	1	780	1
Bin	1	0	2380	1